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| revision date: jan. 18, 2008 32 renesas 32-bit risc microcomputer superh tm risc engine family / sh7700 series sh7720 group hd6417720 hd6417320 SH7721 group r8a77210 r8a77211 rev.3.00 rej09b0033-0300 sh7720 group , SH7721 group hardware manual
rev. 3.00 jan. 18, 2008 page ii of lxii rev. 3.00 jan. 18, 2008 page iii of lxii 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes regarding these materials rev. 3.00 jan. 18, 2008 page iv of lxii general precautions on handling of product 1. treatment of nc pins note: do not connect anything to the nc pins. the nc (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. if something is connected to the nc pins, the operation of the lsi is not guaranteed. 2. treatment of unused input pins note: fix all unused input pins to high or low level. generally, the input pins of cmos products are high-impedance input pins. if unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a pass- through current flows internally, and a malfunction may occur. 3. processing before initialization note: when power is first supplied, the product's state is undefined. the states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pi n. during the period where the states are undefined, the register settings and the output state of each pin are also undefined. design your system so that it does not malfunction because of processing while it is in this undefined state. for those products which have a reset function, reset the lsi immediately after the power supply has been turned on. 4. prohibition of access to undefined or reserved addresses note: access to undefined or reserved addresses is prohibited. the undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresse s. do not access these registers; the system's operation is not guaranteed if they are accessed. rev. 3.00 jan. 18, 2008 page v of lxii configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic styl e includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includ es this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions and additions in this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents . for details, see the actual locations in this manual. 11. index rev. 3.00 jan. 18, 2008 page vi of lxii preface the sh7720 or SH7721 group risc (reduced instruction set computer) microcomputer includes a renesas technology original risc cp u as its core, and the peripheral functions required to configure a system. target users: this manual was written for users who will be using this lsi in the design of application systems. user s of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardwa re functions and electrical characteristics of this lsi to the above users. refer to the sh-3/sh-3e/sh3-dsp software manual for a detailed description of the instruction set. notes on reading this manual: ? product names the following products are covered in this manual. product classifications and abbreviations basic classification product code sh7720 group hd6417720, hd6417320 SH7721 group r8a77210, r8a77211 ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, periph eral functions, and elect rical characteristics. ? in order to understand the details of the cpu's functions read the sh-3/sh-3e/sh3-dsp software manual. rev. 3.00 jan. 18, 2008 page vii of lxii rules: register name: the following notatio n is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb (most significant bit) is on the left and the lsb (least significant bit) is on the right. number notation: binary is b'xx, hexadecimal is h'xxxx, decimal is xxxx. signal notation: an overbar is added to a low-active signal: xxxx related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ sh7720 or SH7721 group manuals: document title document no. sh7720/SH7721 group hardware manual this manual sh-3/sh-3e/sh3-dsp software manual rej09b0317 users manuals for development tools: document title document no. super tm risc engine c/c++ compiler, assembler, optimizing linkage editor compiler package v.9.00 user's manual rej10b0152 superh tm risc engine high-performance embedded workshop 3 user's manual rej10b0025 superh tm risc engine high-performance embedded workshop 3 tutorial rej10b0023 application note: document title document no. superh tm risc engine c/c++ compiler package application note rej05b0463 rev. 3.00 jan. 18, 2008 page viii of lxii abbreviations adc analog to digital converter alu arithmetic logic unit ase adaptive system evaluator asid address space identifier aud advanced user debugger bcd binary coded decimal bps bit per second bsc bus state controller ccn cache memory controller cmt compare match timer cpg clock pulse generator cpu central processing unit des data encryption standard dmac direct memory access controller etu elementary time unit fifo first-in first-out hi-z high impedance h-udi user debugging interface intc interrupt controller irda infrared data association jtag joint test action group lqfp low profile qfp lru least recently used lsb least significant bit mmu memory management unit mpx multiplex msb most significant bit pc program counter pfc pin function controller pll phase locked loop pwm pulse width modulation ram random access memory risc reduced instruction set computer rev. 3.00 jan. 18, 2008 page ix of lxii rom read only memory rsa rivest shamir adleman rtc real time clock scif serial communica tion interface with fifo sdhi sd host interface sdram synchronous dram ssl secure socket layer tap test access port t.b.d to be determined tlb translation lookaside buffer tmu timer unit tpu timer pulse unit uart universal asynchronou s receiver/transmitter ubc user break controller usb universal serial bus wdt watchdog timer all trademarks and registered trademarks ar e the property of th eir respective owners. rev. 3.00 jan. 18, 2008 page x of lxii rev. 3.00 jan. 18, 2008 page xi of lxii contents section 1 overview..................................................................................................1 1.1 features....................................................................................................................... ........... 1 1.2 block diagram .................................................................................................................. ... 10 1.3 pin assign ments................................................................................................................ ... 10 1.3.1 pin assign ments ..................................................................................................... 10 1.3.2 pin functions .......................................................................................................... 25 section 2 cpu........................................................................................................37 2.1 processing states and processing modes ............................................................................. 37 2.1.1 processing states..................................................................................................... 37 2.1.2 processing modes ................................................................................................... 38 2.2 memory map ..................................................................................................................... .. 39 2.2.1 virtual addr ess space............................................................................................. 39 2.2.2 external memory space.......................................................................................... 40 2.3 register de scriptions .......................................................................................................... .42 2.3.1 general registers.................................................................................................... 45 2.3.2 system regi sters..................................................................................................... 46 2.3.3 program counter..................................................................................................... 47 2.3.4 control registers .................................................................................................... 48 2.4 data formats................................................................................................................... ..... 51 2.4.1 register data format .............................................................................................. 51 2.4.2 memory data formats ............................................................................................ 52 2.5 features of cpu co re instructions ...................................................................................... 54 2.5.1 instruction exec ution method................................................................................. 54 2.5.2 cpu instruction addr essing modes ....................................................................... 56 2.5.3 instruction formats ................................................................................................. 60 2.6 instruction set ................................................................................................................ ...... 63 2.6.1 instruction set base d on functions......................................................................... 63 2.6.2 operation c ode map............................................................................................... 77 section 3 dsp operating unit ...............................................................................81 3.1 dsp extended functio ns ..................................................................................................... 81 3.2 dsp mode re sources .......................................................................................................... 83 3.2.1 processing modes ................................................................................................... 83 3.2.2 dsp mode memo ry map........................................................................................ 83 3.2.3 cpu register sets................................................................................................... 84 rev. 3.00 jan. 18, 2008 page xii of lxii 3.2.4 dsp registers ......................................................................................................... 88 3.3 cpu extended instructions.................................................................................................. 89 3.3.1 dsp repeat control................................................................................................ 89 3.4 dsp data transfer instructio ns ......................................................................................... 100 3.4.1 general registers.................................................................................................. 104 3.4.2 dsp data addr essing ........................................................................................... 106 3.4.3 modulo addr essing .............................................................................................. 108 3.4.4 memory data formats .......................................................................................... 110 3.4.5 instruction formats of double and single transfer instructions .......................... 111 3.5 dsp data operation instructio ns....................................................................................... 113 3.5.1 dsp regist ers ....................................................................................................... 113 3.5.2 dsp operation inst ruction se t.............................................................................. 118 3.5.3 dsp-type data formats....................................................................................... 123 3.5.4 alu fixed-point arithme tic operations.............................................................. 125 3.5.5 alu integer operations ....................................................................................... 131 3.5.6 alu logical operations ...................................................................................... 133 3.5.7 fixed-point multiply operation............................................................................ 135 3.5.8 shift opera tions .................................................................................................... 137 3.5.9 most significant bit de tection oper ation ............................................................ 141 3.5.10 rounding operation.............................................................................................. 144 3.5.11 overflow protection.............................................................................................. 146 3.5.12 local data move instruction ................................................................................ 147 3.5.13 operand conflict .................................................................................................. 148 3.6 dsp extended function instruction set............................................................................. 149 3.6.1 cpu extended in structions................................................................................... 149 3.6.2 double-data transfer instructions ....................................................................... 151 3.6.3 single-data transfer instruct ions ......................................................................... 152 3.6.4 dsp operation in structions .................................................................................. 154 3.6.5 operation code map in dsp mode ...................................................................... 160 section 4 memory management unit (mmu).................................................... 165 4.1 role of mmu .................................................................................................................... 165 4.1.1 mmu of this lsi................................................................................................. 168 4.2 register desc riptions......................................................................................................... 1 74 4.2.1 page table entry regist er high (pteh).............................................................. 174 4.2.2 page table entry regi ster low (ptel) ............................................................... 175 4.2.3 translation table base register (ttb) ................................................................ 175 4.2.4 mmu control regist er (mmucr) ...................................................................... 175 4.3 tlb functions .................................................................................................................. .177 4.3.1 configuration of the tlb ..................................................................................... 177 rev. 3.00 jan. 18, 2008 page xiii of lxii 4.3.2 tlb indexing........................................................................................................ 179 4.3.3 tlb address co mparison .................................................................................... 180 4.3.4 page management information............................................................................. 182 4.4 mmu functions................................................................................................................. 1 83 4.4.1 mmu hardware management .............................................................................. 183 4.4.2 mmu software management ............................................................................... 184 4.4.3 mmu instruction (ldtlb).................................................................................. 184 4.4.4 avoiding synonym problems ............................................................................... 186 4.5 mmu excepti ons............................................................................................................... 18 8 4.5.1 tlb miss exce ption............................................................................................. 188 4.5.2 tlb protection viola tion exceptio n .................................................................... 189 4.5.3 tlb invalid ex ception ......................................................................................... 190 4.5.4 initial page write exception................................................................................. 191 4.5.5 mmu exception in repeat lo op.......................................................................... 192 4.6 memory-mappe d tlb....................................................................................................... 194 4.6.1 address array ....................................................................................................... 194 4.6.2 data array ............................................................................................................ 194 4.6.3 usage examples.................................................................................................... 196 4.7 usage note..................................................................................................................... .... 196 section 5 cache ...................................................................................................197 5.1 features....................................................................................................................... ....... 197 5.1.1 cache struct ure..................................................................................................... 197 5.2 register desc riptions ......................................................................................................... 1 99 5.2.1 cache control regist er 1 (ccr1) ........................................................................ 200 5.2.2 cache control regist er 2 (ccr2) ........................................................................ 201 5.2.3 cache control regist er 3 (ccr3) ........................................................................ 204 5.3 operation ...................................................................................................................... ..... 205 5.3.1 searching the cache.............................................................................................. 205 5.3.2 read acces s.......................................................................................................... 207 5.3.3 prefetch operation ................................................................................................ 207 5.3.4 write acces s ......................................................................................................... 207 5.3.5 write-back buffer ................................................................................................ 208 5.3.6 coherency of cache and external memory .......................................................... 208 5.4 memory-mapped cache .................................................................................................... 209 5.4.1 address array ....................................................................................................... 209 5.4.2 data array ............................................................................................................ 210 5.4.3 usage examples.................................................................................................... 212 rev. 3.00 jan. 18, 2008 page xiv of lxii section 6 x/y memory ....................................................................................... 213 6.1 features....................................................................................................................... ....... 213 6.2 operation ...................................................................................................................... ..... 214 6.2.1 access from cpu ................................................................................................. 214 6.2.2 access from dsp.................................................................................................. 214 6.2.3 access from bus ma ster modu le.......................................................................... 215 6.3 usage notes .................................................................................................................... ... 215 6.3.1 page conflict ........................................................................................................ 215 6.3.2 bus conflic t .......................................................................................................... 215 6.3.3 mmu and cache settings..................................................................................... 216 6.3.4 sleep mode ........................................................................................................... 216 section 7 exception handling ............................................................................. 217 7.1 register desc riptions......................................................................................................... 2 17 7.1.1 trapa exception regi ster (tra) ...................................................................... 218 7.1.2 exception event regi ster (expevt)................................................................... 219 7.1.3 interrupt event regi ster (intevt)...................................................................... 219 7.1.4 interrupt event regist er 2 (intevt2)................................................................. 220 7.1.5 exception address re gister ( tea) ...................................................................... 220 7.2 exception handlin g function ............................................................................................ 221 7.2.1 exception hand ling flow ..................................................................................... 221 7.2.2 exception vector addresses................................................................................. 222 7.2.3 exception c odes ................................................................................................... 222 7.2.4 exception request and bl bit (mu ltiple exception pr evention) ......................... 222 7.2.5 exception source acceptance timing and pr iority .............................................. 223 7.3 individual exceptio n operatio ns ....................................................................................... 227 7.3.1 resets .................................................................................................................... 227 7.3.2 general exceptions............................................................................................... 227 7.3.3 general exceptions ( mmu exceptions)............................................................... 231 7.4 exception processing while dsp ex tension function is valid......................................... 234 7.4.1 illegal instruction exception and illega l slot instruction exception .................... 234 7.4.2 cpu address error ............................................................................................... 234 7.4.3 exception in repeat control pe riod ..................................................................... 234 7.5 usage notes .................................................................................................................... ... 241 section 8 interrupt controller (intc)................................................................. 243 8.1 features....................................................................................................................... ....... 243 8.2 input/output pins.............................................................................................................. .245 8.3 register desc riptions......................................................................................................... 2 46 rev. 3.00 jan. 18, 2008 page xv of lxii 8.3.1 interrupt priority registers a to j (ipra to iprj)................................................ 247 8.3.2 interrupt control regi ster 0 (i cr0)...................................................................... 249 8.3.3 interrupt control regi ster 1 (i cr1)...................................................................... 250 8.3.4 interrupt request regi ster 0 (irr0) ..................................................................... 252 8.3.5 interrupt request regi ster 1 (irr1) ..................................................................... 253 8.3.6 interrupt request regi ster 2 (irr2) ..................................................................... 254 8.3.7 interrupt request regi ster 3 (irr3) ..................................................................... 255 8.3.8 interrupt request regi ster 4 (irr4) ..................................................................... 256 8.3.9 interrupt request regi ster 5 (irr5) ..................................................................... 257 8.3.10 interrupt request regi ster 6 (irr6) ..................................................................... 259 8.3.11 interrupt request regi ster 7 (irr7) ..................................................................... 260 8.3.12 interrupt request regi ster 8 (irr8) ..................................................................... 261 8.3.13 interrupt request regi ster 9 (irr9) ..................................................................... 262 8.3.14 pint interrupt enable register (pinter)........................................................... 264 8.3.15 interrupt control regi ster 2 (i cr2)...................................................................... 265 8.4 interrupt sources.............................................................................................................. .. 266 8.4.1 nmi interrupt........................................................................................................ 266 8.4.2 irq interr upts ....................................................................................................... 266 8.4.3 irl interr upts........................................................................................................ 267 8.4.4 pint interrupts ..................................................................................................... 268 8.4.5 on-chip peripheral mo dule interr upts ................................................................. 268 8.4.6 interrupt exception hand ling and prio rity............................................................ 269 8.5 operation ...................................................................................................................... ..... 276 8.5.1 interrupt sequence ................................................................................................ 276 8.5.2 multiple interrupts ................................................................................................ 278 section 9 bus state controller (bsc)..................................................................279 9.1 features....................................................................................................................... ....... 279 9.2 input/output pins .............................................................................................................. .283 9.3 area overview .................................................................................................................. .285 9.3.1 area division........................................................................................................ 285 9.3.2 shadow area......................................................................................................... 285 9.3.3 address ma p ......................................................................................................... 287 9.3.4 area 0 memory type and memory bus width .................................................... 289 9.3.5 data alignm ent..................................................................................................... 289 9.4 register desc riptions ......................................................................................................... 2 90 9.4.1 common control regi ster (cmncr) .................................................................. 291 9.4.2 csn space bus control register (c snbcr) ........................................................ 294 9.4.3 csn space wait control re gister (csnwcr) ..................................................... 299 9.4.4 sdram control regi ster (sd cr)....................................................................... 325 rev. 3.00 jan. 18, 2008 page xvi of lxii 9.4.5 refresh timer control/statu s register (r tcsr)................................................. 328 9.4.6 refresh timer coun ter (rtcnt)......................................................................... 329 9.4.7 refresh time constant register (rtcor) .......................................................... 330 9.4.8 sdram mode registers 2, 3 (sdmr2 and srmr3) ......................................... 330 9.5 operation ...................................................................................................................... ..... 331 9.5.1 endian/access size and da ta alignment.............................................................. 331 9.5.2 normal space interface ........................................................................................ 337 9.5.3 access wait control ............................................................................................. 343 9.5.4 csn assert period expansion ............................................................................... 345 9.5.5 sdram interface ................................................................................................. 346 9.5.6 burst rom (clock asynch ronous) interface ....................................................... 385 9.5.7 byte-selection sram interface ........................................................................... 387 9.5.8 pcmcia inte rface................................................................................................ 392 9.5.9 burst rom (clock sync hronous) interface.......................................................... 400 9.5.10 wait between acce ss cycles ................................................................................ 401 9.5.11 bus arbitrat ion ..................................................................................................... 401 9.6 usage notes .................................................................................................................... ... 404 section 10 direct memory access controller (dmac)..................................... 407 10.1 features....................................................................................................................... ....... 407 10.2 input/output pins.............................................................................................................. .409 10.3 register desc riptions......................................................................................................... 4 10 10.3.1 dma source address register s (sar_0 to sar_5) ........................................... 411 10.3.2 dma destination address regist ers (dar_0 to dar_5) .................................. 412 10.3.3 dma transfer count registers (dmatcr_0 to dmatcr_5) ......................... 412 10.3.4 dma channel control register s (chcr_0 to chcr_5) ................................... 413 10.3.5 dma operation regist er (dmaor) ................................................................... 418 10.3.6 dma extended resource selectors 0 to 2 (dmars0 to dmars2)................... 420 10.4 operation ...................................................................................................................... ..... 424 10.4.1 dma transfer flow ............................................................................................. 424 10.4.2 dma transfer requests ....................................................................................... 426 10.4.3 channel prio rity.................................................................................................... 431 10.4.4 dma transfer types............................................................................................ 434 10.4.5 number of bus cycle states and dreq pin sampli ng timing ........................... 444 10.5 usage notes .................................................................................................................... ... 448 10.5.1 notes on dack pin output ................................................................................. 448 10.5.2 notes on the cases when dack is divided........................................................ 448 10.5.3 other notes........................................................................................................... 452 rev. 3.00 jan. 18, 2008 page xvii of lxii section 11 clock pulse generator (cpg)............................................................453 11.1 features....................................................................................................................... ....... 453 11.2 input/output pins .............................................................................................................. .457 11.3 clock operatin g modes ..................................................................................................... 458 11.4 register desc riptions ......................................................................................................... 4 61 11.4.1 frequency control re gister (f rqcr) ................................................................. 461 11.4.2 usbh/usbf clock control register (u clkcr) ............................................... 464 11.5 changing frequency .......................................................................................................... 465 11.5.1 changing multipli cation ra te............................................................................... 465 11.5.2 changing divisi on ratio....................................................................................... 465 11.6 usage notes .................................................................................................................... ... 466 11.7 notes on boar d design ...................................................................................................... 466 section 12 watchdog timer (wdt)....................................................................469 12.1 features....................................................................................................................... ....... 469 12.2 register descripti ons for wdt ......................................................................................... 471 12.2.1 watchdog timer coun ter (wtcnt).................................................................... 471 12.2.2 watchdog timer control/statu s register (w tcsr)............................................ 471 12.2.3 notes on regist er access...................................................................................... 473 12.3 wdt opera tion ................................................................................................................. 4 74 12.3.1 canceling software standbys ............................................................................... 474 12.3.2 changing frequency ............................................................................................. 475 12.3.3 using watchdog ti mer mode .............................................................................. 475 12.3.4 using interval timer mode .................................................................................. 476 section 13 power-down modes ..........................................................................477 13.1 features....................................................................................................................... ....... 477 13.1.1 power-down modes ............................................................................................. 477 13.1.2 reset ..................................................................................................................... 478 13.2 input/output pins .............................................................................................................. .479 13.3 register desc riptions ......................................................................................................... 4 80 13.3.1 standby control regi ster (st bcr)...................................................................... 480 13.3.2 standby control regist er 2 (st bcr2)................................................................. 481 13.3.3 standby control regist er 3 (st bcr3)................................................................. 483 13.3.4 standby control regist er 4 (st bcr4)................................................................. 484 13.3.5 standby control regist er 5 (st bcr5)................................................................. 486 13.4 sleep mode ..................................................................................................................... ... 488 13.4.1 transition to sl eep mode...................................................................................... 488 13.4.2 canceling slee p mode .......................................................................................... 488 rev. 3.00 jan. 18, 2008 page xviii of lxii 13.5 software sta ndby mode ..................................................................................................... 489 13.5.1 transition to software standby mode .................................................................. 489 13.5.2 canceling software standby m ode ...................................................................... 489 13.6 module standby function.................................................................................................. 491 13.6.1 transition to module standby function ............................................................... 491 13.6.2 canceling module stan dby function.................................................................... 491 13.7 status pin chan ge timing ............................................................................................ 492 13.7.1 reset ..................................................................................................................... 492 13.7.2 software sta ndby mode ........................................................................................ 493 13.7.3 sleep mode ........................................................................................................... 494 13.8 hardware stan dby mode ................................................................................................... 496 13.8.1 transition to hardware standby mode................................................................. 496 13.8.2 canceling the hardware standby mode ............................................................... 496 13.8.3 hardware standby mode timing.......................................................................... 497 section 14 timer unit (tmu)............................................................................. 499 14.1 features....................................................................................................................... ....... 499 14.2 register desc riptions......................................................................................................... 5 01 14.2.1 timer start regist er (tstr) ................................................................................ 502 14.2.2 timer control regi sters (tcr) ............................................................................ 503 14.2.3 timer constant regi sters (tco r) ....................................................................... 504 14.2.4 timer counters (tcnt) ....................................................................................... 504 14.3 operation ...................................................................................................................... ..... 505 14.3.1 counter operation ................................................................................................ 505 14.4 interrupts..................................................................................................................... ....... 508 14.4.1 status flag se t timing.......................................................................................... 508 14.4.2 status flag cl ear timi ng ...................................................................................... 508 14.4.3 interrupt sources an d prioritie s ............................................................................ 509 14.5 usage notes .................................................................................................................... ... 510 14.5.1 writing to regi sters .............................................................................................. 510 14.5.2 reading registers ................................................................................................. 510 section 15 16-bit timer pulse unit (tpu) ......................................................... 511 15.1 features....................................................................................................................... ....... 511 15.2 input/output pins.............................................................................................................. .514 15.3 register desc riptions......................................................................................................... 5 15 15.3.1 timer control regi sters (tcr) ............................................................................ 516 15.3.2 timer mode regist ers (tmd r) ........................................................................... 520 15.3.3 timer i/o control re gisters (tior) .................................................................... 521 15.3.4 timer interrupt enable registers (tier) ............................................................. 523 rev. 3.00 jan. 18, 2008 page xix of lxii 15.3.5 timer status regi sters (tsr) ............................................................................... 524 15.3.6 timer counters (tcnt) ....................................................................................... 526 15.3.7 timer general regi sters (tgr )............................................................................ 526 15.3.8 timer start regist er (tstr) ................................................................................ 527 15.4 operation ...................................................................................................................... ..... 528 15.4.1 overview............................................................................................................... 528 15.4.2 basic func tions..................................................................................................... 529 15.4.3 buffer operation ................................................................................................... 534 15.4.4 pwm modes ......................................................................................................... 536 15.4.5 phase counting mode........................................................................................... 539 15.5 usage notes .................................................................................................................... ... 545 section 16 compare match timer (cmt) ..........................................................547 16.1 features....................................................................................................................... ....... 547 16.2 register desc riptions ......................................................................................................... 5 49 16.2.1 compare match timer start register (c mstr) .................................................. 550 16.2.2 compare match timer control/sta tus register (cmcsr) .................................. 551 16.2.3 compare match timer co unter (cmcnt) .......................................................... 553 16.2.4 compare match timer constant register (c mcor)........................................... 553 16.3 operation ...................................................................................................................... ..... 554 16.3.1 counter operation................................................................................................. 554 16.3.2 counter si ze.......................................................................................................... 555 16.3.3 timing for countin g by cmcnt ......................................................................... 556 16.3.4 dma transfer requests and internal interrupt reques ts to cpu ........................ 556 16.3.5 compare match flag set ti ming (all channels) ................................................. 557 section 17 realtime clock (rtc) .......................................................................559 17.1 features....................................................................................................................... ....... 559 17.2 input/output pin............................................................................................................... .. 561 17.3 register desc riptions ......................................................................................................... 5 62 17.3.1 64-hz counter (r64cnt) .................................................................................... 563 17.3.2 second counter (rseccnt) ............................................................................... 564 17.3.3 minute counter (r mincnt) ............................................................................... 565 17.3.4 hour counter (rhrcnt)..................................................................................... 566 17.3.5 day of week coun ter (rwkcnt) ...................................................................... 567 17.3.6 date counter (r daycnt) .................................................................................. 568 17.3.7 month counter (r moncnt) .............................................................................. 569 17.3.8 year counter (ryrcnt) ..................................................................................... 569 17.3.9 second alarm regist er (rsecar) ...................................................................... 570 17.3.10 minute alarm regist er (rminar)...................................................................... 570 rev. 3.00 jan. 18, 2008 page xx of lxii 17.3.11 hour alarm regist er (rhrar) ........................................................................... 571 17.3.12 day of week alarm re gister (rwkar) ............................................................. 572 17.3.13 date alarm regist er (rdaya r)......................................................................... 573 17.3.14 month alarm regist er (rmonar) ..................................................................... 574 17.3.15 year alarm regist er (ryrar)............................................................................ 574 17.3.16 rtc control regist er 1 (rcr1)........................................................................... 575 17.3.17 rtc control regist er 2 (rcr2)........................................................................... 577 17.3.18 rtc control regist er 3 (rcr3)........................................................................... 579 17.4 operation ...................................................................................................................... ..... 580 17.4.1 initial settings of regist ers after po wer-on ......................................................... 580 17.4.2 setting ti me ......................................................................................................... 580 17.4.3 reading ti me........................................................................................................ 581 17.4.4 alarm func tion..................................................................................................... 582 17.5 usage notes .................................................................................................................... ... 583 17.5.1 register writing dur ing rtc count..................................................................... 583 17.5.2 use of realtime clock (rtc ) periodic inte rrupts................................................ 583 17.5.3 transition to standby mode after setting re gister............................................... 583 17.5.4 crystal oscillato r circuit ...................................................................................... 584 section 18 serial communication in terface with fifo (scif).......................... 585 18.1 features....................................................................................................................... ....... 585 18.2 input/output pins.............................................................................................................. .588 18.3 register desc riptions......................................................................................................... 5 89 18.3.1 receive shift regi ster (scrs r) .......................................................................... 590 18.3.2 receive fifo data re gister (scf rdr) .............................................................. 590 18.3.3 transmit shift regi ster (sct sr) ......................................................................... 590 18.3.4 transmit fifo data re gister (scftdr)............................................................. 590 18.3.5 serial mode regist er (scsmr)............................................................................ 591 18.3.6 serial control regi ster (scs cr).......................................................................... 595 18.3.7 fifo error count regi ster (scfer) ................................................................... 599 18.3.8 serial status regi ster (scssr) ............................................................................ 600 18.3.9 bit rate regist er (scbrr) .................................................................................. 607 18.3.10 fifo control regi ster (scf cr) .......................................................................... 609 18.3.11 fifo data count regi ster (scfdr).................................................................... 612 18.3.12 transmit data stop re gister (sctdsr) .............................................................. 613 18.4 operation ...................................................................................................................... ..... 613 18.4.1 asynchronous mode............................................................................................. 613 18.4.2 serial oper ation .................................................................................................... 614 18.4.3 synchronous mode ............................................................................................... 624 18.4.4 serial operation in synchronous mode ................................................................ 625 rev. 3.00 jan. 18, 2008 page xxi of lxii 18.5 interrupt source s and dmac ............................................................................................ 635 18.6 usage notes .................................................................................................................... ... 637 section 19 infrared data association module (irda).........................................639 19.1 features....................................................................................................................... ....... 639 19.2 input/output pins .............................................................................................................. .640 19.3 register de scription........................................................................................................... 640 19.3.1 irda mode regist er (scimr) ............................................................................. 640 19.4 operation ...................................................................................................................... ..... 642 19.4.1 transmittin g.......................................................................................................... 642 19.4.2 receiving .............................................................................................................. 642 19.4.3 data format sp ecificatio n .................................................................................... 643 section 20 i 2 c bus interface (iic) .......................................................................645 20.1 features....................................................................................................................... ....... 645 20.2 input/output pins .............................................................................................................. .648 20.3 register desc riptions ......................................................................................................... 6 48 20.3.1 i 2 c bus control regist er 1 (iccr1 )..................................................................... 649 20.3.2 i 2 c bus control regist er 2 (iccr2 )..................................................................... 650 20.3.3 i 2 c bus mode regist er (icmr)............................................................................ 651 20.3.4 i 2 c bus interrupt enable register (i cier) ........................................................... 653 20.3.5 i 2 c bus status regi ster (icsr)............................................................................. 655 20.3.6 slave address regi ster (sar).............................................................................. 657 20.3.7 i 2 c bus transmit data re gister (icdrt)............................................................. 658 20.3.8 i 2 c bus receive data re gister (icd rr).............................................................. 658 20.3.9 i 2 c bus shift regist er (icdrs)............................................................................ 658 20.3.10 i 2 c bus master transfer clock select register (iccks)..................................... 658 20.4 operation ...................................................................................................................... ..... 660 20.4.1 i 2 c bus format...................................................................................................... 660 20.4.2 master transmit operation ................................................................................... 661 20.4.3 master receive operation..................................................................................... 663 20.4.4 slave transmit op eration ..................................................................................... 665 20.4.5 slave receive op eration....................................................................................... 667 20.4.6 noise cance ller..................................................................................................... 670 20.4.7 example of use..................................................................................................... 670 20.5 interrupt request.............................................................................................................. .. 675 20.6 bit synchronous circuit..................................................................................................... 676 20.7 usage notes .................................................................................................................... ... 677 rev. 3.00 jan. 18, 2008 page xxii of lxii section 21 serial i/o with fifo (siof) ............................................................. 679 21.1 features....................................................................................................................... ....... 679 21.2 input/output pins.............................................................................................................. .681 21.3 register desc riptions......................................................................................................... 6 82 21.3.1 mode register (simdr) ...................................................................................... 683 21.3.2 control register (sictr)..................................................................................... 686 21.3.3 transmit data regi ster (sitdr) .......................................................................... 689 21.3.4 receive data regist er (sirdr) ........................................................................... 690 21.3.5 transmit control data register (s itcr) ............................................................. 691 21.3.6 receive control data register (s ircr) .............................................................. 692 21.3.7 status register (sistr)........................................................................................ 693 21.3.8 interrupt enable regi ster (siier) ........................................................................ 699 21.3.9 fifo control regist er (sifctr) ......................................................................... 701 21.3.10 clock select regi ster (siscr) ............................................................................. 703 21.3.11 transmit data assign register (s itdar) ........................................................... 704 21.3.12 receive data assign re gister (sirdar) ............................................................ 706 21.3.13 control data assign re gister (sicdar) ............................................................. 707 21.4 operation ...................................................................................................................... ..... 709 21.4.1 serial cl ocks......................................................................................................... 709 21.4.2 serial ti ming ........................................................................................................ 711 21.4.3 transfer data format............................................................................................ 713 21.4.4 register allocation of transfer data .................................................................... 715 21.4.5 control data interface .......................................................................................... 717 21.4.6 fifo...................................................................................................................... 719 21.4.7 transmit and receive procedures......................................................................... 721 21.4.8 interrupts............................................................................................................... 727 21.4.9 transmit and recei ve timi ng............................................................................... 729 21.5 usage notes .................................................................................................................... ... 734 21.5.1 regarding sync signal high width when restarting transmission in master mode 2.................................................................................................. 734 section 22 analog front end interface (afeif) ................................................ 735 22.1 features....................................................................................................................... ....... 735 22.2 input/output pins.............................................................................................................. .736 22.3 register conf iguratio n....................................................................................................... 73 6 22.3.1 afeif control register 1 and 2 (actr1, actr2) ............................................ 737 22.3.2 make ratio count re gister (m rcr) ................................................................... 740 22.3.3 minimum pause count re gister (mpcr) ............................................................ 740 22.3.4 afeif status register 1 and 2 (astr1, astr2)................................................ 740 rev. 3.00 jan. 18, 2008 page xxiii of lxii 22.3.5 dial pulse number queue (dpnq) ...................................................................... 745 22.3.6 ringing pulse coun ter (rcn t)............................................................................ 746 22.3.7 afe control data re gister (acdr) .................................................................... 746 22.3.8 afe status data re gister (asdr) ....................................................................... 746 22.3.9 transmit data fifo port (tdfp)......................................................................... 747 22.3.10 receive data fifo port (rdfp) .......................................................................... 747 22.4 operation ...................................................................................................................... ..... 748 22.4.1 interrupt timing.................................................................................................... 748 22.4.2 afe interface........................................................................................................ 750 22.4.3 daa interface....................................................................................................... 752 22.4.4 wake up ringing interrupt ................................................................................... 754 section 23 usb pin multiplex controller ...........................................................755 23.1 features....................................................................................................................... ....... 755 23.2 input/output pins .............................................................................................................. .756 23.3 register desc riptions ......................................................................................................... 7 58 23.3.1 usb transceiver control register (u trctl) .................................................... 758 23.4 examples of extern al circuit............................................................................................. 759 23.4.1 example of the connection between usb function controller and transceiver. 759 23.4.2 example of the connection between usb ho st controller and transceiver........ 761 23.5 usage notes .................................................................................................................... ... 763 23.5.1 about the usb tr ansceiver .................................................................................. 763 23.5.2 about the examples of external ci rcuit ............................................................... 763 section 24 usb host c ontroller (usbh) ...........................................................765 24.1 features....................................................................................................................... ....... 765 24.2 input/output pins .............................................................................................................. .766 24.3 register desc riptions ......................................................................................................... 7 67 24.3.1 hc revision regist er (usbhr ) ........................................................................... 768 24.3.2 hc control regist er (usbhc) ............................................................................. 768 24.3.3 hc command status re gister (usbhcs) ............................................................ 771 24.3.4 hc interrupt status re gister (usbhis) ................................................................ 774 24.3.5 hc interrupt enable re gister (usb hie) .............................................................. 776 24.3.6 hc interrupt disable re gister (usb hid) ............................................................. 777 24.3.7 hcca register (usbhhcca)............................................................................ 779 24.3.8 hc period current ed re gister (usb hpced) .................................................... 779 24.3.9 hc control head ed re gister (usb hched)...................................................... 780 24.3.10 hc control current ed re gister (usbhcced) .................................................. 780 24.3.11 hc bulk head ed register (usbhbhed) .......................................................... 780 24.3.12 hc bulk current ed re gister (usb hbced) ...................................................... 781 rev. 3.00 jan. 18, 2008 page xxiv of lxii 24.3.13 hc done head ed regi ster (usbhdhed)......................................................... 781 24.3.14 hc fm interval regi ster (usbhfi)...................................................................... 781 24.3.15 hc frame remaining re gister (usb hfr)........................................................... 783 24.3.16 hc fm number b regi ster (usbhfn)................................................................. 784 24.3.17 hc periodic start re gister (usbhps) .................................................................. 785 24.3.18 hc ls threshold regi ster (usbhlst) ............................................................... 786 24.3.19 hc rh descriptor a re gister (usb hrda) ......................................................... 787 24.3.20 hc rh descriptor b re gister (usb hrdb).......................................................... 789 24.3.21 hc rh status regi ster (usbhrs)........................................................................ 790 24.3.22 hc rh port status 1 and hc rh port status 2 registers (usbhrps1, usbhrps2) .................................................................................. 792 24.4 data storage format which require d by usb host controller ........................................ 798 24.4.1 storage format of the transferred data ............................................................... 798 24.4.2 storage format of the descri ptor.......................................................................... 799 24.5 data alignment restriction of usb host co ntroller......................................................... 799 24.5.1 restriction on the li ne boundary of the synchronous dram ............................ 799 24.5.2 restriction on the memo ry access ad dress ......................................................... 800 24.6 accessing external addre ss from the us b host............................................................... 800 24.7 usage notes .................................................................................................................... ... 801 section 25 usb function controller (usbf) ..................................................... 803 25.1 features....................................................................................................................... ....... 803 25.2 input/output pins.............................................................................................................. .805 25.3 register desc riptions......................................................................................................... 8 06 25.3.1 interrupt flag regi ster 0 (ifr0) ........................................................................... 808 25.3.2 interrupt flag regi ster 1 (ifr1) ........................................................................... 810 25.3.3 interrupt flag regi ster 2 (ifr2) ........................................................................... 811 25.3.4 interrupt flag regi ster 3 (ifr3) ........................................................................... 813 25.3.5 interrupt flag regi ster 4 (ifr4) ........................................................................... 815 25.3.6 interrupt select regi ster 0 (isr0)......................................................................... 816 25.3.7 interrupt select regi ster 1 (isr1)......................................................................... 816 25.3.8 interrupt select regi ster 2 (isr2)......................................................................... 817 25.3.9 interrupt select regi ster 3 (isr3)......................................................................... 817 25.3.10 interrupt select regi ster 4 (isr4)......................................................................... 818 25.3.11 interrupt enable regi ster 0 (ier0) ....................................................................... 818 25.3.12 interrupt enable regi ster 1 (ier1) ....................................................................... 819 25.3.13 interrupt enable regi ster 2 (ier2) ....................................................................... 819 25.3.14 interrupt enable regi ster 3 (ier3) ....................................................................... 820 25.3.15 interrupt enable regi ster 4 (ier4) ....................................................................... 820 25.3.16 ep0i data regist er (epdr0i)............................................................................... 821 rev. 3.00 jan. 18, 2008 page xxv of lxii 25.3.17 ep0o data regist er (epdr0o) ............................................................................. 821 25.3.18 ep0s data regist er (epdr0s) .............................................................................. 821 25.3.19 ep1 data register (epdr1) ................................................................................. 822 25.3.20 ep2 data register (epdr2) ................................................................................. 822 25.3.21 ep3 data register (epdr3) ................................................................................. 822 25.3.22 ep4 data register (epdr4) ................................................................................. 823 25.3.23 ep5 data register (epdr5) ................................................................................. 823 25.3.24 ep0o receive data size register (epsz0o) ........................................................ 823 25.3.25 ep1 receive data size register (e psz1) ............................................................ 824 25.3.26 ep4 receive data size register (e psz4) ............................................................ 824 25.3.27 trigger register (trg)......................................................................................... 824 25.3.28 data status regist er (dasts).............................................................................. 825 25.3.29 fifo clear register 0 (fclr0) ........................................................................... 825 25.3.30 fifo clear register 1 (fclr1) ........................................................................... 826 25.3.31 dma transfer setting re gister (dma) ............................................................... 826 25.3.32 endpoint stall regist er 0 (epstl0)..................................................................... 827 25.3.33 endpoint stall regist er 1 (epstl1)..................................................................... 828 25.3.34 configuration value re gister (cvr) ................................................................... 828 25.3.35 time stamp register (tsrh/tsrl).................................................................... 829 25.3.36 control register 0 (ctlr0) ................................................................................. 830 25.3.37 control register 1 (ctlr1) ................................................................................. 831 25.3.38 endpoint information register (epir) ................................................................. 831 25.3.39 timer register (t mrh/tmrl) ........................................................................... 836 25.3.40 set time out register (stoh/stol).................................................................. 836 25.4 operation ...................................................................................................................... ..... 837 25.4.1 cable connect ion.................................................................................................. 837 25.4.2 cable disconn ection ............................................................................................. 838 25.4.3 control tran sfer.................................................................................................... 839 25.4.4 ep1 bulk-out transfer (dual fifos)................................................................... 845 25.4.5 ep2 bulk-in transfer (dual fifos) ..................................................................... 846 25.4.6 ep3 interrupt-in transfer...................................................................................... 848 25.5 ep4 isochronous-out transfer........................................................................................... 849 25.6 ep5 isochronous-in transfer ............................................................................................. 852 25.7 processing of usb standard command s and class/vendor commands........................... 855 25.7.1 processing of commands transmitted by control transfer ................................. 855 25.8 stall oper atio ns............................................................................................................... ... 856 25.8.1 overview............................................................................................................... 856 25.8.2 forcible stall by applicatio n ................................................................................ 856 25.8.3 automatic stall by usb function controller ....................................................... 858 rev. 3.00 jan. 18, 2008 page xxvi of lxii 25.9 usage notes .................................................................................................................... ... 859 25.9.1 setup data re ception ........................................................................................... 859 25.9.2 fifo cl ear............................................................................................................ 859 25.9.3 overreading/overwriting of data re gister........................................................... 859 25.9.4 assigning ep0 inte rrupt sour ces .......................................................................... 860 25.9.5 fifo clear when dma tr ansfer is set ................................................................ 860 25.9.6 note on using tr interrupt .................................................................................. 860 25.9.7 note on clock frequency ..................................................................................... 861 section 26 lcd controller (lcdc) ................................................................... 863 26.1 features....................................................................................................................... ....... 863 26.2 input/output pins.............................................................................................................. .865 26.3 register conf iguratio n....................................................................................................... 86 6 26.3.1 lcdc input clock regi ster (ldickr) ............................................................... 867 26.3.2 lcdc module type re gister (ldmtr) ............................................................. 868 26.3.3 lcdc data format re gister (lddfr)................................................................ 871 26.3.4 lcdc scan mode regi ster (ldsmr) ................................................................. 873 26.3.5 lcdc start address register for uppe r display data fetch (ldsaru) ........... 875 26.3.6 lcdc start address register for lowe r display data fetch (ldsarl) ........... 876 26.3.7 lcdc line address offset register for display data fetch (ldlaor) ........... 877 26.3.8 lcdc palette control re gister (ldp alcr)....................................................... 878 26.3.9 palette data registers 00 to ff (ldpr00 to ldprff) ....................................... 879 26.3.10 lcdc horizontal character nu mber register (ldhcnr) ................................. 880 26.3.11 lcdc horizontal sync signa l register (l dhsynr)......................................... 881 26.3.12 lcdc vertical display line nu mber register (ldvdlnr) ............................. 882 26.3.13 lcdc vertical total line numb er register (l dvtlnr).................................. 883 26.3.14 lcdc vertical sync signal register (ldvsynr) ............................................. 884 26.3.15 lcdc ac modulation signal toggle line number register (ldaclnr) ....... 885 26.3.16 lcdc interrupt control register (ldintr) ....................................................... 886 26.3.17 lcdc power management mode register (l dpmmr) ..................................... 889 26.3.18 lcdc power-supply sequence peri od register (ldpspr)................................ 891 26.3.19 lcdc control regist er (ldcntr)..................................................................... 892 26.3.20 lcdc user specified interrupt co ntrol register (lduintr)............................ 893 26.3.21 lcdc user specified interrupt line number register (lduintlnr) ............. 895 26.3.22 lcdc memory access interval nu mber register (ldlirnr) .......................... 896 26.4 operation ...................................................................................................................... ..... 897 26.4.1 lcd module sizes which can be displayed in th is lcdc .................................. 897 26.4.2 limits on the resolution of rotated displays, burst length, and connected memo ry (sdram) ...................................................................... 898 26.4.3 color palette sp ecificatio n ................................................................................... 905 rev. 3.00 jan. 18, 2008 page xxvii of lxii 26.4.4 data format .......................................................................................................... 907 26.4.5 setting the displa y resolution.............................................................................. 910 26.4.6 power management registers............................................................................... 910 26.4.7 operation for hardwa re rotation ......................................................................... 915 26.5 clock and lcd data si gnal exam ples.............................................................................. 918 26.6 usage notes .................................................................................................................... ... 928 26.6.1 procedure for halting access to display data storage vram (synchronous dram in area 3) .......................................................................... 928 section 27 a/d converter....................................................................................929 27.1 features....................................................................................................................... ....... 929 27.2 input pins ..................................................................................................................... ...... 931 27.3 register desc riptions ......................................................................................................... 9 32 27.3.1 a/d data registers a to d (addra to addrd) .............................................. 932 27.3.2 a/d control/status re gisters (adc sr)............................................................... 933 27.4 operation ...................................................................................................................... ..... 936 27.4.1 single mode.......................................................................................................... 936 27.4.2 multi m ode ........................................................................................................... 938 27.4.3 scan mode ............................................................................................................ 940 27.4.4 input sampling and a/d conversion time .......................................................... 942 27.4.5 external trigger input timi ng.............................................................................. 943 27.5 interrupts..................................................................................................................... ....... 944 27.6 definitions of a/d co nversion accuracy.......................................................................... 944 27.7 usage notes .................................................................................................................... ... 946 27.7.1 notes on a/d co nversion ..................................................................................... 946 27.7.2 notes on a/d conversion-end in terrupt and dma transfer............................... 948 27.7.3 allowable signal-sou rce impedance.................................................................... 948 27.7.4 influence to absolu te accuracy............................................................................ 949 27.7.5 setting analog in put voltage ............................................................................... 949 27.7.6 notes on boar d design ......................................................................................... 949 27.7.7 notes on countermeasur es to noise ..................................................................... 950 section 28 d/a converter (dac)........................................................................953 28.1 features....................................................................................................................... ....... 953 28.2 input/output pins .............................................................................................................. .954 28.3 register desc riptions ......................................................................................................... 9 54 28.3.1 d/a data registers 0 an d 1 (dadr0, dadr1) .................................................. 954 28.3.2 d/a control regist er (dacr) ............................................................................. 955 28.4 operation ...................................................................................................................... ..... 956 rev. 3.00 jan. 18, 2008 page xxviii of lxii section 29 pc card controller (pcc)................................................................. 957 29.1 features....................................................................................................................... ....... 957 29.1.1 pcmcia s upport ................................................................................................. 959 29.2 input/output pins.............................................................................................................. .962 29.3 register desc riptions......................................................................................................... 9 63 29.3.1 area 6 interface status register (p cc0isr) ........................................................ 963 29.3.2 area 6 general control register (p cc0gcr) ..................................................... 966 29.3.3 area 6 card status change register (p cc0cscr) ............................................. 969 29.3.4 area 6 card status change interrupt enable register (pcc0cscier)............... 972 29.4 operation ...................................................................................................................... ..... 976 29.4.1 pc card connection specification (interf ace diagram, pin correspondence)...... 976 29.4.2 pc card interf ace timing ..................................................................................... 980 29.5 usage notes .................................................................................................................... ... 985 section 30 sim card module (sim) ................................................................... 987 30.1 features....................................................................................................................... ....... 987 30.2 input/output pins.............................................................................................................. .989 30.3 register desc riptions......................................................................................................... 9 89 30.3.1 serial mode regist er (scsmr)............................................................................ 990 30.3.2 bit rate regist er (scbrr) .................................................................................. 991 30.3.3 serial control regi ster (scs cr).......................................................................... 992 30.3.4 transmit shift regi ster (sct sr) ......................................................................... 994 30.3.5 transmit data regi ster (sctdr)......................................................................... 994 30.3.6 serial status regi ster (scssr) ............................................................................ 995 30.3.7 receive shift regi ster (scrs r) ........................................................................ 1001 30.3.8 receive data regi ster (scrd r) ........................................................................ 1001 30.3.9 smart card mode regi ster (scs cmr) .............................................................. 1002 30.3.10 serial control 2 regi ster (scs c2r)................................................................... 1003 30.3.11 guard extension regi ster (scg rd) .................................................................. 1004 30.3.12 wait time register (scwai t) .......................................................................... 1004 30.3.13 sampling register (scsmp l)............................................................................ 1005 30.4 operation ...................................................................................................................... ... 1006 30.4.1 overview ............................................................................................................ 1006 30.4.2 data form at ........................................................................................................ 1007 30.4.3 register se ttings ................................................................................................. 1008 30.4.4 clocks ................................................................................................................. 1011 30.4.5 data transmit/receive operatio n....................................................................... 1012 30.5 usage notes .................................................................................................................... . 1020 rev. 3.00 jan. 18, 2008 page xxix of lxii section 31 multimediacard interface (mmcif) ..............................................1027 31.1 features....................................................................................................................... ..... 1027 31.2 input/output pins ............................................................................................................. 1 029 31.3 register desc riptions ....................................................................................................... 103 0 31.3.1 mode register (moder)................................................................................... 1031 31.3.2 command type regist er (cmdtyr)................................................................ 1031 31.3.3 response type regi ster (rsp tyr) ................................................................... 1033 31.3.4 transfer byte number co unt register (tbcr) ................................................. 1036 31.3.5 transfer block number counter (t bncr)........................................................ 1037 31.3.6 command registers 0 to 5 (cmdr0 to cmdr5) .............................................. 1037 31.3.7 response registers 0 to 16 and d (rspr0 to rspr16 and rsprd) ................ 1038 31.3.8 command start regist er (cmdstrt)............................................................... 1040 31.3.9 operation control re gister (o pcr) ................................................................... 1041 31.3.10 command timeout control register (ctocr) ................................................. 1043 31.3.11 data timeout regist er (dtout r) .................................................................... 1044 31.3.12 card status regi ster (cst r) .............................................................................. 1045 31.3.13 interrupt control registers 0 an d 1 (intcr0 and intcr1) .............................. 1047 31.3.14 interrupt status registers 0 an d 1 (intstr0 an d intstr1) ............................ 1049 31.3.15 transfer clock control register (c lkon)........................................................ 1053 31.3.16 vdd/open-drain control register (v dcnt) ................................................... 1054 31.3.17 data register (dr) ............................................................................................. 1054 31.3.18 fifo pointer clear regi ster (fifoclr) ........................................................... 1055 31.3.19 dma control regist er (dma cr) ..................................................................... 1055 31.3.20 interrupt control regi ster 2 (int cr2)............................................................... 1056 31.3.21 interrupt status regist er 2 (intstr2)............................................................... 1057 31.4 operation ...................................................................................................................... ... 1058 31.4.1 operations in mmc mode .................................................................................. 1058 31.5 operations us ing dmac................................................................................................. 1088 31.5.1 operation of read sequence............................................................................... 1088 31.5.2 operation of write sequence.............................................................................. 1098 31.6 mmcif interrupt sources ................................................................................................ 1108 section 32 ssl accelerator (ssl) ....................................................................1109 section 33 user break controller (ubc) ..........................................................1111 33.1 features....................................................................................................................... ..... 1111 33.2 register desc riptions ....................................................................................................... 111 3 33.2.1 break address regist er a (bar a) .................................................................... 1113 33.2.2 break address mask regi ster a (bam ra)....................................................... 1114 rev. 3.00 jan. 18, 2008 page xxx of lxii 33.2.3 break bus cycle regi ster a ( bbra)................................................................. 1114 33.2.4 break address regist er b (ba rb) .................................................................... 1116 33.2.5 break address mask re gister b (b amrb) ....................................................... 1117 33.2.6 break data regist er b (bdr b).......................................................................... 1117 33.2.7 break data mask regi ster b (b dmrb)............................................................. 1118 33.2.8 break bus cycle regi ster b ( bbrb) ................................................................. 1119 33.2.9 break control regi ster (brc r) ......................................................................... 1120 33.2.10 execution times break register (b etr)........................................................... 1124 33.2.11 branch source regi ster (brs r)......................................................................... 1124 33.2.12 branch destination re gister ( brdr)................................................................. 1125 33.2.13 break asid register a (basra ) ..................................................................... 1125 33.2.14 break asid regist er b (bas rb)...................................................................... 1126 33.3 operation ...................................................................................................................... ... 1127 33.3.1 flow of the user br eak operat ion ...................................................................... 1127 33.3.2 break on instructio n fetch cy cle ....................................................................... 1128 33.3.3 break on data a ccess cycl e............................................................................... 1129 33.3.4 break on x/y-memory bus cycl e ..................................................................... 1130 33.3.5 sequential br eak................................................................................................. 1131 33.3.6 value of saved prog ram counte r ....................................................................... 1131 33.3.7 pc trace ............................................................................................................. 1132 33.3.8 usage examples.................................................................................................. 1133 33.4 usage notes .................................................................................................................... . 1138 section 34 pin function controller (pfc) ........................................................ 1141 34.1 register desc riptions....................................................................................................... 114 6 34.1.1 port a control regi ster (pac r) ........................................................................ 1147 34.1.2 port b control re gister (p bcr)......................................................................... 1148 34.1.3 port c control re gister (p ccr)......................................................................... 1150 34.1.4 port d control regi ster (pdc r) ........................................................................ 1151 34.1.5 port e control regi ster (pec r) ......................................................................... 1153 34.1.6 port f control regi ster (pfc r).......................................................................... 1154 34.1.7 port g control regi ster (pgc r) ........................................................................ 1156 34.1.8 port h control regi ster (phc r) ........................................................................ 1157 34.1.9 port j control regi ster (pjc r) ........................................................................... 1159 34.1.10 port k control regi ster (pkc r) ........................................................................ 1160 34.1.11 port l control regi ster (plc r) ......................................................................... 1161 34.1.12 port m control regi ster (pm cr) ....................................................................... 1162 34.1.13 port p control regi ster (ppc r).......................................................................... 1164 34.1.14 port r control re gister (p rcr)......................................................................... 1165 34.1.15 port s control regi ster (psc r).......................................................................... 1167 rev. 3.00 jan. 18, 2008 page xxxi of lxii 34.1.16 port t control regi ster (ptc r) ......................................................................... 1168 34.1.17 port u control regi ster (puc r) ........................................................................ 1169 34.1.18 port v control regi ster (pvc r) ........................................................................ 1170 34.1.19 pin select register a (psela) .......................................................................... 1171 34.1.20 pin select register b (pselb)........................................................................... 1173 34.1.21 pin select register c (pselc)........................................................................... 1174 34.1.22 pin select register d (pseld) .......................................................................... 1176 34.1.23 usb transceiver control register (u trctl) .................................................. 1178 section 35 i/o ports ...........................................................................................1179 35.1 port a......................................................................................................................... ...... 1179 35.1.1 register desc ription ........................................................................................... 1179 35.1.2 port a data regi ster (padr)............................................................................. 1180 35.2 port b ......................................................................................................................... ...... 1181 35.2.1 register desc ription ........................................................................................... 1181 35.2.2 port b data regi ster (pbdr) ............................................................................. 1182 35.3 port c ......................................................................................................................... ...... 1183 35.3.1 register desc ription ........................................................................................... 1183 35.3.2 port c data regi ster (pcdr) ............................................................................. 1184 35.4 port d......................................................................................................................... ...... 1185 35.4.1 register desc ription ........................................................................................... 1185 35.4.2 port d data regi ster (pddr)............................................................................. 1186 35.5 port e ......................................................................................................................... ...... 1187 35.5.1 register desc ription ........................................................................................... 1187 35.5.2 port e data regi ster (ped r).............................................................................. 1188 35.6 port f ......................................................................................................................... ...... 1190 35.6.1 register desc ription ........................................................................................... 1190 35.6.2 port f data regi ster (pfd r) .............................................................................. 1191 35.7 port g......................................................................................................................... ...... 1193 35.7.1 register desc ription ........................................................................................... 1193 35.7.2 port g data regi ster (pgdr)............................................................................. 1194 35.8 port h......................................................................................................................... ...... 1195 35.8.1 register desc ription ........................................................................................... 1195 35.8.2 port h data regi ster (phdr)............................................................................. 1196 35.9 port j ......................................................................................................................... ....... 1197 35.9.1 register desc ription ........................................................................................... 1197 35.9.2 port j data regi ster (pjd r) ............................................................................... 1198 35.10 port k......................................................................................................................... ...... 1199 35.10.1 register desc ription ........................................................................................... 1199 35.10.2 port k data regi ster (pkdr)............................................................................. 1200 rev. 3.00 jan. 18, 2008 page xxxii of lxii 35.11 port l ......................................................................................................................... ...... 1201 35.11.1 register desc ription ........................................................................................... 1201 35.11.2 port l data regi ster (pld r).............................................................................. 1202 35.12 port m ......................................................................................................................... ..... 1203 35.12.1 register desc ription ........................................................................................... 1203 35.12.2 port m data regi ster (pmd r) ........................................................................... 1204 35.13 port p ......................................................................................................................... ...... 1205 35.13.1 register desc ription ........................................................................................... 1205 35.13.2 port p data regi ster (ppd r) .............................................................................. 1206 35.14 port r ......................................................................................................................... ...... 1207 35.14.1 register desc ription ........................................................................................... 1207 35.14.2 port r data regi ster (prdr) ............................................................................. 1208 35.15 port s ......................................................................................................................... ...... 1209 35.15.1 register desc ription ........................................................................................... 1209 35.15.2 port s data regi ster (psd r) .............................................................................. 1210 35.16 port t ......................................................................................................................... ...... 1211 35.16.1 register desc ription ........................................................................................... 1211 35.16.2 port t data regi ster (ptd r).............................................................................. 1212 35.17 port u......................................................................................................................... ...... 1213 35.17.1 register desc ription ........................................................................................... 1213 35.17.2 port u data regi ster (pudr)............................................................................. 1214 35.18 port v......................................................................................................................... ...... 1215 35.18.1 register desc ription ........................................................................................... 1215 35.18.2 port v data regi ster (pvdr)............................................................................. 1216 section 36 user debugging interface (h-udi)................................................. 1217 36.1 features....................................................................................................................... ..... 1217 36.2 input/output pins............................................................................................................. 1 218 36.3 register desc riptions....................................................................................................... 122 0 36.3.1 bypass register (sdbpr) .................................................................................. 1220 36.3.2 instruction regist er (sdir) ................................................................................ 1220 36.3.3 shift regi ster ...................................................................................................... 1221 36.3.4 boundary scan regist er (sdbsr) ..................................................................... 1221 36.3.5 id register (sdid)............................................................................................. 1230 36.4 operation ...................................................................................................................... ... 1231 36.4.1 tap contro ller ................................................................................................... 1231 36.4.2 reset configur ation ............................................................................................ 1232 36.4.3 tdo output timing ........................................................................................... 1232 36.4.4 h-udi rese t ....................................................................................................... 1233 36.4.5 h-udi interrupt .................................................................................................. 1233 rev. 3.00 jan. 18, 2008 page xxxiii of lxii 36.5 boundary scan ................................................................................................................. 1 234 36.5.1 supported inst ructions ........................................................................................ 1234 36.5.2 points for a ttention ............................................................................................. 1235 36.6 usage notes .................................................................................................................... . 1236 36.7 advanced user de bugger (aud).................................................................................... 1236 section 37 list of registers ...............................................................................1237 37.1 register ad dresses........................................................................................................... 12 38 37.2 register bits.................................................................................................................. ... 1255 37.3 register states in ea ch operating mode ......................................................................... 1289 section 38 electrical characteristics .................................................................1305 38.1 absolute maximu m ratings ............................................................................................ 1305 38.2 power-on and powe r-off orde r ...................................................................................... 1306 38.3 dc character istics ........................................................................................................... 13 09 38.4 ac character istics ........................................................................................................... 13 14 38.4.1 clock timi ng ...................................................................................................... 1315 38.4.2 control signal timing ........................................................................................ 1319 38.4.3 ac bus ti ming................................................................................................... 1322 38.4.4 basic timi ng....................................................................................................... 1324 38.4.5 burst rom ti ming............................................................................................. 1331 38.4.6 sdram timing ................................................................................................. 1332 38.4.7 pcmcia ti ming ................................................................................................ 1351 38.4.8 peripheral module si gnal timi ng....................................................................... 1355 38.4.9 16-bit timer pulse unit (tpu )........................................................................... 1356 38.4.10 rtc signal timing............................................................................................. 1357 38.4.11 scif module signa l timing ............................................................................... 1358 38.4.12 i 2 c bus interfa ce timing .................................................................................... 1360 38.4.13 siof module si gnal timi ng .............................................................................. 1362 38.4.14 afeif module sign al timi ng ............................................................................ 1365 38.4.15 usb module signa l timing ............................................................................... 1366 38.4.16 lcdc module sign al timi ng ............................................................................ 1368 38.4.17 sim module signa l timing ................................................................................ 1369 38.4.18 mmcif module signa l timing .......................................................................... 1370 38.4.19 h-udi related pi n timing ................................................................................. 1372 38.5 a/d converter char acteristic s ......................................................................................... 1374 38.6 d/a converter char acteristic s ......................................................................................... 1374 38.7 ac characteristic te st condi tions................................................................................... 1375 rev. 3.00 jan. 18, 2008 page xxxiv of lxii appendix ....................................................................................................... 1377 a. pin states ..................................................................................................................... .... 1377 b. product lineup................................................................................................................. 1390 c. package dime nsions ........................................................................................................ 1392 main revisions and additions in this edition................................................... 1395 index ....................................................................................................... 1451 rev. 3.00 jan. 18, 2008 page xxxv of lxii figures section 1 overview figure 1.1 block di agram ..................................................................................................... ....... 10 figure 1.2 pin assignments (plbg0256ga-a (bp-256h/hv))................................................. 11 figure 1.3 pin assignments (plbg0256ka-a (bp-256c/cv)) ................................................. 12 section 2 cpu figure 2.1 processi ng state tr ansitions...................................................................................... .. 38 figure 2.2 virtual address to external memory space mapping................................................. 41 figure 2.3 register configura tion in each pro cessing mode....................................................... 44 figure 2.4 ge neral registers ................................................................................................. ....... 46 figure 2.5 system regist ers and progra m counter ...................................................................... 47 figure 2.6 control re gister config uration ................................................................................... 5 1 figure 2.7 data format on memory (big endian mode) ............................................................. 52 figure 2.8 data format on memory (little en dian mode) .......................................................... 53 section 3 dsp operating unit figure 3.1 dsp instruction format............................................................................................ ... 82 figure 3.2 cpu regi sters in dsp mode....................................................................................... 84 figure 3.3 dsp regi ster config uration ........................................................................................ 88 figure 3.4 dsp register s and bus connections ......................................................................... 101 figure 3.5 general re gisters (dsp mode) ................................................................................. 104 figure 3.6 sample para llel instructio n program ......................................................................... 119 figure 3.7 examples of conditional operations and data transfer instructions ....................... 121 figure 3.8 data formats ...................................................................................................... ....... 124 figure 3.9 alu fixed-point arithmetic opera tion flow ........................................................... 125 figure 3.10 operatio n sequence example.................................................................................. 127 figure 3.11 dc bit generation exam ples in carry or borrow mode ........................................ 128 figure 3.12 dc bit generation ex amples in negative value mode .......................................... 129 figure 3.13 dc bit generation examples in overflow mode.................................................... 129 figure 3.14 alu integer arithmetic operat ion flow ................................................................ 131 figure 3.15 alu logi cal operatio n flow ................................................................................. 133 figure 3.16 fixed-point multiply opera tion flow ..................................................................... 135 figure 3.17 arithmetic shift operatio n flow............................................................................. 137 figure 3.18 logical shift operatio n flow .................................................................................. 139 figure 3.19 pdms b operation flow ......................................................................................... 141 figure 3.20 roundin g operation flow ....................................................................................... 145 figure 3.21 definition of rounding op eration........................................................................... 145 rev. 3.00 jan. 18, 2008 page xxxvi of lxii figure 3.22 local data move instruc tion flow.......................................................................... 147 section 4 memory ma nagement unit (mmu) figure 4.1 mmu functions ..................................................................................................... ... 167 figure 4.2 virtual addr ess space (mmucr .at = 1)................................................................ 169 figure 4.3 virtual addr ess space (mmucr .at = 0)................................................................ 170 figure 4.4 p4 area........................................................................................................... ........... 171 figure 4.5 phys ical address space............................................................................................ .172 figure 4.6 overall conf iguration of the tlb............................................................................. 177 figure 4.7 virtual addr ess and tlb st ructure............................................................................ 178 figure 4.8 tlb indexing (ix = 1) ............................................................................................. .179 figure 4.9 tlb indexing (ix = 0) ............................................................................................. .180 figure 4.10 objects of address comp arison.............................................................................. 181 figure 4.11 operation of ldtlb inst ruction............................................................................. 185 figure 4.12 synonym pr oblem (32-kbyte cache) ...................................................................... 187 figure 4.13 mmu exceptio n generation flowchart .................................................................. 193 figure 4.14 specifying address and data for memo ry-mapped tlb access ........................... 195 section 5 cache figure 5.1 cache structure ................................................................................................... ...... 198 figure 5.2 cache search scheme ............................................................................................... 206 figure 5.3 write-back buffer configur ation .............................................................................. 208 figure 5.4 specifying address and data for memory-mapped cache access (16-kbyte m ode) ........................................................................................................ 211 section 7 exception handling figure 7.1 register bit config uration ........................................................................................ 218 section 8 interrupt controller (intc) figure 8.1 block diagram of intc............................................................................................ 2 44 figure 8.2 example of ir l interrupt c onnection....................................................................... 267 figure 8.3 interrupt operation flowchart................................................................................... 27 7 section 9 bus state controller (bsc) figure 9.1 block diagram of bsc ............................................................................................. 2 82 figure 9.2 address space ..................................................................................................... ...... 286 figure 9.3 normal space basi c access timing (a ccess wait 0)............................................... 337 figure 9.4 continuous access for normal space 1, bus width = 16 bits, longword access, csnwcr.wm bit = 0 (access wa it = 0, cycle wait = 0) ...................................... 339 rev. 3.00 jan. 18, 2008 page xxxvii of lxii figure 9.5 continuous access for normal space 2, bus width = 16 bits, longword access, csnwcr.wm bit = 1 (access wa it = 0, cycle wait = 0) ...................................... 340 figure 9.6 example of 32-bit data-width sram connection .................................................. 341 figure 9.7 example of 16-bit data-width sram connection .................................................. 342 figure 9.8 example of 8-bit data-width sram connectio n.................................................... 342 figure 9.9 wait timing for normal space access (softwar e wait only ) ................................. 343 figure 9.10 wait state timing for normal space access (wait state insertion using wait signal) .............................................................. 344 figure 9.11 csn assert period expansion.................................................................................. 345 figure 9.12 example of 32-bit data-width sdram connection ............................................. 347 figure 9.13 example of 16-bit data-width sdram connection ............................................. 348 figure 9.14 burst read ba sic timing (auto-precharge)............................................................ 361 figure 9.15 burst read wait speci fication timing (auto-precharge)....................................... 362 figure 9.16 basic timing for single read (auto-precharge)..................................................... 363 figure 9.17 basic timing for burst write (auto- precharge) ..................................................... 365 figure 9.18 basic timing for single write (auto- precharge).................................................... 366 figure 9.19 burst read ti ming (no auto-precharge)................................................................ 368 figure 9.20 burst read timing (bank active, same row address) ......................................... 369 figure 9.21 burst read timing (ban k active, different row addresses) ................................ 370 figure 9.22 single write ti ming (no auto-precharge) ............................................................. 371 figure 9.23 single write timing (b ank active, same row address) ....................................... 372 figure 9.24 single write timing (ban k active, different row addresses) .............................. 373 figure 9.25 au to-refresh timing .............................................................................................. 375 figure 9.26 se lf-refresh timing .............................................................................................. .. 376 figure 9.27 access timi ng in power-down mode .................................................................... 378 figure 9.28 write timing for sdram mode register (based on jedec)............................... 381 figure 9.29 emrs command issue timing............................................................................... 384 figure 9.30 transition timing in deep power- down mode...................................................... 385 figure 9.31 burst rom (clock asynchronous) access (bus width = 32 bits, 16-byte transfer (number of bursts = 4), access wait for first time = 2, access wa it for 2nd time and after = 1) ............. 387 figure 9.32 basic access timing fo r byte-selection sram (bas = 0) ................................... 388 figure 9.33 basic access timing fo r byte-selection sram (bas = 1) ................................... 389 figure 9.34 wait timing for byte-selection sram (bas = 1) (software wait only)............. 390 figure 9.35 example of connection with 32-bit data-width byte-selection sram ............... 391 figure 9.36 example of connection with 16-bit data-width byte-selection sram ............... 391 figure 9.37 example of pc mcia interface connectio n............................................................ 393 figure 9.38 basic access timing fo r pcmcia memory ca rd interface................................... 394 rev. 3.00 jan. 18, 2008 page xxxviii of lxii figure 9.39 wait timing for pcmcia memory card interface (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait = 1, hardware wa it = 1) ................................................................................................. 395 figure 9.40 example of pcmcia space assignment (cs5bwcr.sa[1:0] = b'10, cs6b wcr.sa[1:0] = b'10) .................................... 396 figure 9.41 basic timing for pcmcia i/o card interface ....................................................... 398 figure 9.42 wait timing for pcmcia i/o card interface (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait = 1, hardware wa it = 1) ................................................................................................. 399 figure 9.43 timing for dynamic bus sizing of pcmcia i/o card interface (ted[3:0] = b'0010, teh[3:0] = b' 0001, software waits = 3) ............................. 399 figure 9.44 burst rom (clock synchronous) access timing (burst length = 8, wait cycles inserted in first access = 2, wait cycles inserted in second and subsequent a ccesses = 1).............................. 400 figure 9.45 bus arbitration timing ........................................................................................... 403 section 10 direct memory access controller (dmac) figure 10.1 block diagram of dmac ....................................................................................... 408 figure 10.2 dma transfer flowchart........................................................................................ 425 figure 10.3 round-robin mode................................................................................................. 432 figure 10.4 changes in channel priority in roun d-robin mode............................................... 433 figure 10.5 data flow of dual addr ess mode........................................................................... 435 figure 10.6 example of dma transfer timing in dual mode (source: ordinary memory, destin ation: ordinary memory)................................. 436 figure 10.7 data flow in single addr ess mode......................................................................... 437 figure 10.8 example of dma transf er timing in single address mode ................................. 438 figure 10.9 dma transfer exam ple in cycle-steal normal mode (dual address, dreq lo w level det ection)......................................................... 439 figure 10.10 example of dma transfer in cycle steal intermittent mode (dual address, dreq lo w level det ection)....................................................... 440 figure 10.11 dma transfer example in burst mode (dual address, dreq lo w level det ection)....................................................... 440 figure 10.12 bus state when mu ltiple channels ar e operating................................................. 443 figure 10.13 example of dreq input detec tion in cycle steal mode edge detection............ 444 figure 10.14 example of dreq input detec tion in cycle steal mode level detection........... 445 figure 10.15 example of dreq input det ection in burst mode edge detection ..................... 445 figure 10.16 example of dreq input det ection in burst mode level detection .................... 446 figure 10.17 example of dma transfer en d in cycle steal mode level detection ................ 446 figure 10.18 example of bsc ordinary memory access (no wait, idle cycle 1, longwor d access to 16-b it device) ............................... 447 rev. 3.00 jan. 18, 2008 page xxxix of lxii figure 10.19 timing of dreq input detection by edge detection in cycle stealing mode (dack is divided into four due to idle cycle insertion between access cycles and so dreq sampling is a ccepted one extra time) ........................................ 450 figure 10.20 timing of dreq input detection by edge detection in cycle stealing mode (dack is not divided by idle cycl e insertion between access cycles and so dreq sampling is accepted norm ally)................................................... 450 figure 10.21 timing of dreq input detection by level detection in cycle stealing mode (dack is divided into four due to idle cycle insertion between access cycles and so dreq sampling is a ccepted one extra time) ........................................ 451 figure 10.22 timing of dreq input detection by edge detection in cycle stealing mode (dack is not divided by idle cycl e insertion between access cycles and so dreq sampling is accepted norm ally)................................................... 452 section 11 clock pulse generator (cpg) figure 11.1 bloc k diagram of cpg ........................................................................................... 45 4 figure 11.2 points for attenti on when using crysta l resonator................................................ 467 figure 11.3 points for attention when using pll osc illator circ uit ........................................ 468 section 12 watchdog timer (wdt) figure 12.1 block diagram of wdt .......................................................................................... 470 figure 12.2 writing to wtcnt and wtcsr............................................................................ 474 section 13 power-down modes figure 13.1 canceling standby mode with stby bit in st bcr.............................................. 490 figure 13.2 status out put at power-on reset........................................................................ 492 figure 13.3 status ou tput at manua l reset ........................................................................... 492 figure 13.4 status output when software standby mode is canceled by an interrupt......... 493 figure 13.5 status output when software standby mode is canceled by a power-on reset................................................................................................ 493 figure 13.6 status output when software standby mode is canceled by a manual reset ................................................................................................... 494 figure 13.7 status output when sleep mode is canceled by an interrupt ............................ 494 figure 13.8 status output when sleep m ode is canceled by a power-on reset.................. 495 figure 13.9 status output when sleep mode is canceled by a manual re set ..................... 495 figure 13.10 hardware standby mode timi ng (ca is pulled low in normal operation) ........... 497 figure 13.11 hardware standby mode timing (ca is pulled low while wdt operates af ter the standby mode is canceled) ....... 498 figure 13.12 timing when power of pins other than v cc _rtc and v cc q_rtc is off........... 498 rev. 3.00 jan. 18, 2008 page xl of lxii section 14 timer unit (tmu) figure 14.1 block diagram of tmu .......................................................................................... 500 figure 14.2 setti ng count op eration.......................................................................................... 505 figure 14.3 auto-rel oad count oper ation................................................................................. 506 figure 14.4 count timing when internal clock is operating .................................................... 507 figure 14.5 count timing when rtc clock is operating ......................................................... 507 figure 14.6 unf set timing ................................................................................................... ... 508 figure 14.7 status flag clear timing......................................................................................... 508 section 15 16-bit timer pulse unit (tpu) figure 15.1 bloc k diagram of tpu............................................................................................ 5 13 figure 15.2 example of counte r operation setting procedure .................................................. 529 figure 15.3 free-runnin g counter operation ............................................................................ 530 figure 15.4 periodic counter operation..................................................................................... 53 1 figure 15.5 example of setting procedure for waveform output by compare match.............. 532 figure 15.6 example of 0 ou tput/1 output operation ............................................................... 533 figure 15.7 example of t oggle output op eration ..................................................................... 533 figure 15.8 compare ma tch buffer operation........................................................................... 534 figure 15.9 example of buffe r operation setting procedure..................................................... 535 figure 15.10 example of buffer operation ................................................................................ 536 figure 15.11 example of pw m mode setting pr ocedure .......................................................... 537 figure 15.12 example of pwm mode opera tion (1) ................................................................. 538 figure 15.13 examples of pwm mode opera tion (2)................................................................ 538 figure 15.14 example of phase counting mode settin g procedure........................................... 540 figure 15.15 example of phas e counting mode 1 operation .................................................... 541 figure 15.16 example of phas e counting mode 2 operation .................................................... 542 figure 15.17 example of phas e counting mode 3 operation .................................................... 543 figure 15.18 example of phas e counting mode 4 operation .................................................... 544 figure 15.19 phase difference, overlap, and pulse width in phase counting mode ................ 545 section 16 compare match timer (cmt) figure 16.1 block diagram of cmt .......................................................................................... 548 figure 16.2 counter operat ion (one-shot op eration) ............................................................... 554 figure 16.3 counter operatio n (free-running operation) ........................................................ 555 figure 16.4 cmf set timing................................................................................................... ... 557 section 17 realtime clock (rtc) figure 17.1 rt c block di agram................................................................................................ 560 figure 17.2 setting time ..................................................................................................... ....... 580 figure 17.3 readin g time ..................................................................................................... ..... 581 rev. 3.00 jan. 18, 2008 page xli of lxii figure 17.4 us ing alarm function ............................................................................................. 582 figure 17.5 using peri odic interrupt function ........................................................................... 583 figure 17.6 example of crysta l oscillator circu it connectio n .................................................. 584 section 18 serial communicati on interface with fifo (scif) figure 18.1 bloc k diagram of scif........................................................................................... 5 87 figure 18.2 sample scif initialization fl owchart ..................................................................... 616 figure 18.3 sample serial transmission flowchart ................................................................... 617 figure 18.4 example of transmit operation (example with 8-bit data, parity, one st op bit) .................................................... 619 figure 18.5 example of tr ansmit data stop function ............................................................... 619 figure 18.6 transmit data stop function flowchart ................................................................. 620 figure 18.7 sample serial reception flowch art (1)................................................................... 621 figure 18.8 sample serial reception flowch art (2)................................................................... 622 figure 18.9 example of scif receive operation (example with 8-bit data, parity, one st op bit) .................................................... 623 figure 18.10 example of cts control oper ation ...................................................................... 624 figure 18.11 example of rts control oper ation ...................................................................... 624 figure 18.12 data format in synchronous co mmunication ...................................................... 625 figure 18.13 sample scif initiali zation flowchart (1) (transmission) .................................... 626 figure 18.13 sample scif initia lization flowchart (2) (receptio n).......................................... 627 figure 18.13 sample scif initialization flowchart (3) (simultaneous transmi ssion and recep tion) ........................................................ 628 figure 18.14 sample serial transmission flowchart (1) (first transmission af ter initializa tion) ................................................................. 629 figure 18.14 sample serial transmission flowchart (2) (second and subsequent transmission) ................................................................ 630 figure 18.15 sample serial reception flowch art (1) (first reception after initialization) ....... 631 figure 18.15 sample serial reception flowch art (2) (second and subsequent reception) ...... 632 figure 18.16 sample simultaneous seri al transmission and reception flowchart (1) (first transfer afte r initializat ion) ......................................................................... 633 figure 18.16 sample simultaneous seri al transmission and reception flowchart (2) (second and subsequent transfer) ........................................................................ 634 figure 18.17 receive data sampli ng timing in asynchronous mode ...................................... 638 section 19 infrared data association module (irda) figure 19.1 bloc k diagram of irda........................................................................................... 6 39 figure 19.2 transm it/receive oper ation.................................................................................... 643 rev. 3.00 jan. 18, 2008 page xlii of lxii section 20 i 2 c bus interface (iic) figure 20.1 block diagram of i 2 c bus inte rface ....................................................................... 646 figure 20.2 external circu it connections of i/o pins ................................................................ 647 figure 20.3 i 2 c bus form ats ...................................................................................................... 660 figure 20.4 i 2 c bus timi ng........................................................................................................ 661 figure 20.5 master transmit mode operation timing (1)......................................................... 662 figure 20.6 master transmit mode operation timing (2)......................................................... 663 figure 20.7 master receive mode operation timing (1) .......................................................... 664 figure 20.8 master receive mode operation timing (2) .......................................................... 665 figure 20.9 slave transmit mode operation timing (1) ........................................................... 666 figure 20.10 slave transmit mode operation timing (2) ......................................................... 667 figure 20.11 slave receive mode operation timing (1)........................................................... 668 figure 20.12 slave receive mode operation timing (2)........................................................... 669 figure 20.13 block diagra m of noise co nceller ....................................................................... 670 figure 20.14 sample flowchar t for master tr ansmit mode ...................................................... 671 figure 20.15 sample flowchar t for master r eceive mode ........................................................ 672 figure 20.16 sample flowchar t for slave tran smit mode......................................................... 673 figure 20.17 sample flowch art for slave r eceive mode .......................................................... 674 figure 20.18 the timing of th e bit synchronou s circuit .......................................................... 676 section 21 serial i/o with fifo (siof) figure 21.1 bloc k diagram of siof .......................................................................................... 68 0 figure 21.2 se rial cloc k supply.............................................................................................. ... 709 figure 21.3 serial data synchronizati on timing ....................................................................... 711 figure 21.4 siof tr ansmit/receive timing .............................................................................. 712 figure 21.5 transmit/receiv e data bit a lignment .................................................................... 715 figure 21.6 control data bit alig nment .................................................................................... 716 figure 21.7 control data interface (slot position) ..................................................................... 717 figure 21.8 control data interface (seconda ry fs) ................................................................... 718 figure 21.9 example of transm it operation in ma ster mode.................................................... 721 figure 21.10 example of receive operation in ma ster mode ................................................... 722 figure 21.11 example of tran smit operation in slave mode .................................................... 723 figure 21.12 example of recei ve operation in slave m ode ..................................................... 724 figure 21.13 transmit and receive timing (8-bit monaur al data (1))..................................... 729 figure 21.14 transmit and receive timing (8-bit monaur al data (2))..................................... 730 figure 21.15 transmit and receive ti ming (16-bit monaur al data (1))................................... 730 figure 21.16 transmit and receive timing (16-bit ster eo data (1)) ........................................ 731 figure 21.17 transmit and receive timing (16-bit ster eo data (2)) ........................................ 731 figure 21.18 transmit and receive timing (16-bit ster eo data (3)) ........................................ 732 figure 21.19 transmit and receive timing (16-bit ster eo data (4)) ........................................ 732 rev. 3.00 jan. 18, 2008 page xliii of lxii figure 21.20 transmit and receive timing (16-bit st ereo data).............................................. 733 figure 21.21 fr ame length (32-bit)........................................................................................... 734 section 22 analog front end interface (afeif) figure 22.1 block diag ram of afe interface............................................................................. 735 figure 22.2 fifo interrupt timing............................................................................................ .748 figure 22.3 ringing inte rrupt occurrence timing ..................................................................... 749 figure 22.4 interrupt generator .............................................................................................. .... 749 figure 22.5 af e serial interface............................................................................................. ... 750 figure 22.6 afe control sequence............................................................................................ 7 51 figure 22.7 daa block diagram............................................................................................... 7 52 figure 22.8 ringing detect sequence ........................................................................................ 75 3 section 23 usb pin multiplex controller figure 23.1 block diagra m of usb pin multiplexer ................................................................ 755 figure 23.2 example 1 of transceiver connection for usb function controller (on-chip transceiver is used)................................................................................ 759 figure 23.3 example 2 of transceiver connection for usb function controller (on-chip transceiver is not us ed).......................................................................... 760 figure 23.4 example 1 of transcei ver connection for usb host controller (on-chip transceiver is used)................................................................................ 762 figure 23.5 example 2 of transcei ver connection for usb host controller (on-chip transceiver is not us ed).......................................................................... 763 section 25 usb function controller (usbf) figure 25.1 block diagram of usbf ......................................................................................... 804 figure 25.2 example of endpoint config uration ........................................................................ 835 figure 25.3 cable c onnection oper ation ................................................................................... 837 figure 25.4 cable disc onnection oper ation............................................................................... 838 figure 25.5 transfer stag es in control transfer ........................................................................ 839 figure 25.6 set up stage operation ............................................................................................ .840 figure 25.7 data stage (control-in) op eration .......................................................................... 841 figure 25.8 data stage (control-out) op eration........................................................................ 842 figure 25.9 status stage (control-in) operation ........................................................................ 843 figure 25.10 status stage (control-out) op eration ................................................................... 844 figure 25.11 ep1 bulk-out transfer operation......................................................................... 845 figure 25.12 ep2 bulk-i n transfer operation............................................................................ 846 figure 25.13 ep3 interrupt- in transfer operation ..................................................................... 848 figure 25.14 ep4 isochronous-out tran sfer operation (sof is normal).................................. 849 figure 25.15 ep4 isochronous-out tran sfer operation (sof is broken) .................................. 850 rev. 3.00 jan. 18, 2008 page xliv of lxii figure 25.16 ep5 isochronous-in tran sfer operation (sof is normal) .................................... 852 figure 25.17 ep5 isochronous-in tran sfer operation (sof in broken) .................................... 853 figure 25.18 forcible stall by app lication ................................................................................ 857 figure 25.19 automatic stall by usb function controller........................................................ 858 figure 25.20 set timing of tr interr upt flag............................................................................ 861 section 26 lcd controller (lcdc) figure 26.1 lcdc block diagram............................................................................................. 86 4 figure 26.2 valid displa y and the retr ace period ..................................................................... 898 figure 26.3 color-p alette data format....................................................................................... 9 05 figure 26.4 power-supply control sequ ence and states of the lcd m odule ........................... 911 figure 26.5 power-supply control sequ ence and states of the lcd m odule ........................... 911 figure 26.6 power-supply control sequ ence and states of the lcd m odule ........................... 912 figure 26.7 power-supply control sequ ence and states of the lcd m odule ........................... 912 figure 26.8 operation for hard ware rotation (normal mode).................................................. 916 figure 26.9 operation for hard ware rotation (rot ation mode) ................................................ 917 figure 26.10 clock and lc d data signal example................................................................... 918 figure 26.11 clock and lcd data signal example (stn monochrome 8-bit data bus module) ........................................................ 918 figure 26.12 clock and lcd data signal ex ample (stn color 4-bit data bus module)........ 919 figure 26.13 clock and lcd data signal ex ample (stn color 8-bit data bus module)........ 919 figure 26.14 clock and lcd data signal ex ample (stn color 12-bit data bus module)...... 920 figure 26.15 clock and lcd data signal ex ample (stn color 16-bit data bus module)...... 921 figure 26.16 clock and lcd data signal example (dstn monochrome 8-bit da ta bus module) ..................................................... 922 figure 26.17 clock and lcd data signal example (dstn monochrome 16-bit da ta bus modu le) ................................................... 922 figure 26.18 clock and lcd data signal ex ample (dstn color 8-bit data bus module)..... 923 figure 26.19 clock and lcd data signal example (dstn color 12-bit data bus module)... 923 figure 26.20 clock and lcd data signal example (dstn color 16-bit data bus module)... 924 figure 26.21 clock and lcd data signal ex ample (tft color 16-bit data bus module) ...... 925 figure 26.22 clock and lcd data si gnal example (8-bit interface color 640 480)............. 926 figure 26.23 clock and lcd data si gnal example (16-b it interface color 640 480)........... 927 section 27 a/d converter figure 27.1 block diag ram of a/d c onverter ........................................................................... 930 figure 27.2 example of a/d converter oper ation (single mode, channel 1 selected) ............ 937 figure 27.3 example of a/d converter operation (multi mode, channels an0 to an2 sel ected) ...................................................... 939 rev. 3.00 jan. 18, 2008 page xlv of lxii figure 27.4 example of a/d converter operation (scan mode, channels an0 to an2 selected)........................................................ 941 figure 27.5 a/d conversion timing .......................................................................................... 94 2 figure 27.6 external trigger input timing ................................................................................ 943 figure 27.7 definitions of a/d conversion accuracy ............................................................... 945 figure 27.8 analog i nput circuit ex ample................................................................................. 949 figure 27.9 example of anal og input protection circuit ........................................................... 950 figure 27.10 analog input pin equivalent circuit ..................................................................... 951 section 28 d/a converter (dac) figure 28.1 block diag ram of d/a c onverter ........................................................................... 953 figure 28.2 d/a conver ter operation example ......................................................................... 956 section 29 pc card controller (pcc) figure 29.1 pc card co ntroller block diagram......................................................................... 958 figure 29.2 continuous 32-mbyte area mode........................................................................... 960 figure 29.3 continuous 16-m byte area mode (area 6)............................................................. 961 figure 29.4 interface........................................................................................................ ........... 976 figure 29.5 pcmcia memory card interface ba sic timing..................................................... 980 figure 29.6 pcmcia memory card interface wait timing...................................................... 981 figure 29.7 pcmcia i/o ca rd interface basic timing ............................................................. 982 figure 29.8 pcmcia i/o ca rd interface wa it timing .............................................................. 983 figure 29.9 dynamic bus sizing timi ng for pcmcia i/o ca rd interface ............................... 984 section 30 sim card module (sim) figure 30.1 sm art card interface ............................................................................................. .. 988 figure 30.2 data format us ed by smart card interface .......................................................... 1007 figure 30.3 examples of start character waveforms .............................................................. 1010 figure 30.4 example of initializati on flow .............................................................................. 1013 figure 30.5 example of transmit pro cessing........................................................................... 1015 figure 30.6 example of receive pro cessing ............................................................................ 1017 figure 30.7 receive data samp ling timing in smar t card m ode ........................................... 1020 figure 30.8 retransmission when smart card interface is in receive mode........................... 1022 figure 30.9 retransmit standby mode (clock stopped) when smart card interface is in transm it mode................................................... 1023 figure 30.10 procedure for st opping clock and restartin g ..................................................... 1024 figure 30.11 example of pin conn ections in smart ca rd interface......................................... 1025 figure 30.12 teie set timing ................................................................................................. 1026 rev. 3.00 jan. 18, 2008 page xlvi of lxii section 31 multimedia card interface (mmcif) figure 31.1 block diagram of mmcif.................................................................................... 1028 figure 31.2 example of command sequence for commands that do not require command response............................................................... 1060 figure 31.3 operational flow for commands that do not require command response......... 1061 figure 31.4 example of command sequen ce for commands without data transfer (no data busy state) ............................................................................................. 1063 figure 31.5 example of command sequen ce for commands without data transfer (with data busy state)........................................................................................... 1064 figure 31.6 operational flowchart for commands without data transfer .............................. 1065 figure 31.7 example of command sequence for commands with read data (block size fifo size) ...................................................................................... 1067 figure 31.8 example of command sequence for commands with read data (block size > fi fo size) ...................................................................................... 1068 figure 31.9 example of command sequence for commands with read data (multiblock tr ansfer) ............................................................................................ 1069 figure 31.10 example of command sequence for commands with read data (stream transfer) ................................................................................................ 1070 figure 31.11 operational flowchart for commands with read data (single block tr ansfer) ....................................................................................... 1071 figure 31.12 operational flowchart for commands with read data (open-ended multiblock transfer) (1) ................................................................ 1072 figure 31.12 operational flowchart for commands with read data (open-ended multiblock transfer) (2) ................................................................ 1073 figure 31.13 operational flowchart for commands with read data (pre-defined multiblock transfer) (1) ................................................................. 1074 figure 31.13 operational flowchart for commands with read data (pre-defined multiblock transfer) (2) ................................................................. 1075 figure 31.14 operational flowchart for comma nds with read data (stream transfer) ......... 1076 figure 31.15 example of command sequence for commands with write data (block size fifo size) .................................................................................... 1078 figure 31.16 example of command sequence for commands with write data (block size > fifo size) .................................................................................... 1079 figure 31.17 example of command sequence for commands with write data (multiblock tr ansfer) .......................................................................................... 1080 figure 31.18 example of command sequence for commands with write data (stream transfer) ................................................................................................ 1081 figure 31.19 operational flowch art for commands with write data (single block tr ansfer) ....................................................................................... 1082 rev. 3.00 jan. 18, 2008 page xlvii of lxii figure 31.20 operational flowch art for commands with write data (open-ended multiblock transfer) (1) ................................................................ 1083 figure 31.20 operational flowch art for commands with write data (open-ended multiblock transfer) (2) ................................................................ 1084 figure 31.21 operational flowch art for commands with write data (pre-defined multiblock transfer) (1) ................................................................. 1085 figure 31.21 operational flowch art for commands with write data (pre-defined multiblock transfer) (2) ................................................................. 1086 figure 31.22 operational flowchart for comma nds with write data (stream transfer) ....... 1087 figure 31.23 operational flowchart for r ead sequence (single block transfer) ................... 1090 figure 31.24 operational fl owchart for read sequence (open-ended multiblock transfer) (1) ................................................................ 1091 figure 31.24 operational fl owchart for read sequence (open-ended multiblock transfer) (2) ................................................................ 1092 figure 31.25 operational fl owchart for read sequence (pre-defined multiblock transfer) (1) ................................................................. 1093 figure 31.25 operational fl owchart for read sequence (pre-defined multiblock transfer) (2) ................................................................. 1094 figure 31.26 operational flowchart for r ear sequence (stream read transfer) .................... 1095 figure 31.27 operational flowchart fo r pre-defined multiblock read transfer in auto mode (1) ................................................................................................. 1096 figure 31.27 operational flowchart fo r pre-defined multiblock read transfer in auto mode (2) ................................................................................................. 1097 figure 31.28 operational flowchart for write sequence (single block transfer) .................. 1100 figure 31.29 operational flowchart for write sequence (open-ended multiblock transfer) (1) ................................................................ 1101 figure 31.29 operational flowchart for write sequence (open-ended multiblock transfer) (2) ................................................................ 1102 figure 31.30 operational flowchart for write sequence (pre-defined multiblock transfer) (1) ................................................................. 1103 figure 31.30 operational flowchart for write sequence (pre-defined multiblock transfer) (2) ................................................................. 1104 figure 31.31 operational flowchart for write sequence (stream write transfer).................. 1105 figure 31.32 operational flowchart fo r pre-defied multiblock write transfer in auto mode (1) ................................................................................................. 1106 figure 31.32 operational flowchart fo r pre-defied multiblock write transfer in auto mode (2) ................................................................................................. 1107 section 33 user break controller (ubc) figure 33.1 block diagram of ubc......................................................................................... 1112 rev. 3.00 jan. 18, 2008 page xlviii of lxii section 35 i/o ports figure 35.1 port a ........................................................................................................... ......... 1179 figure 35.2 port b ........................................................................................................... ......... 1181 figure 35.3 port c ........................................................................................................... ......... 1183 figure 35.4 port d ........................................................................................................... ......... 1185 figure 35.5 port e........................................................................................................... .......... 1187 figure 35.6 port f........................................................................................................... .......... 1190 figure 35.7 port g ........................................................................................................... ......... 1193 figure 35.8 port h ........................................................................................................... ......... 1195 figure 35.9 port j ........................................................................................................... .......... 1197 figure 35.10 port k .......................................................................................................... ........ 1199 figure 35.11 port l.......................................................................................................... ......... 1201 figure 35.12 port m.......................................................................................................... ........ 1203 figure 35.13 port p.......................................................................................................... ......... 1205 figure 35.14 port r .......................................................................................................... ........ 1207 figure 35.15 port s.......................................................................................................... ......... 1209 figure 35.16 port t.......................................................................................................... ......... 1211 figure 35.17 port u .......................................................................................................... ........ 1213 figure 35.18 port v .......................................................................................................... ........ 1215 section 36 user debugging interface (h-udi) figure 36.1 block diagram of h-udi...................................................................................... 1218 figure 36.2 tap contro ller state tran sitions .......................................................................... 1231 figure 36.3 h-udi da ta transfer timing................................................................................ 1233 figure 36.4 h-udi reset...................................................................................................... .... 1233 section 38 electrical characteristics figure 38.1 extal clock input timing ................................................................................. 1316 figure 38.2 ckio cl ock output timing.................................................................................. 1316 figure 38.3 ckio clock input timing .................................................................................... 1316 figure 38.4 power-on oscillation settlin g time ..................................................................... 1317 figure 38.5 oscillation settling time on return from standby (r eturn by re set).................. 1317 figure 38.6 oscillation settling time on retu rn from standby (return by nmi or irq)....... 1317 figure 38.7 pll synchronization settling ti me by reset, nmi or irq interr upts................. 1318 figure 38.8 re set input timing............................................................................................... . 1320 figure 38.9 interrupt signal input timing................................................................................ 1320 figure 38.10 bu s release timing ............................................................................................ 13 21 figure 38.11 pin drive timing at st andby............................................................................... 1321 figure 38.12 basic bus cycl e in normal sp ace (no wa it)...................................................... 1324 figure 38.13 basic bus cycle in normal space (sof tware wait 1) ......................................... 1325 rev. 3.00 jan. 18, 2008 page xlix of lxii figure 38.14 basic bus cycle in no rmal space (external wait 1 inpu t)................................. 1326 figure 38.15 basic bus cycle in normal space (software wait 1, external wait valid (wm bit = 0), no idle cycle) ............... 1327 figure 38.16 cs extended bus cycle in normal space (sw = 1 cycle, hw = 1 cycle, external wait 1 input) ...................................... 1328 figure 38.17 bus cycle of sram with byte selection (sw = 1 cycle, hw = 1 cycle, external wait 1 input, bas = 0 (ub and lb in write cycle contro lled)) ............................................. 1329 figure 38.18 bus cycle of sram with byte selection (sw = 1 cycle, hw = 1 cycle, external wait 1 input, bas = 1 (we in write cy cle controlle d)) ......................................................... 1330 figure 38.19 read bus cycle of burst rom (software wait 1, external wait 1 input, burst wait 1, number of burst 2)...... 1331 figure 38.20 single read bus cycle of sdram (auto precharge mode, cas latency 2, trcd = 1 cycle, trp = 1 cycle) ...... 1332 figure 38.21 single read bus cycle of sdram (auto precharge mode, cas latency 2, tr cd = 2 cycles, trp = 2 cycles)... 1333 figure 38.22 burst read bus cycle of sdram (single read 8) (auto precharge mode, cas latency 2, tr cd = 1 cycle, trp = 2 cycles) .... 1334 figure 38.23 burst read bus cycle of sdram (single read 8) (auto precharge mode, cas latency 2, trcd = 2 cycles, trp = 1 cycle) .... 1335 figure 38.24 single write bus cycle of sdram (auto precharge mode, trwl = 1 cy cle).......................................................... 1336 figure 38.25 single write bus cycle of sdram (auto precharge mode, trcd = 3 cycles, trwl = 1 cycle) ........................... 1337 figure 38.26 burst write bus cycle of sdram (single write 8) (auto precharge mode, trcd = 1 cycle, tr wl = 1 cy cle)................................................................... 1338 figure 38.27 burst write bus cycle of sdram (single write 8) (auto precharge mode, trcd = 2 cycles, trwl = 1 cycle) ........................... 1339 figure 38.28 burst read bus cycle of sdram (single read 8) (bank active mode: actv + read command, cas latency 2, trcd = 1 cy cle)................................................................................................. 1340 figure 38.29 burst read bus cycle of sdram (single read 8) (bank active mode: read command, same row address, cas latency 2, trcd = 1 cycl e) ...................................................................... 1341 figure 38.30 burst read bus cycle of sdram (single read 8) (bank active mode: pre + actv + read command, different row address, cas late ncy 2, trcd = 1 cycle) ............................... 1342 figure 38.31 burst write bus cycle of sdram (single write 8) (bank active mode: actv + writ command, trcd = 1 cycle) .................. 1343 rev. 3.00 jan. 18, 2008 page l of lxii figure 38.32 burst write bus cycle of sdram (single write 8) (bank active mode: actv + writ command, trcd = 1 cycle) .................. 1344 figure 38.33 burst write bus cycle of sdram (single write 8) (bank active mode: pre + actv + writ command, trcd = 1 cycle)....... 1345 figure 38.34 auto refresh timi ng of sdram (trp = 2 cycles ) .......................................... 1346 figure 38.35 self refresh timi ng of sdram (trp = 2 cycles ) ............................................ 1347 figure 38.36 power-on sequence of sdram (mode write timing, trp = 2 cycles).......... 1348 figure 38.37 write to read bus cy cle in power-down mode of sdram (auto precharge mode, trcd = 1 cycle, trp = 1 cycle, trwl = 1 cycle)... 1349 figure 38.38 read to write bus cycle in power-down mode of sdram (auto precharge mode, trcd = 1 cycle, trp = 1 cycle, trwl = 1 cycle)... 1350 figure 38.39 pcmcia memory card interface bus timing ................................................... 1351 figure 38.40 pcmcia memory card interface bus timing (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait 1, hardware wa it 1) ................................................................................................ 1352 figure 38.41 pcmcia i/o ca rd interface bu s timing............................................................ 1353 figure 38.42 pcmcia i/o card interface bus timing (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait 1, hardware wa it 1) ................................................................................................ 1354 figure 38.43 refout , irqout delay ti me ........................................................................ 1354 figure 38.44 i/o port timing ................................................................................................. .. 1355 figure 38.45 dreq input timing (dreq low level is detected) ........................................ 1355 figure 38.46 dack output timing......................................................................................... 1355 figure 38.47 tpu output timing ............................................................................................. 135 6 figure 38.48 tpu cl ock input ti ming..................................................................................... 1356 figure 38.49 oscillation settling time when rtc crystal oscillato r is turned on ............... 1357 figure 38.50 sck i nput clock ti ming .................................................................................... 1358 figure 38.51 scif input/output timing in synchr onous mode .............................................. 1359 figure 38.52 i 2 c bus interface input/o utput timing ............................................................... 1361 figure 38.53 siof_m clk input ti ming................................................................................. 1362 figure 38.54 siof transmission/reception timing (master mode 1, fall sampling)............ 1363 figure 38.55 siof transmission/reception timing (master mode 1, rise sampling)........... 1363 figure 38.56 siof transmission/reception timing (master mode 2, fall sampling)............ 1364 figure 38.57 siof transmission/reception timing (master mode 2, rise sampling)........... 1364 figure 38.58 siof transmission/reception timing (slave mode 1, slave mode 2) .............. 1365 figure 38.59 afeif module ac timing ................................................................................. 1366 figure 38.60 usb clock timing.............................................................................................. 13 67 figure 38.61 lcdc m odule signal timing ............................................................................. 1369 figure 38.62 sim m odule signal timing ................................................................................ 1370 figure 38.63 mmcif transmit timing ................................................................................... 1371 rev. 3.00 jan. 18, 2008 page li of lxii figure 38.64 mmcif receive timing (rise sampling) .......................................................... 1371 figure 38.65 tc k input timing............................................................................................... 1 372 figure 38.66 trst input timing (res et hold )........................................................................ 1373 figure 38.67 h-udi da ta transfer timing .............................................................................. 1373 figure 38.68 asemd0 input timing....................................................................................... 1373 figure 38.69 output load circuit............................................................................................. 1375 appendix figure c.1 package dimensions (plbg0256ga-a (bp-256h/hv))...................................... 1392 figure c.2 package dimensions (plbg0256ka-a (b p-256c/cv )) ...................................... 1393 rev. 3.00 jan. 18, 2008 page lii of lxii rev. 3.00 jan. 18, 2008 page liii of lxii tables section 1 overview table 1.1 sh7720/SH7721 features......................................................................................... 2 table 1.2 product lineup (s h7720 group).............................................................................. 8 table 1.3 product lineup (s h7721 group).............................................................................. 9 table 1.4 list of pin assignments .......................................................................................... 13 table 1.5 sh7720/SH7721 pi n functions .............................................................................. 25 section 2 cpu table 2.1 virtual address space............................................................................................. 40 table 2.2 register initia l values............................................................................................. 43 table 2.3 addressing modes and effective ad dresses for cpu instructions......................... 56 table 2.4 cpu instruction formats ........................................................................................ 60 table 2.5 cpu instruction types............................................................................................ 63 table 2.6 data transfer instructions....................................................................................... 67 table 2.7 arithmetic operatio n instructions .......................................................................... 69 table 2.8 logic operation instructions .................................................................................. 71 table 2.9 shift instru ctions..................................................................................................... 72 table 2.10 branch instructions ................................................................................................. 73 table 2.11 system control instructions.................................................................................... 74 table 2.12 operation code map............................................................................................... 77 section 3 dsp operating unit table 3.1 cpu processing modes .......................................................................................... 83 table 3.2 virtual address space............................................................................................. 84 table 3.3 operation of sr bits in each processing mode ..................................................... 87 table 3.4 rs and re setting rule.......................................................................................... 93 table 3.5 repeat control instructions .................................................................................... 93 table 3.6 repeat contro l macros ........................................................................................... 94 table 3.7 dsp mode extended system control instructions ................................................. 96 table 3.8 pc value during repeat control (when rc[11:0] 2) ......................................... 99 table 3.9 extended system control inst ructions in dsp mode ........................................... 103 table 3.10 overview of data tran sfer instructions................................................................ 106 table 3.11 modulo addressing cont rol instruc tions.............................................................. 108 table 3.12 double data transfer in struction formats ........................................................... 111 table 3.13 single data transfer in struction formats ............................................................. 112 table 3.14 destination register in dsp instru ctions.............................................................. 114 table 3.15 source register in dsp operations ...................................................................... 115 rev. 3.00 jan. 18, 2008 page liv of lxii table 3.16 dsr register bits................................................................................................. 116 table 3.17 dsp operation instru ction form ats...................................................................... 118 table 3.18 correspondence between dsp instruc tion operands and registers ..................... 119 table 3.19 dc bit update definitions ................................................................................... 120 table 3.20 examples of nopx and nopy instruction codes............................................... 122 table 3.21 variation of alu fixed- point opera tions............................................................ 126 table 3.22 correspondence between oper ands and registers ............................................... 126 table 3.23 variation of alu inte ger operations ................................................................... 131 table 3.24 variation of alu logi cal operations .................................................................. 133 table 3.25 variation of fixed-point multiply oper ation ....................................................... 135 table 3.26 correspondence between oper ands and registers ............................................... 136 table 3.27 variation of shif t operations................................................................................ 137 table 3.28 operation definition of pdmsb .......................................................................... 143 table 3.29 variation of pdms b operation............................................................................ 144 table 3.30 variation of roundin g operation ......................................................................... 145 table 3.31 definition of overflow protection for fixed-point arithmetic operations .......... 146 table 3.32 definition of overflow protection fo r integer arithmetic operations.................. 146 table 3.33 variation of local data move oper ations............................................................ 147 table 3.34 correspondence between oper ands and registers ............................................... 148 table 3.35 dsp mode extended system control instructions ............................................... 149 table 3.36 double data transfer instruction ......................................................................... 151 table 3.37 single data transfer instructions ......................................................................... 152 table 3.38 correspondence between dsp data tran sfer operands and registers ................ 153 table 3.39 dsp operation in structions .................................................................................. 154 table 3.40 operation code map............................................................................................. 160 section 4 memory ma nagement unit (mmu) table 4.1 access states designated by d, c, and pr bits ................................................... 183 section 5 cache table 5.1 number of entries and size/wa y in each c ache size.......................................... 197 table 5.2 lru and way replacement (when cache locking mechanism is disabled)...... 199 table 5.3 way replacement when a pref inst ruction misses th e cache ........................... 203 table 5.4 way replacement when instructions ot her than the pref instruction miss the c ache...................................................................................................... 203 table 5.5 lru and way replacement (when w2lo ck = 1 and w3lock =0)................ 203 table 5.6 lru and way replacement (when w2lo ck = 0 and w3lock =1)................ 204 table 5.7 lru and way replacement (when w2lo ck = 1 and w3lock =1)................ 204 table 5.8 address format based on the size of c ache to be assigned to memory............. 211 rev. 3.00 jan. 18, 2008 page lv of lxii section 6 x/y memory table 6.1 x/y memory virtua l addresse s ........................................................................... 213 table 6.2 mmu and cache settings..................................................................................... 216 section 7 exception handling table 7.1 exception event vectors....................................................................................... 225 table 7.2 instruction positions and restriction types.......................................................... 235 table 7.3 spc value when a re-execution type exception occurs in repeat control (sr.rc[11:0] 2)................................................................................................... 237 table 7.4 exception acceptance in the repeat loop ........................................................... 239 table 7.5 instruction where a specific exception occurs when a memory access exception occurs in repeat control (sr.rc[11:0] 1)................................................................................................... 240 section 8 interrupt controller (intc) table 8.1 pin configuration.................................................................................................. 245 table 8.2 interrupt sources and ipra to iprj ..................................................................... 248 table 8.3 interrupt exception handling sources and priority (irq mode) ......................... 270 table 8.4 interrupt exception handling sources and priority (irl mode).......................... 272 table 8.5 interrupt level and intevt code....................................................................... 275 section 9 bus state controller (bsc) table 9.1 pin configuration.................................................................................................. 283 table 9.2 address space map 1 (cmncr.map = 0).......................................................... 287 table 9.3 address space map 2 (cmncr.map = 1).......................................................... 288 table 9.4 correspondence between external pins (md3 and md4), memory type of cs0, an d memory bus width................................................... 289 table 9.5 correspondence between external pin (md5) and endians ................................. 289 table 9.6 32-bit external device/big endian access and data alignment ......................... 331 table 9.7 16-bit external device/big endian access and data alignment ......................... 332 table 9.8 8-bit external device/big endian access and data alignment........................... 333 table 9.9 32-bit external device/little endian access and data alignment ...................... 334 table 9.10 16-bit external device/little endian access and data alignment ...................... 335 table 9.11 8-bit external device/little endian access and data alignment ........................ 336 table 9.12 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (1)-1..................................................................... 349 table 9.12 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (1)-2..................................................................... 350 table 9.13 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (2)-1..................................................................... 351 rev. 3.00 jan. 18, 2008 page lvi of lxii table 9.13 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (2)-2..................................................................... 352 table 9.14 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (3) ........................................................................ 353 table 9.15 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (4)-1..................................................................... 354 table 9.15 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (4)-2..................................................................... 355 table 9.16 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (5)-1..................................................................... 356 table 9.16 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (5)-2..................................................................... 357 table 9.17 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (6)-1..................................................................... 358 table 9.17 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (6)-2..................................................................... 359 table 9.18 relationship between access size and number of bursts.................................... 360 table 9.19 access address in sdram m ode register write ............................................... 380 table 9.20 output addresses when emrs command is issued ............................................ 383 table 9.21 relationship between bus width, acce ss size, and number of bursts................ 386 section 10 direct memory access controller (dmac) table 10.1 pin configuration.................................................................................................. 409 table 10.2 transfer request sources ..................................................................................... 423 table 10.3 selecting external request modes with rs bits .................................................. 426 table 10.4 selecting external request det ection with dl, ds bits ...................................... 427 table 10.5 selecting external request de tection with do bit .............................................. 427 table 10.6 selecting on-chip peripheral module re quest modes with rs3 to rs0 bits ..... 429 table 10.7 supported dma transfers.................................................................................... 434 table 10.8 relationship between request modes and bus modes by dma transfer category.................................................................................. 441 section 11 clock pulse generator (cpg) table 11.1 pin configuration.................................................................................................. 457 table 11.2 clock operatin g modes ........................................................................................ 458 table 11.3 possible combination of clock mode and frqcr values ................................. 459 section 13 power-down modes table 13.1 states of power- down modes .............................................................................. 478 table 13.2 pin configuration.................................................................................................. 479 rev. 3.00 jan. 18, 2008 page lvii of lxii section 14 timer unit (tmu) table 14.1 tmu interrupt sources ......................................................................................... 509 section 15 16-bit timer pulse unit (tpu) table 15.1 tpu functio ns ...................................................................................................... 512 table 15.2 tpu pin config urations........................................................................................ 514 table 15.3 tpu clock sources............................................................................................... 518 table 15.4 tpsc2 to tpsc0 (1)............................................................................................. 518 table 15.4 tpsc2 to tpsc0 (2)............................................................................................. 518 table 15.4 tpsc2 to tpsc0 (3)............................................................................................. 519 table 15.4 tpsc2 to tpsc0 (4)............................................................................................. 519 table 15.5 ioa2 to ioa0 ....................................................................................................... 522 table 15.6 register combinations in buffer operation ......................................................... 534 table 15.7 phase counting mode cl ock input pins ............................................................... 539 table 15.8 up/down-count conditions in phase counting mode 1...................................... 541 table 15.9 up/down-count conditions in phase counting mode 2...................................... 542 table 15.10 up/down-count conditions in phase counting mode 3...................................... 543 table 15.11 up/down-count conditions in phase counting mode 4...................................... 544 section 17 realtime clock (rtc) table 17.1 pin configuration.................................................................................................. 561 table 17.2 recommended oscillator circuit cons tants (recommended values).................. 584 section 18 serial communicati on interface with fifo (scif) table 18.1 pin configuration................................................................................................... 588 table 18.2 scsmr settings and scif transmit/receive ...................................................... 614 table 18.3 serial transmit/recei ve format s.......................................................................... 615 table 18.4 scif interrup t sources ......................................................................................... 636 section 19 infrared data association module (irda) table 19.1 pin configuration.................................................................................................. 640 section 20 i 2 c bus interface (iic) table 20.1 i 2 c bus interface pins........................................................................................... 648 table 20.2 transfer rate ........................................................................................................ 659 table 20.3 interrupt re quests ................................................................................................. 675 table 20.4 time for monitoring scl..................................................................................... 676 section 21 serial i/o with fifo (siof) table 21.1 pin configuration.................................................................................................. 681 rev. 3.00 jan. 18, 2008 page lviii of lxii table 21.2 operation in each transfer mode......................................................................... 685 table 21.3 siof serial cloc k frequency ............................................................................... 710 table 21.4 serial transfer modes........................................................................................... 713 table 21.5 frame length........................................................................................................ 714 table 21.6 audio mode specification for transmit data....................................................... 716 table 21.7 audio mode specification for receive data ........................................................ 716 table 21.8 setting number of channels in control data ....................................................... 717 table 21.9 conditions to issue transmit request .................................................................. 719 table 21.10 conditions to issue receive request .................................................................... 720 table 21.11 transmit and recei ve reset.................................................................................. 725 table 21.12 siof interrupt sources ......................................................................................... 727 section 22 analog front end interface (afeif) table 22.1 pin configuration.................................................................................................. 736 table 22.2 fifo interrupt size............................................................................................... 738 table 22.3 telephone number and data ................................................................................ 745 section 23 usb pin multiplex controller table 23.1 pin configuration (digital transceiver signal) .................................................... 756 table 23.2 pin configuration (analog transceiver signal) ................................................... 756 table 23.3 pin configuration (power control si gnal)............................................................ 757 table 23.4 pin configuration (c lock signal) ......................................................................... 757 section 24 usb ho st controller (usbh) table 24.1 pin configuration.................................................................................................. 766 section 25 usb function controller (usbf) table 25.1 pin configuration and functions .......................................................................... 805 table 25.2 restrictions of se ttable values ............................................................................. 834 table 25.3 example of endpoint configura tion..................................................................... 834 table 25.4 example of setting of endpoint configuration in formation ................................ 835 table 25.5 command decoding on a pplication side ............................................................ 855 section 26 lcd controller (lcdc) table 26.1 pin configuration.................................................................................................. 865 table 26.2 i/o clock frequency and cl ock division ratio ................................................... 868 table 26.3 limits on the resolution of rotated displays, burst length, and connected memory (32-bit sdram)............................................................ 899 table 26.4 limits on the resolution of rotated displays, burst length, and connected memory (16-bit sdram)............................................................ 902 rev. 3.00 jan. 18, 2008 page lix of lxii table 26.5 available power-supply control-sequence periods at typical frame rates....... 913 table 26.6 lcdc operatin g modes ....................................................................................... 914 table 26.7 lcd module power-su pply stat es....................................................................... 914 section 27 a/d converter table 27.1 pin configuration.................................................................................................. 931 table 27.2 analog input channels and a/d data regi sters................................................... 932 table 27.3 a/d conversion time (single mode)................................................................... 943 table 27.4 conditions for the method of transferring results of a/d conversion and inclusion of su perfluous dma ...................................................................... 947 table 27.5 analog input pin ratings...................................................................................... 950 section 28 d/a converter (dac) table 28.1 pin configuration.................................................................................................. 954 section 29 pc card controller (pcc) table 29.1 features of the pc mcia inte rface ....................................................................... 959 table 29.2 pcc pin config uration ......................................................................................... 962 table 29.3 pcmcia support interface .................................................................................. 977 section 30 sim card module (sim) table 30.1 pin configuration.................................................................................................. 989 table 30.2 register settings for sm art card in terface ......................................................... 1009 table 30.3 example of bit rates (bits/s) for scbrr settings (p = 19.8 mhz, scsm pl = 3 71)...................................................................... 1011 table 30.4 interrupt sources of sm art card in terface .......................................................... 1018 section 31 multimedia card interface (mmcif) table 31.1 pin configur ation................................................................................................ 1029 table 31.2 correspondence between commands and settings of cmdtyr and rspt yr ...................................................................................................... 1034 table 31.3 cmdr configur ation ......................................................................................... 1037 table 31.4 correspondence between command response byte number and rspr........... 1039 table 31.5 mmcif interrupt sources................................................................................... 1108 section 33 user break controller (ubc) table 33.1 specifying break addr ess regist er .................................................................... 1116 table 33.2 specifying break da ta regist er.......................................................................... 1118 table 33.3 data access cycle addresses and oper and size comparison conditions ......... 1129 rev. 3.00 jan. 18, 2008 page lx of lxii section 34 pin function controller (pfc) table 34.1 multiplexed pins................................................................................................. 1141 section 35 i/o ports table 35.1 port a data register (padr) read/write op erations ....................................... 1180 table 35.2 port b data register (pbdr) read/write op erations ....................................... 1182 table 35.3 port c data register (pcdr) read/write op erations ....................................... 1184 table 35.4 port d data register (pddr) read/write op erations ....................................... 1186 table 35.5 port e data register (pedr) read/write op erations........................................ 1188 table 35.6 port f data register (pfdr) read/write op erations ........................................ 1191 table 35.7 port g data register (pgdr) read/write op erations ....................................... 1194 table 35.8 port h data register (phdr) read/write op erations ....................................... 1196 table 35.9 port j data register (pjdr) read/write op erations.......................................... 1198 table 35.10 port k data register (pkdr) read/write op erations ....................................... 1200 table 35.11 port l data register (pldr) read/write op erations ........................................ 1202 table 35.12 port m data register (pmdr) read/write op erations...................................... 1204 table 35.13 port p data register (ppdr) read/write op erations ........................................ 1206 table 35.14 port r data register (prdr) read/write operations........................................ 1208 table 35.15 port s data register (psdr) read/write op erations ........................................ 1210 table 35.16 port t data register (ptdr) read/write op erations ........................................ 1212 table 35.17 port u data register (pudr) read/write op erations ....................................... 1214 table 35.18 port v data register (pvdr) read/write op erations ....................................... 1216 section 36 user debugging interface (h-udi) table 36.1 pin configur ation................................................................................................ 1219 table 36.2 h-udi commands.............................................................................................. 1221 table 36.3 pins and boundary scan register bits................................................................ 1222 table 36.4 reset configur ation ............................................................................................ 1232 section 38 electrical characteristics table 38.1 absolute maximu m ratings ............................................................................... 1305 table 38.2 recommended timing in power-on .................................................................. 1307 table 38.3 recommended timing in power-off.................................................................. 1308 table 38.4 dc characteristics (1) [common] ...................................................................... 1309 table 38.4 dc characteristics (2-a) [except usb transceiver, i 2 c, adc, dac analog rela ted pins]................................................................................. 1311 table 38.4 dc characteristics (2-b) [i 2 c related pi ns] ....................................................... 1312 table 38.4 dc characteristics (2-c) [usb tr ansceiver related pins] ................................. 1313 table 38.5 permissible output current va lues .................................................................... 1313 table 38.6 maximum operating frequencies....................................................................... 1314 rev. 3.00 jan. 18, 2008 page lxi of lxii table 38.7 clock timi ng ...................................................................................................... 1315 table 38.8 control signal timing ........................................................................................ 1319 table 38.9 bus timi ng ......................................................................................................... 1322 table 38.10 peripheral module si gnal timi ng....................................................................... 1355 table 38.11 16-bit timer pu lse unit ...................................................................................... 1356 table 38.12 rtc signal timing............................................................................................. 1357 table 38.13 scif module si gnal timing............................................................................... 1358 table 38.14 i 2 c bus interface timing .................................................................................... 1360 table 38.15 siof module si gnal timing............................................................................... 1362 table 38.16 afeif module sign al timing ............................................................................ 1365 table 38.17 usb module cloc k timing ................................................................................ 1366 table 38.18 usb electrical characteris tics (full-sp eed)....................................................... 1367 table 38.19 usb electrical characteris tics (low-speed)...................................................... 1367 table 38.20 lcdc module sign al timing............................................................................. 1368 table 38.21 sim module signa l timing ................................................................................ 1369 table 38.22 mmcif module si gnal timing.......................................................................... 1370 table 38.23 h-udi related pi n timing ................................................................................. 1372 table 38.24 a/d converter char acteristic s ............................................................................ 1374 table 38.25 d/a converter char acteristic s ............................................................................ 1374 appendix table a.1 pin stat es ............................................................................................................ 1377 rev. 3.00 jan. 18, 2008 page lxii of lxii section 1 overview rev. 3.00 jan. 18, 2008 page 1 of 1458 rej09b0033-0300 section 1 overview 1.1 features this lsi is a single-chip risc microprocessor that integrates a 32-bit risc-type super h architecture cpu with a digital signal processing (dsp) extension as its core, together with a large-capacity 32-kbyte cache memory, a 16-kbyte x/y memory, and an interrupt controller. high-speed data transfers can be performed by an on-chip direct memory access controller (dmac), and an external memory access support f unction enables direct connection to different kinds of memory. this lsi also supports a stereo audio recording and playback function, a usb host controller, a function controller, an lcd co ntroller, a pcmcia interface, an a/d converter, and a d/a converter. the usb host controller and lcd controller have bus master functions, so that data supplied from an external memory (area 3) can be freely proce ssed. since the usb host controller, in particular, conforms to open hci standards, it is extremel y easy to transfer data from the pc of a device driver or other devices. also, low-power operation suitable for battery operation is possible because the lcd controller continue s to display even in sleep mode. a powerful built-in power management function keeps power consumption low, even during high- speed operation. this lsi is ideal for electronics devices, which require both high speed and low power consumption. the sh7720 group integr ates an ssl (secure socket laye r) accelerator that performs rsa (rivest-shamir-adleman) opera tions and des (data encryption standard) and triple-des encryption/decryption, while the SH7721 group does not have the ssl accelerator. each group consists of several models which includes or doe s not include an sd host interface (sdhi) to be suited to a variety of applications. see table 1.2 and 1.3, product lineup, for the models including (or not including) the sdhi. note: for the detailed specifications of the sdhi and ssl, contact the renesas representatives in your region. table 1.1 shows the feat ures of this lsi. section 1 overview rev. 3.00 jan. 18, 2008 page 2 of 1458 rej09b0033-0300 table 1.1 sh7720/SH7721 features item features cpu ? renesas technology original superh architecture ? upper compatibility with sh-1, sh-2, and sh3-dsp at object code level ? 32-bit internal data bus ? general-register ? sixteen 32-bit general registers (eight 32-bit shadow registers) ? five 32-bit control registers ? four 32-bit system registers ? risc type instruction set ? instruction length: 16-bit fixed length for improved code efficiency ? load/store architecture ? delayed branch instruction ? instruction set based on c language ? instruction execution time: one inst ruction/cycle for basic instructions ? logical address space: 4 gbytes ? space identifier asid: 8 bits, 256 logical address spaces ? five-stage pipeline dsp operating unit ? mixture of 16-bit and 32-bit instructions ? 32-/40-bit internal data bus ? multiplier, alu, barrel shifter, and dsp register ? 16-bit x 16-bit 32-bit one cycle multiplier ? large-capacity dsp data register file ? six 32-bit data registers ? two 40-bit data registers ? extended harvard architecture for dsp data buses ? two data buses ? one instruction bus ? up to four parallel operations: al u, multiply, two loads, and store ? two address units to generating addresses for two memory access ? dsp data addressing modes: increment, index register addition (with or without modulo addressing) ? zero-overhead repeat loop control ? conditional execution instructions ? user dsp mode and privileged dsp mode section 1 overview rev. 3.00 jan. 18, 2008 page 3 of 1458 rej09b0033-0300 item features memory management unit (mmu) ? 4-gbyte address space, 256 address spaces (8-bit asid) ? page unit sharing ? supports multiple page sizes: 1 kbyte or 4 kbytes ? 128-entry, 4-way set associative tlb ? specifies replacement way by softw are and supports random replacement algorithm ? address assignment allows direct access to tlb contents cache memory ? 32-kbyte cache mixing instructions and data ? 512-entry, 4-way set associative, 16-byte block length ? write-back, write-through, least rec ent used (lru) replacement algorithm ? single-stage write-back buffer x/y memory ? user-selectable mapping mechanism ? fixed mapping for mission-critical realtime applications ? automatic mapping through tlb for easy to use ? three independent read/write ports ? 8-/16-/32-bit access from cpu ? up to two 16-bit accesses from dsp ? 8-/16-/32-bit access from dmac ? 8-kbyte ram for x and y memory individual (4 kbytes 4) interrupt controller (intc) ? seven external interrupt pi ns (nmi, irq5 to irq0) ? nmi: fall/rise selectable ? irq: fall/rise/high level/low level selectable ? on-chip peripheral interrupt: se ts priority for each module bus state controller (bsc) ? physical address space is provided to support areas of up to 64 mbytes and 32 mbytes. ? each area allows independent setting of the following functions: ? bus size (8, 16, or 32 bits). an a ccess wait cycle count with a different size to be supported is provided for each area. ? number of access wait cycles. some areas can be inserted wait cycles independently in read access and write access. ? sets of idle wait cycle (for the same or different area) ? supports sram, page mode rom, sdram, and pseudo sram (ready for page mode) by specifying memory to be connected to each area. ? outputs chip select signals to corresponding areas, such as cs0 , cs2 to cs4 , cs5a / cs5b , and cs6a / cs6b section 1 overview rev. 3.00 jan. 18, 2008 page 4 of 1458 rej09b0033-0300 item features direct memory access controller (dmac) ? number of channels: six channels (two channels support external requests) ? address space: 4 gbytes on architecture ? data transfer length: bytes, words (2 bytes), longwords (4 bytes), 16 bytes (longword 4) ? maximum number of transfer times: 16,777,216 times ? address mode: single address mode or dual address mode selectable ? transfer request: selectable from external request, on-chip peripheral module request, and auto request ? bus mode: selectable from cycle steal mode (normal mode and intermittent mode) and burst mode ? priority: selectable from channel priority fixed mode and round robin mode ? interrupt request: supports interrupt request to cpu at the end of data transfer ? external request detection: selectable from dreq input low/high level detection and rising/falling detection ? transfer request acceptance signal: dack and tend can be set an active level clock pulse generator (cpg) ? clock mode: input clock selectable from external clock (extal or ckio) and crystal resonator ? generates three types of clocks ? cpu clock: maximum 133.34 mhz ? bus clock: maximum 66.67 mhz ? peripheral clock: maximum 33.34 mhz ? supports power-down mode ? sleep mode ? standby mode ? module standby mode (x/y memory standby enabled) ? one-channel watchdog timer watchdog timer (wdt) ? one-channel watchdog timer (wdt) ? interrupt request: wdt only timer unit (tmu) ? internal three-channel 32-bit timer ? auto-reload type 32-bit down counter ? internal prescaler for p ? interrupt request section 1 overview rev. 3.00 jan. 18, 2008 page 5 of 1458 rej09b0033-0300 item features 16-bit timer pulse unit (tpu) ? four-channel 16-bit timer ? pwm mode ? four types of counter input clocks ? phase counting mode (two channels) compare match timer (cmt) ? internal six-channel 32-bit counter (16-/32-bit switchable) ? selectable prescaling for p ? internal full-channel compare match function ? with interrupt request and dmac request realtime clock (rtc) ? built-in clock, calendar functions, and alarm functions ? on-chip 32-khz crystal oscillator circ uit with a maximum resolution (cycle interrupt) of 1/256 second serial communication interface with fifo (scif0, scif1) ? includes a 64-byte fifo for transmission and another for reception ? supports high-speed uart for bluetooth ? internal prescaler for p ? with interrupt request and dmac request infrared data association module (irda) ? conforms to the irda 1.0 system ? asynchronous serial communication ? on-chip 64-stage fifo buffers for transmission and reception i 2 c bus interface (iic) ? supports multi master transmission/reception serial i/o with fifo (siof0, siof1) ? includes a 64-byte fifo for transmission and another for reception ? supports 8-/16-/16-bit stereo sound input/output ? sampling rate clock input selectable from p and external pin ? includes a prescaler for p ? interrupt requests and dmac requests analog front end interface (afeif) ? stlc7550 can directly be connected ? data access arrangement function ? 128-word transmit fifo ? 128-word receive fifo section 1 overview rev. 3.00 jan. 18, 2008 page 6 of 1458 rej09b0033-0300 item features usb host controller (usbh) ? conforms to ohci rev. 1.0 ? usb rev. 1.1 compatible ? 127 endpoints ? support interrupt/bulk/control/isochronous mode ? bus master controller (can access area 3 and synchronous dram) ? two ports with analog transceiver (one is common with usb function controller) ? external clock input function usb function controller (usbf) ? conforms to ohci rev. 1.0 ? six endpoints ? support interrupt/bulk/control/isochronous mode ? one port with analog transceiver (comm on with usb function controller), 12 mbps only ? external clock input function lcd controller (lcdc) ? from 16 1 to 1024 1024 pixels can be supported ? 4/8/15/16 bpp (bit per pixel) color pallet ? 1/2/4/6 bpp (bit per pixel) gray scale ? 8-bit frame rate controller ? tft/dstn/stn panels ? signal polarity setting function ? hardware pane l rotation ? power control function ? selectable clock source (lclk, bclk, or pclk) a/d converter (adc) ? 10 bits 4 lsb, four channels ? conversion time: 15 s ? input range: 0 to av cc (max. 3.6 v) d/a converter (dac) ? 8 bits 4 lsb, two channels ? conversion time: 10 s ? output range: 0 to av cc (max. 3.6 v) pc card controller (pcc) ? complies with the pcmcia rev.2.1/jeida version 4.2 ? supports the ic memory card in terface and i/o card interface section 1 overview rev. 3.00 jan. 18, 2008 page 7 of 1458 rej09b0033-0300 item features sim card interface (sim) ? single channel ready for iso7816-3 data protocol (t = 0, t = 1) ? asynchronous half-duplex character transmission protocol ? data length of 8 bits ? generates and checks a parity bit ? number of output clocks per 1 etu selectable ? direct convention/inverse convention selectable ? internal prescaler for p ? clock polarity changeable at idle time (low or high) ? with interrupt request and dmac request multimedia card interface (mmcif) ? complies with the multimedia card system specification version 3.1 ? supports mmc mode ? 16.5-mbps bit rate (max) for the card interface (p = 33 mhz) ? incorporates sixty-four 16-bit data-transfer fifos ? interrupt and dma request ? module standby function sd host interface (sdhi) note: only for models with the sdhi ? supports sdhc (sd high capacity) and sdio ? supports part 1 physical layer ver.1. 01 to 2.0 of sd specification, but not supported for high-speed ? supports part e1 sdio ver. 1. 00 to 2.00 of sd specification ? sd memory/io card interfac e (1 bit/4 bits sd bus) ? sd clock frequency 1/2 peripheral clock frequency ? error check function: crc7 (command/response), crc16 (data) ? mmc (multimedia card) access ? interrupt request and damc transfe r request (sd_buf read/write) ? card detection function ? write protect ssl accelerator (ssl) note: sh7720 group only ? rsa encryption ? supported operations: addition, subtra ction, multiplication, power operation ? des and triple-des encryption/decryption section 1 overview rev. 3.00 jan. 18, 2008 page 8 of 1458 rej09b0033-0300 item features user break controller (ubc) ? two break channels ? all of address, data value, access type, and data size can be set as break conditions. ? supports sequential break function user debugging interface (h-udi) ? supports e10a emulator ? realtime branch trace ? 1-kbyte on-chip memory for execut ing high-speed emulation program table 1.2 product lineup (sh7720 group) power supply voltage model i/o internal operating frequency product code package ssl sdhi hd6417720bp133c 256-pin 17mm x 17mm csp (plbg0256ga-a) o ? hd6417720bp133cv 256-pin 17mm x 17mm csp (plbg0256ga-a) o ? hd6417720bl133c 256-pin 11mm x 11mm csp (plbg0256ka-a) o ? sh7720 hd6417720bl133cv 256-pin 11mm x 11mm csp (plbg0256ka-a) o ? hd6417320bp133c 256-pin 17mm x 17mm csp (plbg0256ga-a) o o hd6417320bp133cv 256-pin 17mm x 17mm csp (plbg0256ga-a) o o hd6417320bl133c 256-pin 11mm x 11mm csp (plbg0256ka-a) o o sh7320 3.3 v 0.3v 1.5 v 0.1v 133.34 mhz hd6417320bl133cv 256-pin 11mm x 11mm csp (plbg0256ka-a) o o [legend] o: provided; ? : not provided section 1 overview rev. 3.00 jan. 18, 2008 page 9 of 1458 rej09b0033-0300 table 1.3 product lineup (SH7721 group) power supply voltage model i/o internal operating frequency product code package ssl sdhi r8a77210c133bg 256-pin 17mm x 17mm csp (plbg0256ga-a) ? ? r8a77210c133bgv 256-pin 17mm x 17mm csp (plbg0256ga-a) ? ? r8a77210c133ba 256-pin 11mm x 11mm csp (plbg0256ka-a) ? ? r8a77210c133bav 256-pin 11mm x 11mm csp (plbg0256ka-a) ? ? r8a77211c133bg 256-pin 17mm x 17mm csp (plbg0256ga-a) ? o r8a77211c133bgv 256-pin 17mm x 17mm csp (plbg0256ga-a) ? o r8a77211c133ba 256-pin 11mm x 11mm csp (plbg0256ka-a) ? o SH7721 3.3 v 0.3v 1.5 v 0.1v 133.34 mhz r8a77211c133bav 256-pin 11mm x 11mm csp (plbg0256ka-a) ? o [legend] o: provided; ? : not provided section 1 overview rev. 3.00 jan. 18, 2008 page 10 of 1458 rej09b0033-0300 1.2 block diagram super h cpu core usb host controller (usbh) ldc controller (lcdc) 512-byte ram 576-byte sram 128-byte ram 256-byte sram 256-byte sram 2.56-kbyte line buffer x/y memory instruction/data for cpu/dsp (16 kbytes) dsp core x bus cpu bus internal bus peripheral bus peripheral bus external bus internal bus y bus user break controller (ubc) bus state controller (bsc) user debugging interface (h-udi) analog front end interface (afeif) multimediacard interface (mmcif) sim card interface (sim) pc card controller (pcc) sd host interface (sdhi) serial i/o with fifo (siof0) serial i/o with fifo (siof1) usb function controller 1-kbyte fifo (usbf) serial communication interface 0 with fifo 128-byte fifo (scif0/irda) serial communication interface 1 with fifo 128-byte fifo (scif1) interrupt controller (intc) compare match timer (cmt) a/d converter (adc) d/a converter (dac) 16-bit timer pulse unit (tpu) realtime clock (rtc) clock pulse generator (cpg) timer unit (tmu) direct memory access controller (dmac) peripheral bus controller cache memory (32 kbytes) cache access controller (ccn) memory management unit (mmu) ssl accelerator (ssl) i 2 c figure 1.1 block diagram 1.3 pin assignments 1.3.1 pin assignments section 1 overview rev. 3.00 jan. 18, 2008 page 11 of 1458 rej09b0033-0300 usb1d_dmns/ pint11/ afe_rlycnt/ pcc_bvd2/ptg3 usb1d_speed/ pint9/ pcc_cd2 / ptg1 mmc_vddon/ scif1_cts / lcd_vepwc/ tpu_to3/ptv4 usb1d_txdpls/ afe_sclk/ iois16 / pcc_iois16 / ptg4 we2 / dqmul/ iciord we3 / dqmuu/ iciowr lcd_data13/ pint13/ptd5 we1 / dqmlu/ we lcd_data14/ pint14/ptd6 lcd_data15/ pint15/ptd7 lcd_data12/ pint12/ptd4 lcd_data10/ ptd2 lcd_data11/ ptd3 lcd_data5/ ptc5 lcd_data9/ ptd1 lcd_data8/ ptd0 lcd_data7/ ptc7 lcd_data1/ ptc1 lcd_data6/ ptc6 lcd_data4/ ptc4 lcd_data3/ ptc3 lcd_data2/ ptc2 lcd_data0/ ptc0 cs6b / ce1b /ptm0 cs5b / ce1a / ptm1 lcd_m_disp/ pte4 siof0_sync/ pts4 siof0_mclk/ pts3 siof0_txd/ pts2 lcd_don/ pte1 lcd_cl1/ pte3 lcd_flm/ pte0 wait / pcc_wait usb1_pwr_en/ usbf_uplup/ pth0 dreq0 / pint0/ptm6 dack0 / pint1/ptm4 usb1d_suspend/ refout / irqout /ptp4 usb1d_rcv/ irq5/afe_fs/ pcc_reg / ptg6 afe_rdet / iic_sda/ pte5 mmc_odmod / scif1_rts / lcd_vcpwc/ tpu_to2/ptv3 scif0_cts / tpu_to1/ ptt4 tend0/ pint2/ptm2 tend1/ pint3/ptm3 usb1_ovr_current / usbf_vbus usb1d_txse0/ irq4/ afe_txout/ pcc_drv / ptg5 usb1d_dpls/ pint10/ afe_hc1/ pcc_bvd1/ptg2 afe_rxin/ iic_scl/ pte6 pint7/ pcc_reset/ ptk3 pint6/ pcc_rdy/ ptk2 pint5/ pcc_vs2 / ptk1 pint4/ pcc_vs1 / ptk0 usb1d_txenl/ pint8/ pcc_cd1 /ptg0 scif0_rts / tpu_to0/ ptt3 asebrkak / ptj5 sh7330 plbg0256ga-a (bp-256h/hv) (top view) index 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y vssq vcc_pll2 vcc_pll1 vssq1 vccq1 d24/ptb0 vssq1 vccq1 vssq1 vccq1 ckio cas /pth5 ras /pth6 vssq1 vccq1 a16 vssq1 vccq1 a8 vssq1 resetm extal status0/ pth2 d30/ptb6 d27/ptb3 vcc vss d19/pta3 d16/pta0 rd/ wr cke/pth4 vcc vss a15 a12 a10 d12 a0/ptr0 vssq1 d11 d14 d15 vccq1 d8 d9 d10 d5 d4 d6 d7 vssq1 d1 d2 d3 vccq1 back breq cs4 vssq1 bs a18 a21/ptr3 a20/ptr2 a19/ptr1 rd a25/ptr7 a23/ptr5 a22/ptr4 vssq1 vccq_rtc extal_rtc vssq1 a24/ptr6 vccq1 cs0 vssq1 vcc cs5a / ce2a vss d0 cs6a / ce2b vccq md2 md1 vssq vccq vssq vccq vss lcd_clk vssq usb2_pwr_en/ pth1 siof0_sck/ pts0 siof0_rxd/ pts1 vccq da1/ptf6 adtrg /ptf0 usb2_ovr_current avss usb2_m usb2_p an0/ptf1 usb1_p avcc_usb usb1_m avss_usb avcc_usb xtal_usb avcc vssq vccq extal_usb vssq vccq vss vcc scif0_txd/ irtx/ptt2 irq1/ irl1 / ptp1 vss scif0_rxd/ irrx/ptt1 vcc audsync / ptj0 vssq irq2/ irl2 / ptp2 audata3/ ptj4 vccq vssq vccq tms/ptl6 dreq1 /ptm7 xtal_rtc vccq1 nmi au data 2 / ptj3 irq3/ irl3 / ptp3 au data 0 / ptj1 asemd0 irq0/ irl0 / ptp0 audata1/ ptj2 scif0_sck/ ptt0 audck/ptj6 trst /ptl7 tck/ptl3 tdi/ptl4 resetp dack1 /ptm5 ca vss_rtc tdo/ptl5 vssq vcc_rtc vccq an1/ptf2 an2/ptf3 an3/ptf4 da0/ptf5 vcc lcd_cl2/ pte2 md4 md3 md0 vss_pll2 d29/ptb5 d26/ptb2 d23/pta7 d20/pta4 d17/pta1 status1/ pth3 xtal md5 d31/ptb7 vss_pll1 d28/ptb4 d25/ptb1 d22/pta6 d21/pta5 d18/pta2 we0 /dqmll cs3 a14 a11 a6 a9 a3 a2 vccq1 cs2 a17 a13 a5 a4 a7 a1 d13 mmc_cmd/ siof1_rxd/ sd_cmd/ tpu_ti2b/ptu1 sim_rst/ sd_wp/ scif1_rxd/ptv1 siof1_mclk/ sd_dat1/ tpu_ti3b/ptu3 sim_d/ scif1_txd/ sd_cd/ptv2 siof1_sync/ sd_dat2/ ptu4 mmc_clk/ siof1_sck/ sd_clk/ tpu_ti2a/ptu0 sim_clk/ scif1_sck/ sd_dat3/ptv0 mmc_dat/ siof1_txd/ sd_dat0/ tpu_ti3a/ptu2 figure 1.2 pin assignments (plbg0256ga-a (bp-256h/hv)) section 1 overview rev. 3.00 jan. 18, 2008 page 12 of 1458 rej09b0033-0300 extal l c d _ data 1 5 / pint15/ptd7 we3 / dqmuu/ iciowr cs6b / ce1b / ptm0 cs5b / ce1a / ptm1 lcd_data14/ pint14/ptd6 lcd_data10/ ptd2 lcd_data12/ pint12/ptd4 lcd_data13/ pint13/ptd5 lcd_data7/ ptc7 lcd_data4/ ptc4 lcd_data6/ ptc6 lcd_data3/ ptc3 lcd_data1/ ptc1 lcd_data0/ ptc0 lcd_data2/ ptc2 lcd_m_disp/ pte4 usb1_pwr_en/ usbf_uplup pth0 siof0_sync/ pts4 siof0_txd/ pts2 siof0_sck/ pts0 usb2_ovr_current usb2_pwr_en/ pth1 dack0 / pint1/ ptm4 tend1/pint3/ ptm3 mmc_vddon/ scif1_cts / lcd_vepwc/ tpu_to3/ptv4 usb1d_dmns/ pint11/ afe_rlycnt/ pcc_bvd2/ptg3 dreq0 / pint0/ ptm6 asebrkak / ptj5 usb1d_speed/ pint9/ pcc_cd2 /ptg1 mmc_odmod / scif1_rts / lcd_vcpwc/ tpu_to2/ptv3 scif0_cts / tpu_to1/ ptt4 usb1_ovr_current / usbf_vbus afe_rdet / iic_sda/ pte5 usb1d_suspend/ refout / irqout / ptp4 usb1d_txse0/ irq4/afe_txout/ pcc_drv /ptg5 scif0_rxd/ irrx/ptt1 pint7/ pcc_reset/ ptk3 pint6/ pcc_rdy/ ptk2 pint4/ pcc_vs1 / ptk0 pint5/ pcc_vs2 / ptk1 usb1d_txenl/ pint8/ pcc_cd1 / /ptg0 usb1d_rcv/ irq5/afe_fs/ pcc_reg / ptg6 scif0_txd/ irtx/ptt2 irq3/ irl3 / ptp3 usb1d_dpls/ pint10/afe_hc1/ pcc_bvd1/ptg2 afe_rxin/ iic_scl/ pte6 scif0_rts / tpu_to0/ ptt3 scif0_sck/ ptt0 tend0/pint2/ ptm2 siof0_mclk/ pts3 lcd_data8/ ptd0 lcd_data9/ ptd1 lcd_data5/ ptc5 l c d _ data 1 1 / ptd3 we2 / dqmul/ iciord index 20 21 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa sh7330 plbg0256ka-a (bp-256c/cv) (top view) usb1d_txdpls/ afe_sclk/ iois16 / pcc_iois16 /ptg4 md1 md2 md0 vss_pll2 vssq1 vccq1 d23/pta7 vccq1 vssq1 vccq1 we0 / dqmll cs3 a15 a12 vccq1 a6 a4 vssq1 a1 ras /pth6 vssq xtal d31/ptb7 vcc_pll1 d29/ptb5 d26/ptb2 d24/ptb0 vssq1 d20/pta4 d17/pta1 cas /pth5 vssq1 a17 a13 a11 a8 a5 a14 a3 a2 md4 md3 d28/ptb4 vcc_pll2 vss_pll1 d30/ptb6 d27/ptb3 vcc d21/pta5 d16/pta0 cke/pth4 vcc vccq1 vssq1 a9 a7 vccq1 d14 a0/ptr0 resetm md5 vccq vccq lcd_cl2/ pte2 lcd_flm/ pte0 d25/ptb1 d22/pta6 vss d19/pta3 d18/pta2 ckio rd/ wr we1 / dqmlu/ we cs2 vss a16 d15 vccq1 d11 d15 status0/ pth2 s tat u s 1 / pth3 vssq vssq vss vssq avss an0/ptf1 an1/ptf2 usb2_p vccq vccq vssq extal_usb vccq da0/ptf5 vccq lcd_clk vcc da1/ptf6 usb2_m avss_usb avcc_usb adtrg / ptf0 vss vssq irq2/ irl2 / ptp2 au data 3 / ptj4 vssq an2/ptf3 usb1_p an3/ptf4 avcc_usb usb1_m vssq avcc siof0_rxd/ pts1 lcd_don/ pte1 lcd_cl1/ pte3 vssq1 d13 d8 d12 vcc vccq1 vccq1 back d10 d6 d9 cs6a / ce2b d7 d2 d4 xtal_rtc cs5a / ce2a d3 d0 d1 vss cs0 vssq1 bs breq rd cs4 a20/ptr2 a23/ptr5 resetp vccq1 a21/ptr3 ca dack1 / ptm5 a22/ptr4 a24/ptr6 vccq tck/ptl3 vccq audck/ ptj6 trst /ptl7 tdi/ptl4 asemd0 vcc vss irq1/ irl1 / ptp1 irq0/ irl0 / ptp0 vccq vcc xtal_usb audata1/ ptj2 a25/ptr7 vssq1 vccq1 wait / pcc_wait a19/ptr1 vssq1 a18 extal_rtc vccq_rtc vcc_rtc vss_rtc vssq1 a10 nmi audata2/ ptj3 audata0/ ptj1 audsync / ptj0 tms/ptl6 vssq tdo/ptl5 dreq1 / ptm7 mmc_cmd/ siof1_rxd/ sd_cmd/ tpu_ti2b/ptu1 sim_rst/ sd_wp/ scif1_rxd/ptv1 siof1_mclk/ sd_dat1/ tpu_ti3b/ptu3 sim_d/ scif1_txd/ sd_cd/ptv2 siof1_sync/ sd_dat2/ ptu4 mmc_clk/ siof1_sck/ sd_clk/ tpu_ti2a/ptu0 sim_clk/ scif1_sck/ sd_dat3/ ptv0 mmc_dat/ siof1_txd/ sd_dat0/ tpu_ti3a/ptu2 figure 1.3 pin assignments (plbg0256ka-a (bp-256c/cv)) section 1 overview rev. 3.00 jan. 18, 2008 page 13 of 1458 rej09b0033-0300 table 1.4 list of pin assignments pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply a1 a2 vssq i/o power supply (0v) ? a2 d5 vccq i/o power supply (3.3 v) ? a3 d6 status1/pth3 st atus output/general-purpose port o/io vccq a4 d7 lcd_data13/pint13/ ptd5 lcd data/port interrupt/ general-purpose port o/i/io vccq a5 e6 vssq i/o power supply (0v) ? a6 d8 vccq i/o power supply (3.3 v) ? a7 e8 lcd_data5/ptc5 lcd dat a/general-purpose port o/io vccq a8 e9 lcd_data1/ptc1 lcd dat a/general-purpose port o/io vccq a9 d10 lcd_cl2/pte2 lcd shift clock 2/general-purpose port o/io vccq a10 a11 vssq i/o power supply (0v) ? a11 e12 vccq i/o power supply (3.3 v) ? a12 e13 lcd_clk lcd clock source i vccq a13 d12 vssq i/o power supply (0v) ? a14 e15 vccq i/o power supply (3.3 v) ? a15 d13 usb1_pwr_en/ usbf_uplup/pth0 usb1 power-enable/pull-up control/general-purpose port o/o/io vccq a16 a15 avss analog power supply (0v) ? a17 a16 an0/ptf1 adc analog input/general-purpose port i/i avcc a18 b18 avcc_usb usb power supply (3.3 v) ? a19 d17 avss_usb usb power supply (0 v) ? a20 b21 vssq i/o power supply (0v) ? b1 e4 vcc_pll2 pll2 power supply (1.5 v) ? b2 b1 md2 clock mode setting i vccq b3 b2 xtal crystal o vccq b4 a5 resetm manual reset i vccq b5 a4 md4 bus width setting i vccq section 1 overview rev. 3.00 jan. 18, 2008 page 14 of 1458 rej09b0033-0300 pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply b6 c1 lcd_data15/pint15/ ptd7 lcd data/port interrupt/ general-purpose port o/i/io vccq b7 b3 lcd_data11/ptd3 lcd dat a/general-purpose port o/io vccq b8 e7 lcd_data7/ptc7 lcd dat a/general-purpose port o/io vccq b9 d9 lcd_data3/ptc3 lcd dat a/general-purpose port o/io vccq b10 e10 lcd_flm/pte0 lcd line marker/general-purpose port o/io vccq b11 d11 lcd_m_disp/pte4 lcd current-alternating signal/ general-purpose port o/io vccq b12 e14 siof0_mclk/pts3 s iof master clock/general- purpose port i/io vccq b13 e16 usb2_pwr_en/pth1 usb2 power-enable/ general-purpose port o/io vccq b14 b16 da1/ptf6 dac analog output/general- purpose port o/i vccq b15 b17 an2/ptf3 adc analog input/general-purpose port i/i avcc b16 a17 usb2_m usb d ? port 2 io avcc_ usb b17 a18 usb1_p usb d + port 1 io avcc_ usb b18 a21 usb1_m usb d ? port 1 io avcc_ usb b19 a20 avcc_usb usb power supply (3.3 v) ? b20 e20 vccq i/o power supply (3.3 v) ? c1 d2 vcc_pll1 pll1 power supply (1.5 v) ? c2 a1 md1 clock mode setting i vccq c3 b5 md5 endian setting i vccq c4 a3 extal external clock i vccq c5 b4 md3 bus width setting i vccq c6 b7 lcd_data12/pint12/ ptd4 lcd data/port interrupt/ general-purpose port o/i/io vccq c7 b8 lcd_data9/ptd1 lcd dat a/general-purpose port o/io vccq section 1 overview rev. 3.00 jan. 18, 2008 page 15 of 1458 rej09b0033-0300 pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply c8 b9 lcd_data6/ptc6 lcd dat a/general-purpose port o/io vccq c9 b10 lcd_data2/ptc2 lcd dat a/general-purpose port o/io vccq c10 b11 lcd_don/pte1 lcd display on signal/ general-purpose port o/io vccq c11 a12 siof0_sync/pts4 siof frame sync/general-purpose port io/io vccq c12 a13 siof0_txd/pts2 siof transmit data/general- purpose port o/io vccq c13 a14 siof0_sck/pts0 siof serial clock/general-purpose port io/io vccq c14 e17 adtrg /ptf0 adc external trigger/general- purpose port i/i vccq c15 d18 an3/ptf4 adc analog input/general-purpose port i/i avcc c16 d16 usb2_p usb d + port 2 io avcc_ usb c17 b19 avcc analog power supply (3.3 v) ? c18 e18 usb1d_txdpls/ afe_sclk/ iois16 / pcc_iois16 /ptg4 d + transmit output/afe shift clock/16-bit io/pcci 6-bit io/general-purpose port o/i/i/i/ io vccq c19 b20 usb1_ovr_current / usbf_vbus usb1 overcurrent/monitor i/i vccq c20 e21 extal_usb usb external clock i vccq d1 f1 vssq1 i/o power supply (0 v) ? d2 d1 md0 clock mode setting i vccq d3 c2 d31/ptb7 data bus/g eneral-purpose port io/io vccq1 d4 b6 status0/pth2 st atus output/general-purpose port o/io vccq d5 a6 lcd_data14/pint14/ ptd6 lcd data/port interrupt/ general-purpose port o/i/io vccq d6 a7 lcd_data10/ptd2 lcd dat a/general-purpose port o/io vccq d7 a8 lcd_data8/ptd0 lcd dat a/general-purpose port o/io vccq d8 a9 lcd_data4/ptc4 lcd dat a/general-purpose port o/io vccq section 1 overview rev. 3.00 jan. 18, 2008 page 16 of 1458 rej09b0033-0300 pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply d9 a10 lcd_data0/ptc0 lcd dat a/general-purpose port o/io vccq d10 e11 lcd_cl1/pte3 lcd shift clock 1/general-purpose port o/io vccq d11 b12 vss internal power supply (0 v) ? d12 b13 vcc internal power supply (1.5 v) ? d13 b14 siof0_rxd/pts1 siof receive data/general- purpose port i/io vccq d14 b15 usb2_ovr_current usb2 port overcurrent i vccq d15 d14 da0/ptf5 dac analog output/general- purpose port o/i vccq d16 d15 an1/ptf2 adc analog input/general-purpose port i/i avcc d17 a19 usb1d_dmns/pint11/ afe_rlycnt/ pcc_bvd2/ptg3 d- signal input/port interrupt/ afe on-hook control/pcc buttery detection 2/general-purpose port i/i/o/i/ io vccq d18 c21 usb1d_suspend/ refout / irqout / ptp4 suspend state/bus request (refresh)/ bus request (interrupt)/ general-purpose port o/o/o/ io vccq d19 f18 xtal_usb usb crystal o vccq d20 f21 usb1d_txenl/pint8/ pcc_cd1 /ptg0 driver output enable/port interrupt/ pcc card detection 1/ general-purpose port o/i/i/io vccq e1 g1 vccq1 i/o power supply (1.8/3.3 v) ? e2 e1 vss_pll2 pll2 power supply (0 v) ? e3 f4 vss_pll1 pll1 power supply (0 v) ? e4 g4 d30/ptb6 data bus/g eneral-purpose port io/io vccq1 e17 g18 usb1d_speed/pint9/ pcc_cd2 /ptg1 speed control/port interrupt/ pcc card detection 2/ general-purpose port o/i/i/io vccq e18 d20 usb1d_rcv/irq5/ afe_fs/ pcc_reg / ptg6 receive data/interrupt/ area indicate signal/ afe frame synchronization/ pcc space indication/ general-purpose port i/i/i/o/ io vccq section 1 overview rev. 3.00 jan. 18, 2008 page 17 of 1458 rej09b0033-0300 pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply e19 d21 usb1d_txse0/irq4/ afe_txout/ pcc_drv /ptg5 se0 state/interrupt/ afe serial transmission/ pcc buffer control/ general-purpose port o/i/o/ o/io vccq e20 g21 vssq i/o power supply (0v) ? f1 g2 d24/ptb0 data bus/g eneral-purpose port io/io vccq1 f2 e2 d29/ptb5 data bus/g eneral-purpose port io/io vccq1 f3 d4 d28/ptb4 data bus/g eneral-purpose port io/io vccq1 f4 h4 d27/ptb3 data bus/g eneral-purpose port io/io vccq1 f17 f17 mmc_vddon/ scif1_cts / lcd_vepwc/ tpu_to3/ptv4 mmc card power supply control/ scif transmit enable/lcd power supply control/ tpu compare- match output/general-purpose port o/i/o/ o/io vccq f18 c20 afe_rdet /iic_sda/ pte5 afe ringing/iic data i/o /general-purpose port i/io/i vccq f19 f20 usb1d_dpls/pint10/ afe_hc1/pcc_bvd1/ ptg2 d + transmit input/port interrupt/ afe hardware control/ pcc battery detection 1/ general-purpose port i/i/o/i/ io vccq f20 h20 vccq i/o power supply (3.3 v) ? g1 h2 vssq1 i/o power supply (0v) ? g2 f2 d26/ptb2 data bus/g eneral-purpose port io/io vccq1 g3 e5 d25/ptb1 data bus/g eneral-purpose port io/io vccq1 g4 j4 vcc internal power supply (1.5 v) ? g17 g17 vss internal power supply (0 v) ? g18 h18 mmc_odmod / scif1_rts / lcd_vcpwc/tpu_to2/ ptv3 mmc open drain control/ scif transmit request/lcd power supply control/tpu compare- match output/general-purpose port o/o/o/ o/io vccq g19 g20 afe_rxin/iic_scl/ pte6 afe serial receive/ iic clock/general-purpose port i/io/i vccq g20 j20 sim_clk/ scif1_sck/ sd_dat3/ptv0 sim clock/scif serial clock/ sd data/general-purpose port o/io/ io/io vccq section 1 overview rev. 3.00 jan. 18, 2008 page 18 of 1458 rej09b0033-0300 pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply h1 j1 vccq1 i/o power supply (1.8/3.3 v) ? h2 h1 d23/pta7 data bus/g eneral-purpose port io/io vccq1 h3 f5 d22/pta6 data bus/g eneral-purpose port io/io vccq1 h4 g5 vss power-supply (0 v) ? h17 j18 vcc power-supply (1.5 v) ? h18 h17 sim_rst/scif1_rxd/ sd_wp/ptv1 sim reset/scif receive data/ sd write protect/ general-purpose port o/i/i/io vccq h19 h21 sim_d/scif1_txd/ sd_cd/ptv2 sim data/scif transmit data/ sd card detection/ general-purpose port io/o/i/ io vccq h20 k20 mmc_dat/siof1_txd/ sd_dat0/tpu_ti3a/ ptu2 mmc data/siof transmit data/ sd data/tpu clock input/ general-purpose port io/o/ io/i/io vccq j1 k1 vssq1 i/o power supply (0v) ? j2 j2 d20/pta4 data bus/g eneral-purpose port io/io vccq1 j3 k4 d21/pta5 data bus/g eneral-purpose port io/io vccq1 j4 h5 d19/pta3 data bus/g eneral-purpose port io/io vccq1 j17 k17 mmc_cmd/ siof1_rxd/sd_cmd/ tpu_ti2b/ptu1 mmc command/siof receive data/sd command/tpu clock input/general-purpose port io/i/io/ i/io vccq j18 j17 siof1_mclk/sd_dat1/ tpu_ti3b/ptu3 siof master clock/sd data/ tpu clock input/general-purpose port i/io/i/io vccq j19 j21 siof1_sync/sd_dat2/ ptu4 siof frame sync/ sd data/general-purpose port io/io/io vccq j20 l17 scif0_rts /tpu_to0/ ptt3 scif transmit request/tpu compare-match output/ general-purpose port o/o/io vccq k1 l1 vccq1 i/o power supply (1.8/3.3 v) ? k2 k2 d17/pta1 data bus/g eneral-purpose port io/io vccq1 section 1 overview rev. 3.00 jan. 18, 2008 page 19 of 1458 rej09b0033-0300 pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply k3 j5 d18/pta2 data bus/g eneral-purpose port io/io vccq1 k4 l4 d16/pta0 data bus/ge neral-purpose port io/io vccq1 k17 l20 scif0_txd/irtx/ptt2 scif transmit data/ irda transmit data/general-purpose port o/o/io vccq k18 k18 scif0_cts /tpu_to1/ ptt4 scif transmit enable/tpu compare-match output/ general-purpose port i/o/io vccq k19 k21 mmc_clk/siof1_sck/ sd_clk/tpu_ti2a/ ptu0 mmc clock/siof serial clock/ sd clock/tpu clock input/general- purpose port o/io/o/ i/io vccq k20 m17 vssq i/o power supply (0v) ? l1 k5 ckio system clock io vccq1 l2 m1 we2 /dqmul/ iciord second-highest-byte write/ dq mask ul/io read o/o/o vccq1 l3 m4 we3 /dqmuu/ iciowr highest-byte write/ dq mask uu/io write o/o/o vccq1 l4 l5 rd/ wr read/write signal o vccq1 l17 l21 scif0_rxd/irrx/ptt1 scif receive data/irda receive data/general-purpose port i/i/io vccq l18 m20 irq3/ irl3 /ptp3 interrupt/interrupt/general-purpose port i/i/io vccq l19 n17 scif0_sck/ptt0 scif serial clock/general-purpose port io/io vccq l20 l18 vccq i/o power supply (3.3 v) ? m1 l2 cas /pth5 column address/general-purpose port o/io vccq1 m2 n1 we0 /dqmll lowest-byte writ e/dq mask ll o/o vccq1 m3 n5 we1 /dqmlu/ we second-lowest-byte write/ dq mask lu/write enable o/o/o vccq1 m4 m5 cke/pth4 clock enable /general-purpose port o/io vccq1 m17 m21 irq1/ irl1 /ptp1 interrupt/interrupt/ general-purpose port i/i/io vccq m18 n20 nmi nmi interrupt i vccq section 1 overview rev. 3.00 jan. 18, 2008 page 20 of 1458 rej09b0033-0300 pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply m19 m18 irq0/ irl0 /ptp0 interrupt/interrupt/ general-purpose port i/i/io vccq m20 p17 irq2/ irl2 /ptp2 interrupt/interrupt/ general-purpose port i/i/io vccq n1 m2 ras /pth6 row address/gener al-purpose port o/io vccq1 n2 p1 cs3 chip select o vccq1 n3 p5 cs2 chip select o vccq1 n4 n4 vcc power-supply (1.5 v) ? n17 n21 vss power-supply (0 v) ? n18 p20 audata2/ptj3 aud data/ general-purpose port o/io vccq n19 n18 audata1/ptj2 aud data/ general-purpose port o/io vccq n20 r17 audata3/ptj4 aud data/ general-purpose port o/io vccq p1 n2 vssq1 i/o power supply (0v) ? p2 w2 a14 address bus o vccq1 p3 p2 a17 address bus o vccq1 p4 r5 vss internal power supply (0 v) ? p17 p21 vcc internal power supply (1.5 v) ? ? p18 r20 audata0/ptj1 aud data/ general-purpose port o/io vccq p19 p18 audck/ptj6 aud clock/general-purpose port o/io vccq p20 t17 vssq i/o power supply (0v) ? r1 p4 vccq1 i/o power supply (1.8/3.3 v) ? r2 t2 a11 address bus o vccq1 r3 r2 a13 address bus o vccq1 r4 r1 a15 address bus o vccq1 r17 t20 audsync /ptj0 aud synchronous signal/ general-purpose port o/io vccq r18 r21 asemd0 ase mode i vccq r19 r18 trst /ptl7 test reset/general -purpose port i/io vccq r20 u17 vccq i/o power supply (3.3 v) ? t1 t5 a16 address bus o vccq1 section 1 overview rev. 3.00 jan. 18, 2008 page 21 of 1458 rej09b0033-0300 pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply t2 v1 a6 address bus o vccq1 t3 v2 a5 address bus o vccq1 t4 t1 a12 address bus o vccq1 t17 u20 tms/ptl6 test m ode select/general-purpose port i/io vccq t18 t18 tck/ptl3 test clock/gen eral-purpose port i/io vccq t19 u21 pint7/pcc_reset/ ptk3 port interrupt/p cc reset/general- purpose port i/o/io vccq t20 v18 asebrkak /ptj5 ase break mo de acknowledge/ general-purpose port o/io vccq u1 r4 vssq1 i/o power supply (0 v) ? u2 t4 a9 address bus o vccq1 u3 w1 a4 address bus o vccq1 u4 aa3 a10 address bus o vccq1 u5 y5 d11 data bus io vccq1 u6 y6 d8 data bus io vccq1 u7 aa8 d4 data bus io vccq1 u8 aa9 d1 data bus io vccq1 u9 aa10 vcc internal power supply (1.5 v) ? u10 v11 vss internal power supply (0 v) ? u11 u11 back bus request acknowledge o vccq1 u12 u12 bs bus start o vccq1 u13 v13 a19/ptr1 address bu s/general-purpose port o/io vccq1 u14 u15 a22/ptr4 address bu s/general-purpose port o/io vccq1 u15 u16 a24/ptr6 address bu s/general-purpose port o/io vccq1 u16 v15 dack0 /pint1/ptm4 dma transfer request reception/ port interrupt/ general-purpose port o/i/io vccq1 u17 w21 dreq1 /ptm7 dma transfer request/ general-purpose port i/io vccq1 u18 t21 tdi/ptl4 test data input/general-purpose port i/io vccq section 1 overview rev. 3.00 jan. 18, 2008 page 22 of 1458 rej09b0033-0300 pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply u19 v21 pint6/pcc_rdy/ptk2 po rt interrupt/pcc ready/general- purpose port i/i/io vccq u20 w20 tdo/ptl5 test data output/general-purpose port o/io vccq v1 u1 vccq1 i/o power supply (1.8/3.3 v) ? v2 y2 a3 address bus o vccq1 v3 u4 a7 address bus o vccq1 v4 aa6 d12 data bus io vccq1 v5 y4 d14 data bus io vccq1 v6 aa7 d9 data bus io vccq1 v7 y7 d6 data bus io vccq1 v8 y8 d2 data bus io vccq1 v9 y9 d0 data bus io vccq1 v10 y10 cs5b / ce1a /ptm1 chip select/chip select/ general-purpose port o/o/io vccq1 v11 v12 breq bus request i vccq1 v12 u13 wait / pcc_wait wait/pcc wait i/i vccq1 v13 u14 a20/ptr2 address bu s/general-purpose port o/io vccq1 v14 v14 a23/ptr5 address bu s/general-purpose port o/io vccq1 v15 y19 dreq0 /pint0/ptm6 dma transfer request/ port interrupt/general-purpose port i/i/io vccq1 v16 y18 extal_rtc rtc external clock i vccq_ rtc v17 aa19 xtal_rtc rtc crystal o vccq_ rtc v18 v17 resetp power-on reset i vccq_ rtc v19 aa21 pint5/ pcc_vs2 /ptk1 port interrupt/ pcc voltage detection 2/ general-purpose port i/i/io vccq v20 v20 vssq i/o power supply (0 v) ? section 1 overview rev. 3.00 jan. 18, 2008 page 23 of 1458 rej09b0033-0300 pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply w1 u2 a8 address bus o vccq1 w2 aa2 a2 address bus o vccq1 w3 aa1 a1 address bus o vccq1 w4 aa4 a0/ptr0 address bus/general-purpose port o/io vccq1 w5 aa5 d15 data bus io vccq1 w6 v7 d10 data bus io vccq1 w7 v8 d7 data bus io vccq1 w8 v9 d3 data bus io vccq1 w9 v10 cs6b / ce1b /ptm0 chip select/chip select/general- purpose port o/o/io vccq1 w10 u9 cs5a / ce2a chip select/chip select o/o vccq1 w11 aa12 cs4 chip select o vccq1 w12 aa13 a18 address bus o vccq1 w13 aa14 a21/ptr3 address bu s/general-purpose port o/io vccq1 w14 y15 a25/ptr7 address bu s/general-purpose port o/io vccq1 w15 y16 tend0/pint2/ptm2 dma transfer end/port interrupt/ general-purpose port o/i/io vccq1 w16 aa18 vccq_rtc rtc power supply (3.3 v) ? w17 v16 tend1/pint3/ptm3 dma transfer end/port interrupt/ general-purpose port o/i/io vccq1 w18 y20 vss_rtc rtc power supply (0 v) ? w19 y21 pint4/ pcc_vs1 /ptk0 port interrupt/pcc voltage detection 1/general-purpose port i/i/io vccq w20 u18 vccq i/o power supply (3.3 v) ? y1 y1 vssq1 i/o power supply (0 v) ? y2 v5 vccq1 i/o power supply (1.8/3.3 v) ? y3 v6 d13 data bus io vccq1 y4 y3 vssq1 i/o power supply (0 v) ? y5 v4 vccq1 i/o power supply (1.8/3.3 v) ? y6 u5 d5 data bus io vccq1 section 1 overview rev. 3.00 jan. 18, 2008 page 24 of 1458 rej09b0033-0300 pin no. (plbg 0256 ga-a) pin no. (plbg 0256 ka-a) pin name function i/o i/o buffer power supply y7 u6 vssq1 i/o power supply (0 v) ? y8 u7 vccq1 i/o power supply (1.8/3.3 v) ? y9 u8 cs6a / ce2b chip select/chip select o/o vccq1 y10 aa11 vssq1 i/o power supply (0 v) ? y11 u10 vccq1 i/o power supply (1.8/3.3 v) ? y12 y11 cs0 chip select o vccq1 y13 y12 rd read strobe o vccq1 y14 y13 vssq1 i/o power supply (0 v) vccq1 y15 y14 vccq1 i/o power supply (1.8/3.3 v) ? y16 aa15 vssq1 i/o power supply (0 v) ? y17 aa16 vccq1 i/o power supply (1.8/3.3 v) ? y18 aa17 dack1 /ptm5 dma transfer request reception/ general-purpose port o/io vccq1 y19 y17 ca chip active i vccq_ rtc y20 aa20 vcc_rtc rtc power supply (1.5 v) ? section 1 overview rev. 3.00 jan. 18, 2008 page 25 of 1458 rej09b0033-0300 1.3.2 pin functions table 1.5 lists the pin functions. table 1.5 sh7720/SH7721 pin functions classification symbol i/o name function vcc power supply power supply for the internal modules and ports for the system. connect all vcc pins to the system power supply. there will be no operation if any pins are open. vss ground ground pin. connect all vss pins to the system power supply (0 v). there will be no operation if any pins are open. vccq power supply power supply for i/o pins. connect all vccq pins to the system power supply. there will be no operation if any pins are open. vssq ground ground pin. connect all vssq pins to the system power supply (0 v). there will be no operation if any pins are open. vccq1 power supply input/output power supply (1.8/3.3 v) pin. power supply vssq1 ground input/output power supply (0 v) pin. vcc_pll1 pll1 power supply power supply for the on-chip pll1 oscillator. (1.5 v) vss_pll1 pll1 ground ground pin for the on-chip pll1 oscillator. vcc_pll2 pll2 power supply power supply for the on-chip pll2 oscillator. (1.5 v) vss_pll2 pll2 ground ground pin for the on-chip pll2 oscillator. clock extal i external clock for connection to a crystal resonator. an exte rnal clock signal may also be input. section 1 overview rev. 3.00 jan. 18, 2008 page 26 of 1458 rej09b0033-0300 classification symbol i/o name function xtal o crystal for connection to a crystal resonator. clock ckio i/o system clock used as a pin to input external clock or output clock. operating mode control md5 to md0 i mode set sets the operating mode. do not change values on these pins during operation. md2 to md0 set the clock mode, md3 and md4 set the bus width of area 0 and md5 sets the endian. resetp i power-on reset when lo w, the system enters the power-on reset state. resetm i manual reset when low, the system enters the manual reset state. status1, status0 o status output indicate s the operating state. breq i bus request low when an external device requests the release of the bus mastership. back o bus request acknowledge indicates that the bus mastership has been released to an external device. reception of the back signal informs the device which has output the breq signal that it has acquired the bus. system control ca i chip active high in normal operation, and low in hardware standby mode. nmi i non-maskable interrupt non-maskable interrupt request pin. fix to high level when not in use. irq5 to irq0 i interrupt requests 5 to 0 maskable interrupt request pins. selectable as level input or edge input. the rising edge or falling edge is selectable as the detection edge. the low level or high level is selectable as the detection level. interrupts irl3 to irl0 i interrupt requests 3 to 0 maskable interrupt request pin. input a coded interrupt level. section 1 overview rev. 3.00 jan. 18, 2008 page 27 of 1458 rej09b0033-0300 classification symbol i/o name function pint15 to pint0 i port interrupt requests 15 to 0 port interrupt request pins refout o bus request bus request signal for refreshing interrupts irqout o bus request bus request signal for interrupt address bus a25 to a0 o address bus outputs addresses. data bus d31 to d0 i/o data bus 32-bit bidirectional data bus cs4 to cs2 , cs0 cs6a , cs6b , cs5a , cs5b , ce2a , ce2b , ce1a , ce1b o chip select chip-select signal for external memory or devices. rd o read strobe indicates reading of data from external devices. rd/ wr o read/write signal read/write signal bs o bus start bus-cycle start signal pin back o bus request acknowledge indicates that the bus mastership has been released to an external device. breq i bus request low when an external device requests the release of the bus mastership. we o write enable write enable pin for pcmcia we3 ( be3 ) o highest-byte write indicates that bits 31 to 24 of the data in the external memory or device are being written. we2 ( be2 ) o second-highest- byte write indicates that bits 23 to 16 of the data in the external memory or device are being written. we1 ( be1 ) o second-lowest- byte write indicates that bits 15 to 8 of the data in the external memory or device are being written. we0 ( be0 ) o lowest-byte write indicates that bits 7 to 0 of the data in the external memory or device are being written. bus control cke o clock enable clock enable (sdram) section 1 overview rev. 3.00 jan. 18, 2008 page 28 of 1458 rej09b0033-0300 classification symbol i/o name function cas o column address connect to the cas pin when the sdram is connected. dqmuu o dq mask uu selects d31 to d24. (sdram) dqmul o dq mask ul selects d23 to d16. (sdram) dqmlu o dq mask lu selects d15 to d8. (sdram) dqmll o dq mask ll selects d7 to d0. (sdram) ras o row address connect to the ras pin when the sdram is connected. wait i wait input inserts a wait cycle into the bus cycles during access to the external space. iois16 i 16-bit io indicates 16-bit i/o when pcmcia is in use. iciord o io read indicates i/o read when pcmcia is in use. bus control iciowr o io write indicates i/o write when pcmcia is in use. dreq0 , dreq1 i dma-transfer request input pins for external requests for dma transfer dack0 , dack1 o dma transfer request reception indicates the acceptance of dma transfer requests to external devices. direct memory access controller (dmac) tend0, tend1 o dma-transfer end transfer end output pins for dmac tpu_to3 to tpu_to0 o tpu compare- match output tpu compare-match output pins tpu_ti3a to tpu_ti2a i tpu clock input tpu clock input pins 16-bit timer pulse unit (tpu) tpu_ti2b to tpu_ti3b i tpu clock input tpu clock input pins afe_rlycnt o afe on-hook control on-hook control pin afe_fs i afe frame synchronization afe frame synchronization signal pin analog front end interface (afeif) afe_sclk i afe shift clock afe shift clock input pin section 1 overview rev. 3.00 jan. 18, 2008 page 29 of 1458 rej09b0033-0300 classification symbol i/o name function afe_txout o afe serial transmission afe serial transmit data output pin afe_rdet i afe ringing signal afe ringing signal input pin afe_hc1 o afe hardware control afe hardware control signal analog front end interface (afeif) afe_rxin i afe serial reception afe serial receive data scif0_txd, scif1_txd o scif transmit data transmit data pins scif0_rxd, scif1_rxd i scif receive data receive data pins scif0_sck, scif1_sck i/o scif serial clock clock input/output pins scif0_rts , scif1_rts o scif transmit request transmit request output pins serial communication interface with fifo (scif) scif0_cts , scif1_cts i scif transmit enable modem control pins irtx o irda transmit data irda transmit data output pin irda irrx i irda receive data irda receive data input pin siof0_sync, siof1_sync i/o siof frame sync siof frame synchronization signals siof0_txd, siof1_txd o siof transmit data siof transmit data pin siof0_rxd, siof1_rxd i siof receive data siof receive data pin siof0_sck, siof1_sck i/o siof serial clock siof serial clock pins serial i/o with fifo (siof) siof0_mclk, siof1_mclk i siof master clock siof master clock input pins iic_scl i/o iic clock i 2 c serial clock pin i 2 c bus interface (iic) iic_sda i/o iic data i 2 c data input/output pin realtime clock (rtc) vccq_rtc ? rtc power supply power supply pin for the rtc (3.3 v) section 1 overview rev. 3.00 jan. 18, 2008 page 30 of 1458 rej09b0033-0300 classification symbol i/o name function vcc_rtc ? rtc power supply power supply pin for the rtc (1.5 v) vss_rtc ? rtc ground ground pin for the rtc. extal_rtc i rtc external clock connects crystal resonator for the rtc. also used to input external clock for the rtc. realtime clock (rtc) xtal_rtc o rtc crystal connec ts crystal resonator for the rtc. lcd_data15 to lcd_data0 o lcd data data output pin for lcd panel lcd_cl1 o lcd shift clock 1 lcd shift clock 1/ horizontal sync signal pin lcd_cl2 o lcd shift clock 2 lcd shift clock 2/dot clock pin lcd_clk i lcd clock source lcd clock source input pin lcd_flm o lcd line marker first line marker/vertical sync signal pin lcd_don o lcd display on lcd display on signal pin lcd_vcpwc o lcd power control (vcc) lcd module power control (vcc) pin lcd_vepwc o lcd power control (vee) lcd module power control (vee) pin lcd controller (lcdc) lcd_m_disp o lcd current alternating signal lcd current alternating signal pin pcc_bvd1 i pcc battery detection 1 pin for buttery voltage detect 1/ card status change signal from pc card pcc_bvd2 i pcc battery detection 2 pin for buttery voltage detect 2/ digital sound signal pin from pc card pcc_rdy i pcc ready pin for ready signal/interrupt request signal form pc card pcc_reg o pcc space indication area indicate signal pin for pc card pcc_reset o pcc reset reset signal pin for pc card pc card controller (pcc) pcc_cd1 i pcc card detection 1 pin for card detect 1 signal from pc card section 1 overview rev. 3.00 jan. 18, 2008 page 31 of 1458 rej09b0033-0300 classification symbol i/o name function pcc_cd2 i pcc card detection 2 pin for card detect 2 signal from pc card pcc_wait i pcc wait request pcc hardware wait request signal pin pcc_drv o pcc buffer control pcc buffer control signal pin pcc_vs1 i pcc voltage detection 1 pin for voltage sense 1 signal from pc card pcc_vs2 i pcc voltage detection 2 pin for voltage sense 2 signal from pc card pc card controller (pcc) pcc_iois16 i pcc16-bit io pin for write protection signal/16- bit i/o signal from pc card mmc_odmod o mmc open drain control open drain mode control pin mmc_vddon o mmc card power control mmc power control pin mmc_clk o mmc clock clock output pin mmc_dat i/o mmc data data input/output pin in mmc mode response/data input pin in spi mode this pin is connected to the data out pin on the mmc side. multimedia card interface (mmcif) mmc_cmd i/o mmc command command output/response input pin in mmc mode command/data output pin in spi mode this pin is connected to the data in pin on the mmc side. sd_clk o sd clock clock output pin sd_cmd i/o sd command command output/response input pin sd_dat0 i/o sd data 0 data input/output pin sd_dat1 i/o sd data 1 data input/output pin sd_dat2 i/o sd data 2 data input/output pin sd host interface (sdhi) sd_dat3 i/o sd data 3 data input/output pin section 1 overview rev. 3.00 jan. 18, 2008 page 32 of 1458 rej09b0033-0300 classification symbol i/o name function sd_cd i sd card detection card detection pin sd host interface (sdhi) sd_wp i sd write protect write protect pin sim_rst o sim reset smart card reset output pin sim_clk o sim clock smart card clock output pin sim card module (sim) sim_d i/o sim data transmit/r eceive data input/output pin an3 to an0 i adc analog input analog input pin avcc ? analog power supply power supply pin for the a/d or d/a converter. when the a/d or d/a converter is not in use, connect this pin to input/output power supply (vccq). avss ? analog ground ground pin for the a/d or d/a converter. connect this pin to input/output power supply (vssq). a/d converter (adc) adtrg i adc external trigger external trigger signal for starting a/d conversion da0 o dac analog output channel 0 analog output pin d/a converter (dac) da1 o dac analog output channel 1 analog output pin avcc_usb ? usb power supply power supply pin for usb avss_usb ? usb ground ground pin for usb extal_usb i usb external clock connects crystal resonator for usb. also used to input external clock for usb (48 mhz) xtal_usb o usb crystal connects a crystal resonator for usb usb1_ovr_ current / usbf_vbus i usb1 over- current/ monitor usb port 1 over-current detection/ usb cable connection monitor pin usb usb2_ovr_ current i usb2 over- current usb port 2 over-current detection pin section 1 overview rev. 3.00 jan. 18, 2008 page 33 of 1458 rej09b0033-0300 classification symbol i/o name function usb1_pwr_en/ usbf_uplup o usb1 power enable/pull-up control usb port 1 power enable control/ pull- up control output pin sub2_pwer_en o usb2 power enable usb port 2 power enable control pin usb1_p i/o usb d + port 1 d + port 1 transceiver pin for usb usb1_m i/o usb d ? port 1 d ? port 1 transceiver pin for usb usb2_p i/o usb d + port 2 d + port 2 transceiver pin for usb usb2_m i/o usb d ? port 2 d ? port 2 transceiver pin for usb usb1d_dmns i d ? signal input input pin to driver for d ? signal from receiver usb1d_ suspend o suspend state transceiv er suspend state output pin usb1d_rcv i receive data input pin for receive data from differential receiver usb1d_txenl o driver output enable driver output enable pin usb1d_speed o speed control transceiver speed control pin usb1d_txse0 o se0 state se0 state output pin usb1d_ txdpls o d+ transmit output d+ transmit output pin to driver usb usb1d_dpls i d+ transmit input d+ transmit input pin to driver pta7 to pta0 i/o general purpose port 8-bit general-purpose port pins ptb7 to ptb0 i/o general purpose port 8-bit general-purpose port pins ptc7 to ptc0 i/o general purpose port 8-bit general-purpose port pins ptd7 to ptd0 i/o general purpose port 8-bit general-purpose port pins pte6, pte5 i general purpose port pte4 to pte0 i/o general purpose port 7-bit general-purpose port pins i/o port ptf6 to ptf0 i general purpose port 7-bit general-purpose port pins section 1 overview rev. 3.00 jan. 18, 2008 page 34 of 1458 rej09b0033-0300 classification symbol i/o name function ptg6 to ptg0 i/o general purpose port 7-bit general-purpose port pins pth6 to pth0 i/o general purpose port 7-bit general-purpose port pins ptj6 to ptj0 i/o general purpose port 7-bit general-purpose port pins ptk3 to ptk0 i/o general purpose port 4-bit general-purpose port pins ptl7 to ptl3 i/o general purpose port 5-bit general-purpose port pins ptm7 to ptm0 i/o general purpose port 8-bit general-purpose port pins ptp4 to ptp0 i/o general purpose port 5-bit general-purpose port pins ptr7 to ptr0 i/o general purpose port 8-bit general-purpose port pins pts4 to pts0 i/o general purpose port 5-bit general-purpose port pins ptt4 to ptt0 i/o general purpose port 5-bit general-purpose port pins ptu4 to ptu0 i/o general purpose port 5-bit general-purpose port pins i/o port ptv4 to ptv0 i/o general purpose port 5-bit general-purpose port pins tck i test clock test-clock input pin tms i test mode select test-mode select signal input pin tdi i test data input serial input pin for instructions and data tdo o test data output serial output pin for instructions and data user debugging interface (h-udi) trst i test reset initial-signal input pin section 1 overview rev. 3.00 jan. 18, 2008 page 35 of 1458 rej09b0033-0300 classification symbol i/o name function audata3 to audata0 o aud data destination-address output pin in branch-trace mode audck o aud clock synchronous clock output pin in branch-trace mode advanced user debugger (aud) audsync o aud synchronous signal data start-position acknowledge- signal output pin in branch-trace mode asebrkak o ase break mode acknowledge indicates that the e10a emulator has entered its break mode. e10a interface asemd0 i ase mode sets ase mode. notes: 1. all vcc/vss/vccq/vssq/vccq1/v ssq1/avcc/avss/avcc_usb/avss_usb/vccq_rtc/ vcc_rtc/vss_rtc/vcc_pll1/vss_pll1/vcc_pll2/vss_pll2 should be connected to the system power supply (so that power is supplied at all times.) in hardware standby mode, the power supply to other than vcc_rtc and vccq_rtc can be turned off (section 13.8). 2. always supply power to the vcc_rtc an d vccq_rtc, even if the rtc is not being used. 3. always supply power to the vcc_pll1 an d vcc_pll2, even if the pll is not being used. 4. drive asemd0 high when using the user system alon e, and not using an emulator or the h-udi. when this pin is low or open, resetp may be masked. 5. drivability can be switched by the register settings of the pin function controller (pfc). when 3.3 v is applied to vccq1, set the dr ivability low. when 1.8 v is applied to vccq1, set the drivability high. 6. sdhi associated pins support only for the models including the sdhi. section 1 overview rev. 3.00 jan. 18, 2008 page 36 of 1458 rej09b0033-0300 section 2 cpu cpus3d0s_000020020300 rev. 3.00 jan. 18, 2008 page 37 of 1458 rej09b0033-0300 section 2 cpu 2.1 processing states and processing modes 2.1.1 processing states this lsi supports four types of processing states: a reset state, an exception handling state, a program execution state, and a low-power consum ption state, according to the cpu processing states. (1) reset state in the reset state, the cpu is reset. the lsi supports two types of resets: power-on reset and manual reset. for details on resets, refer to section 7, exception handling. in power-on reset, the registers an d internal statuses of all lsi on -chip modules are initialized. in manual reset, the register conten ts of a part of the lsi on-chip modules are retained. for details, refer to section 37, list of registers. the cpu inte rnal statuses and registers are initialized both in power-on reset and manual reset. after initi alization, the program branches to address h'a0000000 to pass control to the reset processing program to be executed. (2) exception handling state in the exception handling state, the cpu processing flow is changed temporarily by a general exception or interrupt exception pr ocessing. the program counter (pc) and status register (sr) are saved in the save program counter (spc) and save status register (ssr), respectively. the program branches to an address ob tained by adding a vector offset to the vector base register (vbr) and passes control to the exception processing program defined by the user to be executed. for details on reset, refer to section 7, exception handling. (3) program execution state the cpu executes programs sequentially. (4) low-power consumption state the cpu stops operation to reduce power consumption. the power-down mode can be entered by executing the sleep instruction. for details on the power-down mode, refer to section 13, power- down modes. figure 2.1 shows a status transition diagram. section 2 cpu rev. 3.00 jan. 18, 2008 page 38 of 1458 rej09b0033-0300 2.1.2 processing modes this lsi supports two processing modes: user mode and privileged mode. these processing modes can be determined by the processing mode bit (md) in the status register (sr). if the md bit is cleared to 0, the user mode is selected. if the md bit is set to 1, the privileged mode is selected. the cpu enters the privileged mode by a transition to reset state or exception handling state. in the privileged mode , any registers and resources in address spaces can be accessed. clearing the md bit in the sr to 0 puts the cpu in the user mode. in the user mode, some of the registers, including sr, and so me of the address spaces cannot be accessed by the user program and system control instru ctions cannot be executed. this func tion effectively protects the system resources from the user program. to change the processing mode from user to privileged mode, a transition to exception handling state is required. note: to call a service routine used in privileged mode from user mode, the lsi supports an unconditional trap instruction (trapa). when a transition from user mode to privileged mode occurs, the contents of the sr and pc are saved. a program execution in user mode can be resumed by restoring the contents of the sr and pc. to return from an exception processing program, the lsi supports an rte instruction. (from any states) power-on reset manual reset reset state program execution state low-power consumption state exception handling state an exception is accepted exception handling routine starts reset processing routine starts an exception is accepted multiple exceptions sleep instruction figure 2.1 processing state transitions section 2 cpu rev. 3.00 jan. 18, 2008 page 39 of 1458 rej09b0033-0300 2.2 memory map 2.2.1 virtual address space the lsi supports 32-bit virtual addresses and accesses system reso urces using the 4-gbytes of virtual address space. user prog rams and data are accessed from the virtual address space. the virtual address space is divided into se veral areas as shown in table 2.1. (1) p0/u0 area this area is called the p0 area when the cpu is in privileged mode and the u0 area when in user mode. for the p0 and u0 areas, access using th e cache is enabled. the p0 and u0 areas are handled as address translatable areas. if the cache is enabled, access to the p0 or u0 ar ea is cached. if a p0 or u0 address is specified while the address translation unit is enabled, the p0 or u0 address is tran slated into a physical address based on translation information defined by the user. if the cpu is in user mode, only the u0 area can be accessed. if p1, p2, p3, or p4 is accessed in user mode, a transition to an address error exception occurs. (2) p1 area the p1 area is defined as a ca cheable but non-address translat able area. normally, programs executed at high speed in privileged mode, such as exception processing handlers, which are at the core of the operating system (os) , are assigned to the p1 area. (3) p2 area the p2 area is defined as a non-cacheable but n on-address translatable area. a reset processing program to be called from the reset state is described at the start address (h'a0000000) of the p2 area. normally, programs such as system initialization routines and os initiation programs are assigned to the p2 area. to access a part of an on-chip i/o, its corresponding program should be assigned to the p2 area. (4) p3 area the p3 area is defined as a cacheable and address tr anslatable area. this area is used if an address translation is required for a privileged program. section 2 cpu rev. 3.00 jan. 18, 2008 page 40 of 1458 rej09b0033-0300 (5) p4 area the p4 area is defined as a control area which is non-cacheable and non-addr ess translatable. this area can be accessed only in privileged mode. a part of the lsi?s on-chip i/o is assigned to this area. table 2.1 virtual address space address range name mode description h'00000000 to h'7fffffff p0/u0 privileged/user mode 2-gbyte physical space, cacheable, address translatable in user mode, only this address space can be accessed. h'80000000 to h'9fffffff p1 privileged mode 0.5-gbyte physical space, cacheable h'a0000000 to h'bfffffff p2 privileged mode 0.5-gbyte physical space, non-cacheable h'c0000000 to h'dfffffff p3 privileged mode 0.5-gbyte physical space, cacheable, address translatable h'e0000000 to h'ffffffff p4 privileged mode 0.5-gbyte control space, non-cacheable 2.2.2 external memory space this lsi uses 29 bits of the 32-bit virtual addr ess to access external memo ry. in this case, 0.5- gbyte of external memory space can be accessed. the external memory space is managed in area units. different types of memory can be connected to each area, as shown in figure 2.2. for details, please refer to section 9, bus state controller (bsc). in addition, area 1 in the extern al memory space is used as an on -chip i/o space where most of this lsi?s on-chip i/os are mapped. normally, the upper three bits of the 32-bit virtual address are masked and the lower 29 bits are used for external memory addresses.* 2 for example, address h'00000100 in the p0 area, address h'80000100 in the p1 area, address h'a0000100 in the p2 area, and address h'c0000100 in the p3 area of the virtual address space are mapped into address h'00000100 of area 0 in the external memory space. the p4 area in th e virtual address space is not mapped into the external memory address. if an address in th e p4 area is accessed, an external memory cannot be accessed. section 2 cpu rev. 3.00 jan. 18, 2008 page 41 of 1458 rej09b0033-0300 notes: 1. to access an on-chip i/o mapped into area 1 in the external memory space, access the address from the p2 area which is not cached in th e virtual address space. 2. if the address translation unit is enabled, arbitrary mapping in page units can be specified. for details, refer to section 4, memory management unit (mmu). p0 area privileged mode user mode external memory space area 0 area 1 area 2 area 3 area 4 area 5 area 6 area 7 h'0000 0000 h'0000 0000 h'8000 0000 h'ffff ffff h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff u0 area address error p1 area p2 area p3 area p4 area figure 2.2 virtual address to external memory space mapping section 2 cpu rev. 3.00 jan. 18, 2008 page 42 of 1458 rej09b0033-0300 2.3 register descriptions this lsi provides thirty-three 32-bit registers: 24 general registers, five control registers, three system registers, and one program counter. (1) general registers this lsi incorporates 24 general registers: r0_bank0 to r7_bank0, r0_bank1 to r7_bank1 and r8 to r15. r0 to r7 are banked. the process mode and the register bank (rb) bit in the status register (sr) define which set of banked registers (r0_bank0 to r7_bank0 or r0_bank1 to r7_bank1) are acce ssed as general registers. (2) system registers this lsi incorporates the multiply and accum ulate registers (mach/macl) and procedure register (pr) as system regist ers. these registers can be accessed regardless of the processing mode. (3) program counter the program counter stores the va lue obtained by adding 4 to th e current instruction address. (4) control registers this lsi incorporates the status register (sr), gl obal base register (gbr), save status register (ssr), save program counter (spc), and vector base register as control register. only the gbr can be accessed in user mode. control registers other than the gbr can be accessed only in privileged mode. section 2 cpu rev. 3.00 jan. 18, 2008 page 43 of 1458 rej09b0033-0300 table 2.2 shows the register values after reset. figure 2.3 shows the register configurations in each process mode. table 2.2 register initial values register type registers initial values * general registers r0_bank0 to r7_bank0, r0_bank1 to r7_bank1, r8 to r15 undefined system registers mach, macl, pr undefined program counter pc h'a0000000 sr md bit = 1, rb bit = 1, bl bit = 1, i3 to i0 bits = h'f (1111), reserved bits = all 0, other bits = undefined gbr, ssr, spc undefined control registers vbr h'00000000 note: * initialized by a power-on or manual reset. section 2 cpu rev. 3.00 jan. 18, 2008 page 44 of 1458 rej09b0033-0300 31 r0_bank0 * 1, * 2 r1_bank0 * 2 r2_bank0 * 2 r3_bank0 * 2 r4_bank0 * 2 r5_bank0 * 2 r6_bank0 * 2 r7_bank0 * 2 r8 r9 r10 r11 r12 r13 r14 r15 sr gbr mach macl pr pc 031 r0_bank1 * 1, * 3 r1_bank1 * 3 r2_bank1 * 3 r3_bank1 * 3 r4_bank1 * 3 r5_bank1 * 3 r6_bank1 * 3 r7_bank1 * 3 r0_bank0 * 1, * 4 r1_bank0 * 4 r2_bank0 * 4 r3_bank0 * 4 r4_bank0 * 4 r5_bank0 * 4 r6_bank0 * 4 r7_bank0 * 4 r8 r9 r10 r11 r12 r13 r14 r15 sr ssr gbr mach macl vbr pr pc spc 031 r0_bank0 * 1, * 4 r1_bank0 * 4 r2_bank0 * 4 r3_bank0 * 4 r4_bank0 * 4 r5_bank0 * 4 r6_bank0 * 4 r7_bank0 * 4 r0_bank1 * 1, * 3 r1_bank1 * 3 r2_bank1 * 3 r3_bank1 * 3 r4_bank1 * 3 r5_bank1 * 3 r6_bank1 * 3 r7_bank1 * 3 r8 r9 r10 r11 r12 r13 r14 r15 sr ssr gbr mach macl vbr pr pc spc 0 (a) user mode register configuration (b) privileged mode register configuration (rb = 1) (c) privileged mode register configuration (rb = 0) notes: 1. the r0 register is used as an index register in indexed register indirect addressing mode and indexed gbr indirect addressing mode. 2. bank register 3. bank register accessed as a general register when the rb bit is set to 1 in the sr register. accessed only by ldc/stc instructions when the rb bit is cleared to 0. 4. bank register accessed as a general register when the rb bit is cleared to 0 in the sr register. accessed only by ldc/stc instructions when the rb bit is set to 1. figure 2.3 register configurat ion in each processing mode section 2 cpu rev. 3.00 jan. 18, 2008 page 45 of 1458 rej09b0033-0300 2.3.1 general registers there are twenty-four 32-bit general registers: r0_bank0 to r7_bank0, r0_bank1 to r7_bank1, and r8 to r15. r0 to r7 are banked. the process mode and the register bank (rb) bit in the status register (sr) define which set of banked registers (r0_bank0 to r7_bank0 or r0_bank1 to r7_bank1) are accessed as general registers. r0 to r7 registers in the selected bank are accessed as r0 to r7. r0 to r7 in the non-selected bank is accessed as r0_bank to r7_bank by the control register load instruction (ldc) and control register store instruction (stc). in user mode, bank 0 is selected regardless of the rb bit value. sixteen registers: r0_bank0 to r7_bank0 and r8 to r15 are accessed as gene ral registers r0 to r15. the r0_bank1 to r7_bank1 registers in bank 1 cannot be accessed. in privileged mode that is entered by a transition to exception handling state, the rb bit is set to 1 to select bank 1. in privileged mode, sixteen registers: r0_bank1 to r7_bank1 and r8 to r15 are accessed as general registers r0 to r15. a bank is switched automatically when an exception handling state is entered, registers r0 to r7 need not be saved by the exception handling routine. the r0_bank0 to r7_bank0 registers in bank 0 can be accessed as r0_bank to r7_bank by the ldc and stc instructions. in privileged mode, bank 0 can also be used as general registers by clearing the rb bit to 0. in this case, sixteen registers: r0_bank0 to r7_bank0 and r8 to r15 are accessed as general registers r0 to r15. the r0 _bank1 to r7_bank1 registers in bank 1 can be accessed as r0_bank to r7_bank by the ldc and stc instructions. the general registers r0 to r15 are used as equivalent registers for almost all instructions. in some instructions, the r0 register is automatically used or only the r0 register can be used as source or destination registers. section 2 cpu rev. 3.00 jan. 18, 2008 page 46 of 1458 rej09b0033-0300 31 r0 * 1, * 2 r1 * 2 r2 * 2 r3 * 2 r4 * 2 r5 * 2 r6 * 2 r7 * 2 r8 r9 r10 r11 r12 r13 r14 r15 0 general registers: undefined after reset notes: 1. r0 functions as an index register in the indexed register-indirect addressing mode and indexed gbr-indirect addressing mode. in some instructions, only r0 can be used as the source or destination register. 2. r0 to r7 are banked registers. in privileged mode, either r0_bank0 to r7_bank0 or r0_bank1 to r7_bank1 is selected by the rb bit in the sr register. figure 2.4 general registers 2.3.2 system registers the system registers: multiply and accumulate registers (mach/ macl) and procedure register (pr) as system registers can be acce ssed by the lds and sts instructions. (1) multiply and accumula te registers (mach/macl) the multiply and accumulate registers (mach/ma cl) store the results of multiplication and accumulation instructions or mu ltiplication instructions. the ma ch/macl registers also store addition values for the multiplication and accumulati ons. after reset, these registers are undefined. the mach and macl registers store upper 32 bits and lower 32 bits, respectively. (2) procedure register (pr) the procedure register (pr) stor es the return addres s for a subroutine call using the bsr, bsrf, or jsr instruction. the return addr ess stored in the pr register is restored to the program counter (pc) by the rts (return from the subroutine) instruction. after reset, this register is undefined. section 2 cpu rev. 3.00 jan. 18, 2008 page 47 of 1458 rej09b0033-0300 2.3.3 program counter the program counter (pc) stores the value obtained by adding 4 to the curr ent instruction address. there is no instruction to read the pc directly. before an exception handlin g state is entered, the pc is saved in the save program counter (spc). before a subroutine call is executed, the pc is saved in the procedure register (pr). in addition, the pc can be used for pc relative addressing mode. figure 2.5 shows the system register and program counter configurations. mach macl 31 0 pr 31 0 pc 31 0 multiply and accumulate high and low registers (mach/macl) procedure register (pr) program counter (pc) figure 2.5 system regi sters and program counter section 2 cpu rev. 3.00 jan. 18, 2008 page 48 of 1458 rej09b0033-0300 2.3.4 control registers the control registers (sr, ss r, spc, gbr, and vbr) can be accessed by the ldc or stc instruction in privileged mode. the gbr regi ster can be accessed in the user mode. the control registers are described below. (1) status register (sr) the status register (sr) indicates the system st atus as shown below. the sr register can be accessed only in privileged mode. bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 md 1 r/w processing mode indicates the cpu processing mode. 0: user mode 1: privileged mode the md bit is set to 1 in reset or exception handling state. 29 rb 1 r/w register bank the general registers r0 to r7 are banked registers. 0: in this case, r0_bank0 to r7_bank0 and r8 to r15 are used as general registers. r0_bank1 to r7_bank1 can be accessed by the ldc or str instruction. 1: in this case, r0_bank1 to r7_bank1 and r8 to r15 are used as general registers. r0_bank0 to r7_bank0 can be accessed by the ldc or str instruction. the rb bit is set to 1 in reset or exception handling state. section 2 cpu rev. 3.00 jan. 18, 2008 page 49 of 1458 rej09b0033-0300 bit bit name initial value r/w description 28 bl 1 r/w block specifies whether an exception, interrupt, or user break is enabled or not. 0: enables an exception, interrupt, or user break. 1: disables an exception, interrupt, or user break. the bl bit is set to 1 in reset or exception handling state. 27 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 m q ? ? r/w r/w m bit q bit these bits are used by t he div0s, div0u, and div1 instructions. these bits can be changed even in user mode by using the div0 s, div0u, and div1 instructions. these bits ar e undefined at reset. these bits do not change in an ex ception handling state. 7 to 4 i3 to i0 all 1 r/w interrupt mask indicates the interrupt mask level. these bits do not change even if an interrupt occurs. at reset, these bits are initialized to b'1111. thes e bits are not affected in an exception handling state. 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 s ? r/w saturation mode specifies the saturation mode for multiply instructions or multiply and accumulate instructions. this bit can be specified by the sets and clrs instructions in user mode. at reset, this bit is undefined. this bit is not affected in an exception handling state. section 2 cpu rev. 3.00 jan. 18, 2008 page 50 of 1458 rej09b0033-0300 bit bit name initial value r/w description 0 t ? r/w t bit indicates true or false for compare instructions or carry or borrow occurrence for an operation instruction with carry or borrow. this bit can be specified by the sett and clrt instructions in user mode. at reset, this bit is undefined. this bit is not affected in an exception handling state. note: the m, q, s, and t bits can be set/cleared by the user mode specific instructions. other bits can be read or written in privileged mode. (2) save status register (ssr) the save status regist er (ssr) can be accessed only in priv ileged mode. before entering the exception, the contents of the sr register is stored in the ssr re gister. at reset, the ssr initial value is undefined. (3) save program counter (spc) the save program counter (spc) can be accessed on ly in privileged mode. before entering the exception, the contents of the pc is stored in th e spc. at reset, the spc initial value is undefined. (4) global base register (gbr) the global base register (gbr) is referenced as a base register in gbr indirect addressing mode. at reset, the gbr initial value is undefined. (5) vector base register (vbr) the vector base register (vbr) can be accessed on ly in privileged mode. if a transition from reset state to exception ha ndling state occurs, this register is refe renced as a base address. for details, refer to section 7, exception handling. at reset, the vbr is initialized as h'00000000. section 2 cpu rev. 3.00 jan. 18, 2008 page 51 of 1458 rej09b0033-0300 figure 2.6 shows the control register configuration. 31 0 31 spc ssr 0 save status register (ssr) save program counter (spc) 31 0 31 vbr gbr 0 global base register (gbr) vector base register (vbr) 31 0 0 md rb bl 0 status register (sr) t s 0 0 i0 i1 i2 i3 q m 0 figure 2.6 control register configuration 2.4 data formats 2.4.1 register data format register operands are always longwords (32 bits). when the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. 31 0 longword section 2 cpu rev. 3.00 jan. 18, 2008 page 52 of 1458 rej09b0033-0300 2.4.2 memory data formats memory data formats are classi fied into byte, word, and long word. memory can be accessed in byte, word, and longword. when the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register. an address error will occur if word data starting from an address other than 2n or longword data starting from an address other th an 4n is accessed. in such cases, the data accessed cannot be guaranteed. when a word or longword operand is accessed, th e byte positions on the me mory corres ponding to the word or longword data on the register is determined to the specified endian mode (big endian or little endian). figure 2.7 shows a byte correspondence in big endian mode. in big endian mode, the msb byte in the register corresponds to the lowest address in the memory, and the lsb the in the register corresponds to the highest address. for example, if the contents of th e general register r0 is stored at an address indicated by the general register r1 in longword, the msb byte of the r0 is stored at the address indicated by the r1 and the lsb byte of the r1 regist er is stored at the address indicated by the (r1 +3). the on-chip device registers assigne d to memory are accessed in big endian mode. note that the available access size (byte, word, or l ong word) differs in each register. note: the cpu instruction codes of this lsi must be stored in word units. in big endian mode, the instruction code must be stored from upper byte to lower byte in this order from the word boundary of the memory. 31 @(r1+0) @(r1+1) @(r1+2) @(r1+3) @(r1+0) @(r1+1) @(r1+2) @(r1+3) @(r1+0) @(r1+1) @(r1+2) @(r1+3) [7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [15:8] [7:0] [7:0] (a) byte access example: mov.b r0, @r1 (r1 = address 4n) (b) word access example: mov.w r0, @r1 (r1 = address 4n) (c) longword access example: mov.l r0, @r1 (r1 = address 4n) byte position in r0 byte position in memory 23 15 7 0 figure 2.7 data format on memory (big endian mode) section 2 cpu rev. 3.00 jan. 18, 2008 page 53 of 1458 rej09b0033-0300 the little endian mode can also be specified as data format. either big-endian or little-endian mode can be selected according to the md5 pin at rese t. when md5 is low at reset, the processor operates in big-endian mode. when md5 is high at reset, the processor operates in little-endian mode. the endian mode cannot be modified dynamically. in little endian mode, the msb byte in the regi ster corresponds to the highest address in the memory, and the lsb the in the register corres ponds to the lowest address (figure 2.8). for example, if the contents of the general register r0 is stored at an address indicated by the general register r1 in longword, the msb byte of the r0 is stored at the address indicated by the (r1+3) and the lsb byte of the r1 register is st ored at the address indicated by the r1. if the little endian mode is selected, the on- chip memory are accessed in little endian mode. however, the on-chip device regi sters assigned to memory are acce ssed in big endian mode. note that the available access size (byte, word, or long word ) differs in each register. note: the cpu instruction codes of this lsi must be stored in word units. in little endian mode, the instruction code must be stored from lower byte to upper byte in this order from the word boundary of the memory. 31 @(r1+3) @(r1+2) @(r1+1) @(r1+0) @(r1+3) @(r1+2) @(r1+1) @(r1+0) @(r1+3) @(r1+2) @(r1+1) @(r1+0) [7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0] [15:8] [7:0] [7:0] (a) byte access example: mov.b r0, @r1 (r1 = address 4n) (b) word access example: mov.w r0, @r1 (r1 = address 4n) (c) longword access example: mov.l r0, @r1 (r1 = address 4n) byte position in r0 byte position in memory 23 15 7 0 figure 2.8 data format on memory (little endian mode) section 2 cpu rev. 3.00 jan. 18, 2008 page 54 of 1458 rej09b0033-0300 2.5 features of cpu core instructions 2.5.1 instruction execution method (1) instruction length all instructions have a fixed length of 16 bits and are executed in the sequential pipeline. in the sequential pipeline, almost all instructions can be executed in one cycle. al l data items are handles in longword (32 bits). memory can be accessed in byte, word, or longword. in this case, memory byte or word data is sign-extended and operated on as longword data. immediate data is sign- extended to longword size for arithmetic operations (mov, add, and cmp/eq instructions) or zero-extended to longword size fo r logical operations (tst, and , or, and xor instructions). (2) load/store architecture basic operations are executed between registers. in operations involving memory, data is first loaded into a register (load/stor e architecture). however, bit mani pulation instructions such as and are executed directly on memory. (3) delayed branching unconditional branch instructions are executed as delayed branches. with a delayed branch instruction, the branch is made after execution of the instruction (calle d the slot instruction) immediately following the delayed branch instruction. this minimizes disruption of the pipeline when a branch is made. this lsi supports two types of conditional branch instructions: delayed branch instruction or normal branch instruction. example: bra target add r1, r0 ; add is executed before branching to the target section 2 cpu rev. 3.00 jan. 18, 2008 page 55 of 1458 rej09b0033-0300 (4) t bit the result of a comparison is indicated by the t b it in the status register (sr), and a conditional branch is performed according to whether the result is true or false. processing speed has been improved by keeping the number of instructions that modify the t bit to a minimum. example: add #1, r0 ; the t bit cannot be modified by the add instruction cmp/eq #0, r0 ; the t bit is set to 1 if r0 is 0. bt target ; branch to target if the t bit is set to 1 (r0=0). (5) literal constant byte literal constant is placed inside the instruc tion code as immediate da ta. since the instruction length is fixed to 16 bits, word and longword literal constant is not placed inside the instruction code, but in a table in memory. the table in memory is referenced with a mov instruction using pc-relative addressing mo de with displacement. example: mov.w @(disp, pc), r0 (6) absolute addresses when data is referenced by abso lute address, the abso lute address value is placed in a table in memory beforehand as well as word or longword literal constant. using the method whereby immediate data is loaded when an instruction is ex ecuted, this value is transferred to a register and the data is referenced using register indirect addressing mode. (7) 16-bit/32-bit displacement when data is referenced with a 16- or 32-bit displacem ent, the displacement value is placed in a table in memory beforehand. using the method whereby word or longword immediate data is loaded when an instruction is executed, this valu e is transferred to a register and the data is referenced using indexed register indirect addressing mode. section 2 cpu rev. 3.00 jan. 18, 2008 page 56 of 1458 rej09b0033-0300 2.5.2 cpu instruction addressing modes the following table shows addressing modes and effective address calculation methods for instructions executed by the cpu core. table 2.3 addressing modes and effect ive addresses for cpu instructions addressing mode instruction format effective address calculation method calculation formula register direct rn effective address is register rn. (operand is register rn contents.) ? register indirect @rn effective address is register rn contents. rn rn rn register indirect with post-increment @rn+ effective address is register rn contents. a constant is added to rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn rn 1/2/4 + rn + 1/2/4 rn after instruction execution byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn register indirect with pre-decrement @?rn effective address is register rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn rn - 1/2/4 1/2/4 - rn - 1/2/4 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn (instruction executed with rn after calculation) section 2 cpu rev. 3.00 jan. 18, 2008 page 57 of 1458 rej09b0033-0300 addressing mode instruction format effective address calculation method calculation formula register indirect with displacement @(disp:4, rn) effective address is register rn contents with 4-bit displacement disp added. after disp is zero- extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. rn rn + disp 1/2/4 1/2/4 + disp (zero-extended) byte: rn + disp word: rn + disp 2 longword: rn + disp 4 indexed register indirect @(r0, rn) effective address is sum of register rn and r0 contents. + rn r0 rn + r0 rn + r0 gbr indirect with displacement @(disp:8, gbr) effective address is register gbr contents with 8- bit displacement disp added. after disp is zero- extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. gbr gbr + disp 1/2/4 1/2/4 + disp (zero-extended) byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4 indexed gbr indirect @(r0, gbr) effective address is sum of register gbr and r0 contents. gbr gbr + r0 r0 + gbr + r0 section 2 cpu rev. 3.00 jan. 18, 2008 page 58 of 1458 rej09b0033-0300 addressing mode instruction format effective address calculation method calculation formula pc-relative with displacement @(disp:8, pc) effective address is pc with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. with a longword operand, the lower 2 bits of pc are masked. pc pc + disp 2 or pc & h'fffffffc + disp 4 h'fffffffc + & 2/4 disp (zero-extended) * *: with longword operand word: pc + disp 2 longword: pc&h'fffffffc + disp 4 pc-relative disp:8 effective address is pc with 8-bit displacement disp added after being sign-extended and multiplied by 2. pc 2 disp (sign-extended) + pc + disp 2 pc + disp 2 disp:12 effective address is pc with 12-bit displacement disp added after being sign-extended and multiplied by 2 pc 2 disp (sign-extended) + pc + disp 2 pc + disp 2 rn effective address is sum of pc and rn. pc pc + rn rn + pc + rn section 2 cpu rev. 3.00 jan. 18, 2008 page 59 of 1458 rej09b0033-0300 addressing mode instruction format effective address calculation method calculation formula #imm:8 8-bit immediate data imm of tst, and, or, or xor instruction is zero-extended. ? #imm:8 8-bit immediate data imm of mov, add, or cmp/eq instruction is sign-extended. ? immediate #imm:8 8-bit immediate data imm of trapa instruction is zero-extended and multiplied by 4. ? note: for addressing modes with displacement (dis p) as shown below, the assembler description in this manual indicates the value before it is scaled (x1, x2, or x4) according to the operand size to clarify the lsi operation. for det ails on assembler description, refer to the description rules in each assembler. @ (disp:4, rn) ; register indirect with displacement @ (disp:8, gbr) ; gbr indirect with displacement @ (disp:8, pc) ; pc rela tive with displacement disp:8, disp:12 ; pc relative section 2 cpu rev. 3.00 jan. 18, 2008 page 60 of 1458 rej09b0033-0300 2.5.3 instruction formats table 2.4 shows the instruction formats, and the meaning of the source and destination operands, for instructions executed by the cpu core. the meaning of the operands depends on the instruction code. the following symbols are used in the table. xxxx: instruction code mmmm: source register nnnn: destination register iiii: immediate data dddd: displacement table 2.4 cpu instruction formats instruction format source operand destination operand sample instruction 0 type xxxx xxxx xxxx xxxx 15 0 ? ? nop n type xxxx nnnn xxxx xxxx 15 0 ? nnnn: register direct movt rn control register or system register nnnn: register direct sts mach,rn control register or system register nnnn: pre- decrement register indirect stc.l sr,@-rn m type xxxx mmmm xxxx xxxx 15 0 mmmm: register direct control register or system register ldc rm,sr mmmm: post- increment register indirect control register or system register ldc.l @rm+,sr mmmm: register indirect ? jmp @rm pc-relative using rm ? braf rm section 2 cpu rev. 3.00 jan. 18, 2008 page 61 of 1458 rej09b0033-0300 instruction format source operand destination operand sample instruction nm type xxxx nnnn mmmm xxxx 15 0 mmmm: register direct nnnn: register direct add rm,rn mmmm: register indirect nnnn: register indirect mov.l rm,@rn mmmm: post- increment register indirect (multiply- and-accumulate operation) nnnn: * post- increment register indirect (multiply- and-accumulate operation) mach, macl mac.w @rm+,@rn+ mmmm: post- increment register indirect nnnn: register direct mov.l @rm+,rn mmmm: register direct nnnn: pre- decrement register indirect mov.l rm,@-rn mmmm: register direct nnnn: indexed register indirect mov.l rm,@(r0,rn) md type xxxx xxxx mmmm dddd 15 0 mmmmdddd: register indirect with displacement r0 (register direct) mov.b @(disp,rm),r0 nd4 type xxxx xxxx nnnn dddd 15 0 r0 (register direct) nnnndddd: register indirect with displacement mov.b r0,@(disp,rn) nmd type xxxx nnnn mmmm dddd 15 0 mmmm: register direct nnnndddd: register indirect with displacement mov.l rm,@(disp,rn) mmmmdddd: register indirect with displacement nnnn: register direct mov.l @(disp,rm),rn section 2 cpu rev. 3.00 jan. 18, 2008 page 62 of 1458 rej09b0033-0300 instruction format source operand destination operand sample instruction d type xxxx xxxx dddd dddd 15 0 dddddddd: gbr indirect with displacement r0 (register direct) mov.l @(disp,gbr),r0 r0 (register direct) dddddddd: gbr indirect with displacement mov.l r0,@(disp,gbr) dddddddd: pc-relative with displacement r0 (register direct) mova @(disp,pc),r0 dddddddd: pc-relative ? bf label d12 type xxxx dddd dddd dddd 15 0 dddddddddddd: pc-relative ? bra label (label=disp+pc) nd8 type xxxx nnnn dddd dddd 15 0 dddddddd: pc- relative with displacement nnnn: register direct mov.l @(disp,pc),rn i type xxxx xxxx i i i i i i i i 15 0 iiiiiiii: immediate indexed gbr indirect and.b #imm,@(r0,gbr) iiiiiiii: immediate r0 (register direct) and #imm,r0 iiiiiiii: immediate ? trapa #imm ni type xxxx nnnn i i i i i i i i 15 0 iiiiiiii: immediate nnnn: register direct add #imm,rn note: * in multiply-and-accumula te instructions, nnnn is the source register. section 2 cpu rev. 3.00 jan. 18, 2008 page 63 of 1458 rej09b0033-0300 2.6 instruction set 2.6.1 instruction set based on functions table 2.5 shows the instructions classified by function. table 2.5 cpu instruction types type kinds of instruction op code function number of instructions mov data transfer 39 mova effective address transfer movt t bit transfer swap upper/lower swap data transfer instructions 5 xtrct extraction of middl e of linked registers 21 add binary addition 33 addc binary addition with carry addv binary addition with overflow check cmp/cond comparison div1 division div0s signed division initialization div0u unsigned division initialization dmuls signed double-precision multiplication dmulu unsigned double-precision multiplication dt decrement and test exts sign extension extu zero extension mac multiply-and-accumulate, double- precision multiply-and-accumulate arithmetic operation instructions mul double-precision multiplication (32 32 bits) section 2 cpu rev. 3.00 jan. 18, 2008 page 64 of 1458 rej09b0033-0300 type kinds of instruction op code function number of instructions 21 muls signed multiplication (16 16 bits) 33 mulu unsigned multiplication (16 16 bits) neg sign inversion negc sign inversion with borrow sub binary subtraction subc binary subtraction with borrow arithmetic operation instructions subv binary subtraction with underflow 6 and logical and 14 not bit inversion or logical or tas memory test and bit setting tst logical and and t bit setting logic operation instructions xor exclusive logical or 12 rotcl 1-bit left shift with t bit 16 rotcr 1-bit right shift with t bit rotl 1-bit left shift rotr 1-bit right shift shad arithmetic dynamic shift shift instructions shal arithmetic 1-bit left shift shar arithmetic 1-bit right shift shld logical dynamic shift shll logical 1-bit left shift shlln logical n-bit left shift shlr logical 1-bit right shift shlrn logical n-bit right shift section 2 cpu rev. 3.00 jan. 18, 2008 page 65 of 1458 rej09b0033-0300 type kinds of instruction op code function number of instructions 9 bf conditional branch, delayed conditional branch (t = 0) 11 bt conditional branch, delayed conditional branch (t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure branch instructions rts return from subroutine procedure 15 clrmac mac register clear 75 clrs s bit clear system control instructions clrt t bit clear ldc load into control register lds load into system register ldtlb pteh/ptel load into tlb nop no operation pref data prefetch to cache rte return from exception handling sets s bit setting sett t bit setting sleep transition to power-down mode stc store from control register sts store from system register trapa trap exception handling total: 68 188 the instruction code, operation, an d number of execution states of the cpu instructions are shown in the following tables, classified by instruction type, using the format shown below. section 2 cpu rev. 3.00 jan. 18, 2008 page 66 of 1458 rej09b0033-0300 instruction instruction code operation privilege execution states t bit indicated by mnemonic. explanation of symbols op.sz src, dest op: operation code sz: size src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement indicated in msb ? lsb order. explanation of symbols mmmm: source register nnnn: destination register 0000: r0 0001: r1 ......... 1111: r15 iiii: immediate data dddd: displacement * 2 indicates summary of operation. explanation of symbols , : transfer direction (xx): memory operand m/q/t: flag bits in sr &: logical and of each bit |: logical or of each bit ^: exclusive logical or of each bit ~: logical not of each bit < section 2 cpu rev. 3.00 jan. 18, 2008 page 67 of 1458 rej09b0033-0300 table 2.6 data transfer instructions instruction instruction code operation privileged mode cycles t bit mov #imm,rn 1110nnnniiiiiiii imm sign extension rn ? 1 ? mov.w @(disp,pc),rn 1001nnnndddddddd (disp x 2+pc) sign extension rn ? 1 ? mov.l @(disp,pc),rn 1101nnnndddddddd (disp x 4+pc) rn ? 1 ? mov rm,rn 0110nnnnmmmm0011 rm rn ? 1 ? mov.b rm,@rn 0010nnnnmmmm0000 rm (rn) ? 1 ? mov.w rm,@rn 0010nnnnmmmm0001 rm (rn) ? 1 ? mov.l rm,@rn 0010nnnnmmmm0010 rm (rn) ? 1 ? mov.b @rm,rn 0110nnnnmmmm0000 (rm) sign extension rn ? 1 ? mov.w @rm,rn 0110nnnnmmmm0001 (rm) sign extension rn ? 1 ? mov.l @rm,rn 0110nnnnmmmm0010 (rm) rn ? 1 ? mov.b rm,@?rn 0010nnnnmmmm0100 rn?1 rn, rm (rn) ? 1 ? mov.w rm,@?rn 0010nnnnmmmm0101 rn?2 rn, rm (rn) ? 1 ? mov.l rm,@?rn 0010nnnnmmmm0110 rn?4 rn, rm (rn) ? 1 ? mov.b @rm+,rn 0110nnnnmmmm0100 (rm) sign extension rn, rm+1 rm ? 1 ? mov.w @rm+,rn 0110nnnnmmmm0101 (rm) sign extension rn, rm+2 rm ? 1 ? mov.l @rm+,rn 0110nnnnmmmm0110 (rm) rn, rm+4 rm ? 1 ? mov.b r0,@(disp,rn) 10000000nnnndddd r0 (disp+rn) ? 1 ? mov.w r0,@(disp,rn) 10000001nnnndddd r0 (disp x 2+rn) ? 1 ? mov.l rm,@(disp,rn) 0001nnnnmmmmdddd rm (disp x 4+rn) ? 1 ? mov.b @(disp,rm),r0 10000100mmmmdddd (disp+rm) sign extension r0 ? 1 ? mov.w @(disp,rm),r0 10000101mmmmdddd (disp x 2+rm) sign extension r0 ? 1 ? mov.l @(disp,rm),rn 0101nnnnmmmmdddd (disp x 4+rm) rn ? 1 ? mov.b rm,@(r0,rn) 0000nnnnmmmm0100 rm (r0+rn) ? 1 ? mov.w rm,@(r0,rn) 0000nnnnmmmm0101 rm (r0+rn) ? 1 ? mov.l rm,@(r0,rn) 0000nnnnmmmm0110 rm (r0+rn) ? 1 ? section 2 cpu rev. 3.00 jan. 18, 2008 page 68 of 1458 rej09b0033-0300 instruction instruction code operation privileged mode cycles t bit mov.b @(r0,rm),rn 0000nnnnmmmm1100 (r0+rm) sign extension rn ? 1 ? mov.w @(r0,rm),rn 0000nnnnmmmm1101 (r0+rm) sign extension rn ? 1 ? mov.l @(r0,rm),rn 0000nnnnmmmm1110 (r0+rm) rn ? 1 ? mov.b r0,@(disp,gbr) 11000000dddddddd r0 (disp+gbr) ? 1 ? mov.w r0,@(disp,gbr) 11000001dddddddd r0 (disp x 2+gbr) ? 1 ? mov.l r0,@(disp,gbr) 11000010dddddddd r0 (disp x 4+gbr) ? 1 ? mov.b @(disp,gbr),r0 11000100dddddddd (disp+gbr) sign extension r0 ? 1 ? mov.w @(disp,gbr),r0 11000101dddddddd (disp x 2+gbr) sign extension r0 ? 1 ? mov.l @(disp,gbr),r0 11000110dddddddd (disp x 4+gbr) r0 ? 1 ? mova @(disp,pc),r0 11000111dddddddd disp x 4+pc r0 ? 1 ? movt rn 0000nnnn00101001 t rn ? 1 ? swap.b rm,rn 0110nnnnmmmm1000 rm swap lowest two bytes rn ? 1 ? swap.w rm,rn 0110nnnnmmmm1001 rm swap two consecutive words rn ? 1 ? xtrct rm,rn 0010nnnnmmmm1101 rm: middle 32 bits of rn rn ? 1 ? section 2 cpu rev. 3.00 jan. 18, 2008 page 69 of 1458 rej09b0033-0300 table 2.7 arithmetic operation instructions instruction instruction code operation privileged mode cycles t bit add rm,rn 0011nnnnmmmm1100 rn+rm rn ? 1 ? add #imm,rn 0111nnnniiiiiiii rn+imm rn ? 1 ? addc rm,rn 0011nnnnmmmm1110 rn+rm+t rn, carry t ? 1 carry addv rm,rn 0011nnnnmmmm1111 rn+rm rn, overflow t ? 1 overflow cmp/eq #imm,r0 10001000iiiiiiii if r0 = imm, 1 t ? 1 comparison result cmp/eq rm,rn 0011nnnnmmmm0000 if rn = rm, 1 t ? 1 comparison result cmp/hs rm,rn 0011nnnnmmmm0010 if rn rm with unsigned data, 1 t ? 1 comparison result cmp/ge rm,rn 0011nnnnmmmm0011 if rn rm with signed data, 1 t ? 1 comparison result cmp/hi rm,rn 0011nnnnmmmm0110 if rn > rm with unsigned data, 1 t ? 1 comparison result cmp/gt rm,rn 0011nnnnmmmm0111 if rn > rm with signed data, 1 t ? 1 comparison result cmp/pl rn 0100nnnn00010101 if rn 0, 1 t ? 1 comparison result cmp/pz rn 0100nnnn00010001 if rn > 0, 1 t ? 1 comparison result cmp/str rm,rn 0010nnnnmmmm1100 if rn and rm have an equivalent byte, 1 t ? 1 comparison result div1 rm,rn 0011nnnnmmmm0100 single-step division (rn/rm) ? 1 calculatio n result div0s rm,rn 0010nnnnmmmm0111 msb of rn q, msb of rm m, m ^ q t ? 1 calculatio n result div0u 0000000000011001 0 m/q/t ? 1 0 dmuls.l rm,rn 0011nnnnmmmm1101 signed operation of rn rm mach, macl 32 32 64 bits ? 2 (to 5) * ? dmulu.l rm,rn 0011nnnnmmmm0101 unsigned operation of rn rm mach, macl 32 32 64 bits ? 2 (to 5) * ? dt rn 0100nnnn00010000 rn ? 1 rn, if rn = 0, 1 t, else 0 t ? 1 comparison result section 2 cpu rev. 3.00 jan. 18, 2008 page 70 of 1458 rej09b0033-0300 instruction instruction code operation privileged mode cycles t bit exts.b rm,rn 0110nnnnmmmm1110 a byte in rm is sign-extended rn ? 1 ? exts.w rm,rn 0110nnnnmmmm1111 a word in rm is sign-extended rn ? 1 ? extu.b rm,rn 0110nnnnmmmm1100 a byte in rm is zero-extended rn ? 1 ? extu.w rm,rn 0110nnnnmmmm1101 a word in rm is zero- extended rn ? 1 ? mac.l @rm+, @rn+ 0000nnnnmmmm1111 signed operation of (rn) (rm) + mac mac, rn + 4 rn, rm + 4 rm 32 32 + 64 64 bits ? 2 (to 5) * ? mac.w @rm+, @rn+ 0100nnnnmmmm1111 signed operation of (rn) (rm) + mac mac, rn + 2 rn, rm + 2 rm 16 16 + 64 64 bits ? 2 (to 5) * ? mul.l rm,rn 0000nnnnmmmm0111 rn rm macl 32 32 32 bits ? 2 (to 5) * ? muls.w rm,rn 0010nnnnmmmm1111 signed operation of rn rm macl 16 16 32 bits ? 1( to 3) * ? mulu.w rm,rn 0010nnnnmmmm1110 unsigned operation of rn rm macl 16 16 32 bits ? 1(to 3) * ? neg rm,rn 0110nnnnmmmm1011 0?rm rn ? 1 ? negc rm,rn 0110nnnnmmmm1010 0?rm?t rn, borrow t ? 1 borrow sub rm,rn 0011nnnnmmmm1000 rn?rm rn ? 1 ? subc rm,rn 0011nnnnmmmm1010 rn?rm?t rn, borrow t ? 1 borrow subv rm,rn 0011nnnnmmmm1011 rn?rm rn, underflow t ? 1 underflow note: * the number of execution cycl es indicated within the parent heses ( ) are required when the operation result is read from the ma ch/macl register immediately after the instruction. section 2 cpu rev. 3.00 jan. 18, 2008 page 71 of 1458 rej09b0033-0300 table 2.8 logic operation instructions instruction instruction code operation privileged mode cycles t bit and rm,rn 0010nnnnmmmm1001 rn & rm rn ? 1 ? and #imm,r0 11001001iiiiiiii r0 & imm r0 ? 1 ? and.b #imm,@(r0, gbr) 11001101iiiiiiii (r0+gbr) & imm (r0+gbr) ? 3 ? not rm,rn 0110nnnnmmmm0111 rm rn ? 1 ? or rm,rn 0010nnnnmmmm1011 rn | rm rn ? 1 ? or #imm,r0 11001011iiiiiiii r0 | imm r0 ? 1 ? or.b #imm,@(r0, gbr) 11001111iiiiiiii (r0+gbr) | imm (r0+gbr) ? 3 ? tas.b @rn 0100nnnn00011011 if (rn) is 0, 1 t; 1 msb of (rn) ? 4 test result tst rm,rn 0010nnnnmmmm1000 rn & rm; if the result is 0, 1 t? 1 test result tst #imm,r0 11001000iiiiiiii r0 & imm; if the result is 0, 1 t ? 1 test result tst.b #imm,@(r0, gbr) 11001100iiiiiiii (r0 + gbr) & imm; if the result is 0, 1 t ? 3 test result xor rm,rn 0010nnnnmmmm1010 rn ^ rm rn ? 1 ? xor #imm,r0 11001010iiiiiiii r0 ^ imm r0 ? 1 ? xor.b #imm,@(r0, gbr) 11001110iiiiiiii (r0+gbr) ^ imm (r0+gbr) ? 3 ? section 2 cpu rev. 3.00 jan. 18, 2008 page 72 of 1458 rej09b0033-0300 table 2.9 shift instructions instruction instruction code operation privileged mode cycles t bit rotl rn 0100nnnn00000100 t rn msb ? 1 msb rotr rn 0100nnnn00000101 lsb rn t ? 1 lsb rotcl rn 0100nnnn00100100 t rn t ? 1 msb rotcr rn 0100nnnn00100101 t rn t ? 1 lsb shad rm, rn 0100nnnnmmmm1100 rn 0: rn << rm rn rn < 0: rn >> rm [msb rn] ? 1 ? shal rn 0100nnnn00100000 t rn 0 ? 1 msb shar rn 0100nnnn00100001 msb rn t ? 1 lsb shld rm, rn 0100nnnnmmmm1101 rm 0: rn << rm rn rm < 0: rn >> rm [0 rn] ? 1 ? shll rn 0100nnnn00000000 t rn 0 ? 1 msb shlr rn 0100nnnn00000001 0 rn t ? 1 lsb shll2 rn 0100nnnn00001000 rn<<2 rn ? 1 ? shlr2 rn 0100nnnn00001001 rn>>2 rn ? 1 ? shll8 rn 0100nnnn00011000 rn<<8 rn ? 1 ? shlr8 rn 0100nnnn00011001 rn>>8 rn ? 1 ? shll16 rn 0100nnnn00101000 rn<<16 rn ? 1 ? shlr16 rn 0100nnnn00101001 rn>>16 rn ? 1 ? section 2 cpu rev. 3.00 jan. 18, 2008 page 73 of 1458 rej09b0033-0300 table 2.10 branch instructions instruction instruction code operation privilege d mode cycle s t bit bf disp 10001011dddddddd if t = 0, disp 2 + pc pc; if t = 1, nop ? 3/1 * ? bf/s disp 10001111dddddddd delayed branch, if t = 0, disp 2 + pc pc; if t = 1, nop ? 2/1 * ? bt disp 10001001dddddddd if t = 1, disp 2 + pc pc; if t = 0, nop ? 3/1 * ? bt/s disp 10001101dddddddd delayed branch, if t = 1, disp 2 + pc pc; if t = 0, nop ? 2/1 * ? bra disp 1010dddddddddddd delayed branch, disp 2 + pc pc ? 2 ? braf rm 0000mmmm00100011 delayed branch,rm + pc pc ? 2 ? bsr disp 1011dddddddddddd delayed branch, pc pr, disp 2 + pc pc ? 2 ? bsrf rm 0000mmmm00000011 delayed branch, pc pr, rm + pc pc ? 2 ? jmp @rm 0100mmmm00101011 delayed branch, rm pc ? 2 ? jsr @rm 0100mmmm00001011 delayed branch, pc pr, rm pc ? 2 ? rts 0000000000001011 delayed branch, pr pc ? 2 ? note: * one state when the br anch is not executed. section 2 cpu rev. 3.00 jan. 18, 2008 page 74 of 1458 rej09b0033-0300 table 2.11 system control instructions instruction instruction code operation privileged mode cycles t bit clrma c 0000000000101000 0 mach,macl ? 1 ? clrs 0000000001001000 0 s ? 1 ? clrt 0000000000001000 0 t ? 1 0 ldc rm,sr 0100mmmm00001110 rm sr 6 lsb ldc rm,gbr 0100mmmm00011110 rm gbr ? 4 ? ldc rm,vbr 0100mmmm00101110 rm vbr 4 ? ldc rm,ssr 0100mmmm00111110 rm ssr 4 ? ldc rm,spc 0100mmmm01001110 rm spc 4 ? ldc rm,r0_bank 0100mmmm10001110 rm r0_bank 4 ? ldc rm,r1_bank 0100mmmm10011110 rm r1_bank 4 ? ldc rm,r2_bank 0100mmmm10101110 rm r2_bank 4 ? ldc rm,r3_bank 0100mmmm10111110 rm r3_bank 4 ? ldc rm,r4_bank 0100mmmm11001110 rm r4_bank 4 ? ldc rm,r5_bank 0100mmmm11011110 rm r5_bank 4 ? ldc rm,r6_bank 0100mmmm11101110 rm r6_bank 4 ? ldc rm,r7_bank 0100mmmm11111110 rm r7_bank 4 ? ldc.l @rm+,sr 0100mmmm00000111 (rm) sr, rm+4 rm 8 lsb ldc.l @rm+,gbr 0100mmmm00010111 (rm) gbr, rm+4 rm ? 4 ? ldc.l @rm+,vbr 0100mmmm00100111 (rm) vbr, rm+4 rm 4 ? ldc.l @rm+,ssr 0100mmmm00110111 (rm) ssr,rm+4 rm 4 ? ldc.l @rm+,spc 0100mmmm01000111 (rm) spc,rm+4 rm 4 ? ldc.l @rm+, r0_bank 0100mmmm10000111 (rm) r0_bank,rm+4 rm 4 ? ldc.l @rm+, r1_bank 0100mmmm10010111 (rm) r1_bank,rm+4 rm 4 ? ldc.l @rm+, r2_bank 0100mmmm10100111 (rm) r2_bank,rm+4 rm 4 ? ldc.l @rm+, r3_bank 0100mmmm10110111 (rm) r3_bank, rm+4 rm 4 ? ldc.l @rm+, r4_bank 0100mmmm11000111 (rm) r4_bank, rm+4 rm 4 ? section 2 cpu rev. 3.00 jan. 18, 2008 page 75 of 1458 rej09b0033-0300 instruction instruction code operation privileged mode cycles t bit ldc.l @rm+, r5_bank 0100mmmm11010111 (rm) r5_bank, rm+4 rm 4 ? ldc.l @rm+, r6_bank 0100mmmm11100111 (rm) r6_bank, rm+4 rm 4 ? ldc.l @rm+, r7_bank 0100mmmm11110111 (rm) r7_bank, rm+4 rm 4 ? lds rm,mach 0100mmmm00001010 rm mach ? 1 ? lds rm,macl 0100mmmm00011010 rm macl ? 1 ? lds rm,pr 0100mmmm00101010 rm pr ? 1 ? lds.l @rm+,mach 0100mmmm00000110 (rm) mach, rm+4 rm ? 1 ? lds.l @rm+,macl 0100mmmm00010110 (rm) macl, rm+4 rm ? 1 ? lds.l @rm+,pr 0100mmmm00100110 (rm) pr, rm+4 rm ? 1 ? ldtlb 0000000000111000 pteh/ptel tlb 1 ? nop 0000000000001001 no operation ? 1 ? pref @rm 0000mmmm10000011 (rm) cache ? 1 ? rte 0000000000101011 delayed branch, ssr sr, spc pc 5 ? sets 0000000001011000 1 s ? 1 ? sett 0000000000011000 1 t ? 1 1 sleep 0000000000011011 sleep 4 * 1 ? stc sr,rn 0000nnnn00000010 sr rn 1 ? stc gbr,rn 0000nnnn00010010 gbr rn ? 1 ? stc vbr,rn 0000nnnn00100010 vbr rn 1 ? stc ssr, rn 0000nnnn00110010 ssr rn 1 ? stc spc,rn 0000nnnn01000010 spc rn 1 ? stc r0_bank,rn 0000nnnn10000010 r0_bank rn 1 ? stc r1_bank,rn 0000nnnn10010010 r1_bank rn 1 ? stc r2_bank,rn 0000nnnn10100010 r2_bank rn 1 ? stc r3_bank,rn 0000nnnn10110010 r3_bank rn 1 ? stc r4_bank,rn 0000nnnn11000010 r4_bank rn 1 ? stc r5_bank,rn 0000nnnn11010010 r5_bank rn 1 ? stc r6_bank,rn 0000nnnn11100010 r6_bank rn 1 ? section 2 cpu rev. 3.00 jan. 18, 2008 page 76 of 1458 rej09b0033-0300 instruction instruction code operation privileged mode cycles t bit stc r7_bank,rn 0000nnnn11110010 r7_bank rn 1 ? stc.l sr,@?rn 0100nnnn00000011 rn?4 rn, sr (rn) 1 ? stc.l gbr,@?rn 0100nnnn00010011 rn?4 rn, gbr (rn) ? 1 ? stc.l vbr,@?rn 0100nnnn00100011 rn?4 rn, vbr (rn) 1 ? stc.l ssr,@?rn 0100nnnn00110011 rn?4 rn, ssr (rn) 1 ? stc.l spc,@?rn 0100nnnn01000011 rn?4 rn, spc (rn) 1 ? stc.l r0_bank,@?rn 0100nnnn10000011 rn?4 rn, r0_bank (rn) 1 ? stc.l r1_bank,@?rn 0100nnnn10010011 rn?4 rn, r1_bank (rn) 1 ? stc.l r2_bank,@?rn 0100nnnn10100011 rn?4 rn, r2_bank (rn) 1 ? stc.l r3_bank,@?rn 0100nnnn10110011 rn?4 rn, r3_bank (rn) 1 ? stc.l r4_bank,@?rn 0100nnnn11000011 rn?4 rn, r4_bank (rn) 1 ? stc.l r5_bank,@?rn 0100nnnn11010011 rn?4 rn, r5_bank (rn) 1 ? stc.l r6_bank,@?rn 0100nnnn11100011 rn?4 rn, r6_bank (rn) 1 ? stc.l r7_bank,@?rn 0100nnnn11110011 rn?4 rn, r7_bank (rn) 1 ? sts mach,rn 0000nnnn00001010 mach rn ? 1 ? sts macl,rn 0000nnnn00011010 macl rn ? 1 ? sts pr,rn 0000nnnn00101010 pr rn ? 1 ? sts.l mach,@?rn 0100nnnn00000010 rn?4 rn, mach (rn) ? 1 ? sts.l macl,@?rn 0100nnnn00010010 rn?4 rn, macl (rn) ? 1 ? sts.l pr,@?rn 0100nnnn00100010 rn?4 rn, pr (rn) ? 1 ? trapa #imm 11000011iiiiiiii unconditional trap exception occurs * 2 ? 8 ? notes: the table shows the minimum number of clocks required for execution. in practice, the number of execution cycles will be incr eased in the follo wing conditions. a. if there is a conflict between an instruction fetch and a data access b. if the destination register of a load instruction (memory register) is also used by the following instruction. for addressing modes with displacement (disp) as shown below, the assembler description in this manual indicates the val ue before it is scaled (x 1, x 2, or x 4) according to the operand size to clarify the lsi operation. for details on assembler description, refer to the descrip tion rules in each assembler. @ (disp:4, rn) ; register indirect with displacement @ (disp:8, gbr) ; gbr indirect with displacement @ (disp:8, pc) ; pc re lative with displacement disp:8, disp:12 ; pc relative section 2 cpu rev. 3.00 jan. 18, 2008 page 77 of 1458 rej09b0033-0300 1. number of states before t he chip enters the sleep state. 2. for details, refer to section 7, exception handling. 2.6.2 operation code map table 2.12 shows the operation code map. table 2.12 operation code map instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0000 rn fx 0000 0000 rn fx 0001 0000 rn 00md 0010 stc sr, rn stc gbr, rn stc vbr, rn stc ssr, rn 0000 rn 01md 0010 stc spc, rn 0000 rn 10md 0010 stc r0_bank, rn stc r1_bank, rn stc r2_bank, rn stc r3_bank, rn 0000 rn 11md 0010 stc r4_bank, rn stc r5_bank, rn stc r6_bank, rn stc r7_bank, rn 0000 rm 00md 0011 bsrf rm bra rm 0000 rm 10md 0011 pref @rm 0000 rn rm 01md mov.b rm, @(r0, rn) mov.w rm, @(r0, rn) mov.l rm,@(r0, rn) mul.l rm, rn 0000 0000 00md 1000 clrt sett clrmac ldtlb 0000 0000 01md 1000 clrs sets 0000 0000 fx 1001 nop div0u 0000 0000 fx 1010 0000 0000 fx 1011 rts sleep rte 0000 rn fx 1000 0000 rn fx 1001 movt rn 0000 rn fx 1010 sts mach, rn sts macl, rn sts pr, rn 0000 rn fx 1011 0000 rn rm 11md mov. b @(r0, rm), rn mov.w @(r0 , rm), rn mov.l @(r0, rm), rn mac.l @rm+,@rn+ 0001 rn rm disp mov.l rm, @(disp:4, rn) 0010 rn rm 00md mov.b rm, @rn mov.w rm, @rn mov.l rm, @rn 0010 rn rm 01md mov.b rm, @?rn mov.w rm , @?rn mov.l rm, @?rn div0s rm, rn 0010 rn rm 10md tst rm, rn and rm, rn xor rm, rn or rm, rn section 2 cpu rev. 3.00 jan. 18, 2008 page 78 of 1458 rej09b0033-0300 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0010 rn rm 11md cmp/str rm, rn xtrct rm, rn mulu.w rm, rn mulsw rm, rn 0011 rn rm 00md cmp/eq rm, rn cmp/hs rm, rn cmp/ge rm, rn 0011 rn rm 01md div1 rm, rn dmulu.l rm,rn cmp/hi rm, rn cmp/gt rm, rn 0011 rn rm 10md sub rm, rn subc rm, rn subv rm, rn 0011 rn rm 11md add rm, rn dmuls.l rm,rn addc rm, rn addv rm, rn 0100 rn fx 0000 shll rn dt rn shal rn 0100 rn fx 0001 shlr rn cmp/pz rn shar rn 0100 rn fx 0010 sts.l mach, @?rn sts.l macl, @?rn sts.l pr, @?rn 0100 rn 00md 0011 stc.l sr, @?rn stc.l gbr, @?rn stc.l vbr, @?rn stc.l ssr, @?rn 0100 rn 01md 0011 stc.l spc, @?rn 0100 rn 10md 0011 stc.l r0_bank, @?rn stc.l r1_bank, @?rn stc.l r2_bank, @?rn stc.l r3_bank, @?rn 0100 rn 11md 0011 stc.l r4_bank, @?rn stc.l r5_bank, @?rn stc.l r6_bank, @?rn stc.l r7_bank, @?rn 0100 rn fx 0100 rotl rn rotcl rn 0100 rn fx 0101 rotr rn cmp/pl rn rotcr rn 0100 rm fx 0110 lds.l @rm+, mach lds.l @rm+, macl lds.l @rm+, pr 0100 rm 00md 0111 ldc.l @rm+, sr ldc.l @rm+, gbr ldc.l @rm+, vbr ldc.l @rm+, ssr 0100 rm 01md 0111 ldc.l @rm+, spc 0100 rm 10md 0111 ldc.l @rm+, r0_bank ldc.l @rm+, r1_bank ldc.l @rm+, r2_bank ldc.l @rm+, r3_bank 0100 rm 11md 0111 ldc.l @rm+, r4_bank ldc.l @rm+, r5_bank ldc.l @rm+, r6_bank ldc.l @rm+, r7_bank 0100 rn fx 1000 shll2 rn shll8 rn shll16 rn 0100 rn fx 1001 shlr2 rn shlr8 rn shlr16 rn 0100 rm fx 1010 lds rm, mach lds rm, macl lds rm, pr 0100 rm/ rn fx 1011 jsr @rm tas.b @rn jmp @rm 0100 rn rm 1100 shad rm, rn 0100 rn rm 1101 shld rm, rn section 2 cpu rev. 3.00 jan. 18, 2008 page 79 of 1458 rej09b0033-0300 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0100 rm 00md 1110 ldc rm, sr ldc rm, gbr ldc rm, vbr ldc rm, ssr 0100 rm 01md 1110 ldc rm, spc 0100 rm 10md 1110 ldc rm, r0_bank ldc rm, r1_bank ldc rm, r2_bank ldc rm, r3_bank 0100 rm 11md 1110 ldc rm, r4_bank ldc rm, r5_bank ldc rm, r6_bank ldc rm, r7_bank 0100 rn rm 1111 mac.w @rm+, @rn+ 0101 rn rm disp mov.l @(disp:4, rm), rn 0110 rn rm 00md mov.b @rm, rn mov.w @rm, rn mov.l @rm, rn mov rm, rn 0110 rn rm 01md mov.b @rm+, rn mov.w @rm+, rn mov.l @rm+, rn not rm, rn 0110 rn rm 10md swap.b rm, rn swap.w rm, rn negc rm, rn neg rm, rn 0110 rn rm 11md extu.b rm, rn extu.w rm, rn exts.b rm, rn exts.w rm, rn 0111 rn imm add # imm : 8, rn 1000 00md rn disp mov. b r0, @(disp: 4, rn) mov. w r0, @(disp: 4, rn) 1000 01md rm disp mov.b @(disp:4, rm), r0 mov.w @(disp: 4, rm), r0 1000 10md imm/disp cmp/eq #imm:8, r0 bt disp: 8 bf disp: 8 1000 11md imm/disp bt/s disp: 8 bf/s disp: 8 1001 rn disp mov.w @(disp : 8, pc), rn 1010 disp bra disp: 12 1011 disp bsr disp: 12 1100 00md imm/disp mov.b r0, @(disp: 8, gbr) mov.w r0, @(disp: 8, gbr) mov.l r0, @(disp: 8, gbr) trapa #imm: 8 1100 01md disp mov.b @(disp: 8, gbr), r0 mov.w @(disp: 8, gbr), r0 mov.l @(disp: 8, gbr), r0 mova @(disp: 8, pc), r0 1100 10md imm tst #imm: 8, r0 and #imm: 8, r0 xor #imm: 8, r0 or #imm: 8, r0 1100 11md imm tst.b #imm: 8, @(r0, gbr) and.b #imm: 8, @(r0, gbr) xor.b #imm: 8, @(r0, gbr) or.b #imm: 8, @(r0, gbr) 1101 rn disp mov.l @(disp: 8, pc), rn 1110 rn imm mov #imm:8, rn 1111 ************ note: for details, refer to the sh -3/sh-3h/sh3-dsp software manual. section 2 cpu rev. 3.00 jan. 18, 2008 page 80 of 1458 rej09b0033-0300 section 3 dsp operating unit dsps301s_010020030200 rev. 3.00 jan. 18, 2008 page 81 of 1458 rej09b0033-0300 section 3 dsp operating unit 3.1 dsp extended functions this lsi incorporates a dsp unit and x/y memory directly connected to the dsp unit. this lsi supports the dsp extended function instruction sets needed to control the dsp unit and x/y memory. the dsp extended function instructions are classified into four groups. (1) extended system contro l instructions for the cpu if the dsp extended function is enabled, the following extended system control instructions can be used for the cpu. ? repeat loop control instructions and repeat loop control regist er access instructions are added. looped programs can be executed efficiently by using the zero-overhead repeat control unit. for details, refer to section 3.3, cpu extended instructions. ? modulo addressing control inst ructions and control register access instructions are added. function allows access to data with a circular st ructure. for details, refer to section 3.4, dsp data transfer instructions. ? dsp unit register access instructions are added. so me of the dsp unit registers can be used in the same way as the cpu system registers. for de tails, refer to section 3.4, dsp data transfer instructions. (2) data transfer instructio ns for data transfers between dsp unit and on-chip x/y memory data transfer instructions for data transfers between the dsp unit and on-chip x/y memory are called double-data transfer instructions. instructio n codes for these double-transfer instructions are 16 bit codes as well as cpu instruction codes. these data transfer instructions perform data transfers between the dsp unit an d on-chip x/y memory that is directly connected to the dsp unit. these data transfer instructions can be described in combination with other dsp unit operation instructions. for details, refer to section 3.4, dsp data transfer instructions. (3) data transfer instructio ns for data transfers between dsp unit registers and all virtual address spaces data transfer instructions for data transfers be tween dsp unit registers and all virtual address spaces are called single-data transfer instructi ons. instruction codes fo r the double-transfer instructions are 16 bit codes as well as cpu inst ruction codes. these data transfer instructions section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 82 of 1458 rej09b0033-0300 performs data transfers between the dsp unit registers and all vi rtual address spaces. for details, refer to section 3.4, dsp data transfer instructions. (4) dsp unit operation instructions dsp unit operation instructions are called dsp data operation instructions. these instructions are provided to execute digital signal processing operations at high speed using the dsp. instruction codes for these instructions are 32 bits. the dsp data operation instruction fields consist of two fields: field a and field b. in field a, a function for double data transfer instructions can be described. in field b, alu operation instructions and multiply instructions can be described. the instructions described in fields a and b can be executed in parallel. a maximum of four instructions (alu operation, multiply, and two data transfers) can be executed in parallel. for details, refer to section 3.5, dsp data operation instructions. notes: 1. 32-bit instruction codes are handled as two consecutive 16-bi t instruction codes. accordingly, 32-bit instruction codes can be assigned to a word boundary. 32-bit instruction codes must be stored in memory, upper word and lower word, in this order, in word units. 2. in little endian, the upper and lower words must be stored in memory as data to be accessed in word units. cpu core instruction 15 0000 1110 111100 111101 111110 a field a field a field b field 0 15 0 15 10 10 9 12 11 90 31 16 26 25 0 15 double-data transfer instruction single-data transfer instruction dsp data operation instruction - * figure 3.1 dsp instruction format section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 83 of 1458 rej09b0033-0300 3.2 dsp mode resources 3.2.1 processing modes the cpu processing modes can be extended using the mode bit (md) and dsp bit (dsp) in the status register (sr), as shown below. table 3.1 cpu processing modes description md dsp processing mode access of resources protected in privileged mode or privileged instruction execution dsp extended functions 0 0 user mode prohibited invalid 0 1 user dsp mode prohibited valid 1 0 privileged mode allowed invalid 1 1 privileged dsp mode allowed valid as shown above, the extension of the dsp function by the dsp bit can be specified independently of the control by the md bit. note, however, that the dsp bit can be modified only in privileged mode. before the dsp bit is modified, a transition to privileged mode or privileged dsp mode is necessary. 3.2.2 dsp mode memory map in dsp mode, a part of the p2 area in the virtua l address space can be accessed in user dsp mode. when this area is accessed in user dsp mode, this area is referred to as a uxy area. x/y memory is then assigned to this uxy area. accordingly, x/y memory can also be accessed in user dsp mode. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 84 of 1458 rej09b0033-0300 table 3.2 virtual address space address range name protection description h'a5000000 to h'a5ffff ff p2/uxy privileged or dsp 16-mbyte physical address space, non-cacheable, non-address translatable can be accessed in privileged mode, privileged dsp mode, and user dsp mode 3.2.3 cpu register sets in dsp mode, the status register (sr) in the cpu unit is extended to add control bits and three control registers: a repeat start register (sr), repeat end register (re), and modulo register (mod) are added as cont rol registers. 31 31 31 31 16 15 0 0 0 30292827 161514131211109876543210 0 md rb bl rc[11:0] 0 0 0 dsp dmy dmx m q i3 i2 i1 i0 rf1 rf0 s t me ms rs re repeat start register (rs) status register (sr) repeat end register (re) modulo register (mod) figure 3.2 cpu registers in dsp mode section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 85 of 1458 rej09b0033-0300 (1) extension of status register (sr) in dsp mode, the following control bits are added to the status register (sr). these added bits are called dsp extension bits. these dsp extension bits are valid only in dsp mode. bit bit name initial value r/w description 31 to 28 ? ? ? for details, refer to section 2, cpu. 27 to 16 rc11 to rc0 all 0 r/w repeat counter holds the number of repeat times in order to perform loop control, and can be modified in privileged mode, privileged dsp mode, or user dsp mode. at reset, this bit is initialized to 0. this bit is not affected in the exception handling state. 15 to 13 ? ? ? for details, refer to section 2, cpu. 12 dsp 0 r/w dsp bit enables or disables the dsp extended functions. if this bit is set to 1, the dsp extended functions are enabled. this bit can be modified in privileged mode, privileged dsp mode, or user dsp mode. at reset, this bit is initialized to 0. this bit is not affected in the exception handling state. 11 10 mdy mdx 0 0 r/w r/w modulo control bits enable or disable modulo addressing for x/y memory access. these bits can be modified in privileged mode, privileged dsp mode, or user dsp mode. at reset, these bits are initialized to 0. these bits are affected in the exception handling state. 9 to 4 ? ? ? for details, refer to section 2, cpu. 3 2 fr1 fr0 0 0 r/w r/w repeat flag bits used by repeat control instructions. these bits can be modified in privileged mode, privileged dsp mode, or user dsp mode. at reset, these bits are initialized to 0. these bits are affected in the exception handling state. 1, 0 ? ? ? for details, refer to section 2, cpu. note: when data is written to the sr register, 0 sh ould be written to bits t hat are specified as 0. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 86 of 1458 rej09b0033-0300 (2) repeat start register (rs) the repeat start register (rs) holds the start address of a loop rep eat module that is controlled by the repeat function. this register can be accessed in dsp mode. at reset, the initial value of this register is undefined. this register is not affected in the exception handling state. (3) repeat end register (re) the repeat end register (re) holds the end address of a loop repeat module that is controlled by the repeat function. this register can be accessed in dsp mode. at reset, this register is initialized to 0. this register is not affected in the exception handling state. (4) modulo register (mod) the modulo register stores the modulo end address and modulo start address for modulo addressing in upper and lower 16 bits. the upper and lower 16 bits of the modulo register are referred to as the me register an d ms register, respectively. this register can be accessed in dsp mode. at reset, the initial value of this register is undefined. this register is not affected in the exception handling state. the above registers can be accessed by the control register load instruction (ldc) and store instruction (stc). note that the ldc and stc instructions for the rs, re, and mod registers can be used only in privileged dsp mode and user dsp mode. the ldc and stc instruction for the sr register can be executed only when the md bit is set to 1 or in user dsp mode. note, however, that the ldc and stc instructions can modify only the rc11 to rc0, rf1 to rf0, dmx, and dmy bits in the sr, as described below. ? in user mode, if the lcd and stc instructions are used for the rs, an illegal instruction exception occurs. ? in privileged and privileged dsp modes, all sr bits can be modified. ? in user dsp mode, the sr can be read by the stc instruction. ? in user dsp mode, the ldc instruction can be issued to the sr but only the dsp extension bits can be modified. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 87 of 1458 rej09b0033-0300 table 3.3 operation of sr bits in each processing mode privileged mode user mode privileged dsp mode user dsp mode field md = 1 & dsp = 0 md = 0 & dsp = 0 md = 1 & dsp = 1 md = 0 & dsp = 1 access to dsp-related bit with dedicated instruction initial value after reset md s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng 1 rb s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng 1 bl s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng 1 rc [11:0] s: ok, l: ok s, l: invalid instruction s: ok, l: ok r: ok, l: ok setrc instruction 000000000000 dsp s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng 0 dmy s: ok, l: ok s, l: invalid instruction s: ok, l: ok r: ok, l: ok 0 dmx s: ok, l: ok s, l: invalid instruction s: ok, l: ok r: ok, l: ok 0 q s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng x m s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng x i[3:0] s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng 1111 rf[1:0] s: ok, l: ok s, l: invalid instruction s: ok, l: ok r: ok, l: ok setrc instruction x s s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng x t s: ok, l: ok s, l: invalid instruction s: ok, l: ok s: ok, l: ng x [legend] s: stc instruction l: ldc instruction ok: stc/ldc operation is enabled. invalid instruction: exception occurs w hen an invalid instruction is executed. ng: previous value is retained. no change. x: undefined section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 88 of 1458 rej09b0033-0300 before entering the exception handling state, all bits including the dsp extension bits of the sr registers are saved in the ssr. before returning from the exception handling, all bits including the dsp extension bits of the sr must be restored. if the repeat control must be recovered before entering the exception hand ling state, the rs and re registers mu st be recovered to the value that existed before exception handling. in addition, if it is necessary to recover modulo control before entering the exception handling st ate, the mod register must be recovered to the value that existed before exception handling. 3.2.4 dsp registers the dsp unit incorporates eight data registers (a 0, a1, x0, x1, y0, y1, m0 , and m1) and a status register (dsr). figure 3.3 shows the dsp register configuration. these are 32-bit width registers with the exception of registers a0 and a1. registers a0 and a1 include 8 guard bits (fields a0g and a1g), giving them a total width of 40 bits. the dsr register stores the dsp data operation result (zero, negative, others). the dsp register has a dc bit whose function is similar to the t bit in the cpu register. for details on dsr bits, refer to section 3.5, dsp data operation instructions. 39 a0g a1g a0 a1 m0 m1 x0 x1 y0 y1 ................ gt v n z cs[2:0] dc (a) dsp data registers (b) dsp status register (dsr) 32 31 0 31 876543 1 0 initial value dsr : all 0 others: undefined figure 3.3 dsp register configuration section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 89 of 1458 rej09b0033-0300 3.3 cpu extended instructions 3.3.1 dsp repeat control in dsp mode, a specific function is provided to ex ecute repeat loops effici ently. by using this function, loop programs can be executed without overhead caused by the compare and branch instructions. (1) examples of repeat loop programs examples of repeat loop programs are shown below. ? example 1: repeat loop consisting of 4 or more instructions ldrs rptstart ; sets repeat start instruction address to the rs register ldre rptdtct +4 ; sets (repeat detection instruction address + 4) to the re register setrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register instr0 ; at least one instruction is required from setrc instruction to [repeat start instruction] rptstart: instr1 ; [repeat start instruction] ... ... ; ... ... ; rptdtct: instr(n-3) ;three instruction prior to the repeat end instruction is regarded as repeat detection instruction rptend2: instr(n-2) ; rptend1: instr(n-1) ; rptend: instrn ; [repeat end instruction] in the above program example, instructions from the rptstart address (instr1 instruction) to the rptend address (instrn instructi on) are repeated four times. thes e repeated instructions in the program are called repeat loop. the start and end instructions of the repe at loop are called the repeat start instruction and repeat end instruct ion, respectively. the cpu sequentially executes instructions and starts repeat loop control if the cpu detects the completion of a specific instruction. this specific instruction is called the repeat detection instruction. in a repeat loop consisting of four or more instructions, an instru ction three instructions prior to the repeat end instruction is regarded as the repeat detection instruction. in a repeat loop consisting of four or section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 90 of 1458 rej09b0033-0300 more instructions, the same instruction is rega rded as the rptstart instruction and rptdtct instruction. to control the repeat loop, the dsp extended cont rol registers, such as the re register and rs register and the rc[11:0] and rf[1:0] bits of th e sr register, are used. these registers can be specified by the ldre, ldrs, and setrc instructions. ? repeat end register (re) the re register is specified by the ldre in struction. the re register specifies (repeat detection instruction address +4). in a repeat loop consisting of four or more instructions, an instruction three instructions prior to the repe at end instruction is re garded as the repeat detection instruction. a repeat loop consisting of three or less instructions is described later. ? repeat start register (rs) the re register is specified by the ldrs instruc tion. in a repeat loop consisting of 4 or more instructions, the rs register sp ecifies the repeat start instruct ion address. in a repeat loop consisting of three or less instructions, a specif ic address is specified in the rs. this is described later. ? repeat counter (rc[11:0] bits of the sr) the repeat counter is specifies the number of repetitions by the setrc instruction. during repeat loop execution, the rc holds the remaining number of repetitions. ? repeat flags (rf[1:0] bits of the sr) the repeat flags are automatically specified according to the rs and re register values during setrc instruction execution. the repeat flags store information on the number of instructions included in the repeat loop. normally, the us er cannot modify the repeat flag values. the cpu always executes instructions by comparing the re register to program counter values. because the pc stores (the curren t instruction address +4), if the re matches the pc during repeat instruction detection execution, a repeat detection instruction can be detected. if a repeat detection instruction is executed without branching and if rc[11:0] > 0, then repeat control is performed. if rc[11:0] 2 when the repeat end instruction is completed, the rc[11:0] is decremented by 1 and then control is passed to the addr ess specified by the rs register. examples 2 to 4 show program examples of the repeat loop consisting of three instructions, two instructions, and one instruction, respectively. in these examples, an instruction immediately prior to the repeat start instruction is regarded as a rep eat detection instru ction. the rs re gister specifies the specific value that indicates th e number of repeat instructions. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 91 of 1458 rej09b0033-0300 ? example 2: repeat loop consisting of three instructions ldrs rptdtct +4 ; sets (repeat detection instruction address + 4) to the rs register ldre rptdtct +4 ; sets (repeat detection instruction address + 4) to the re register setrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register ; if re-rs==0 during setrc instruction execution, the repeat loop is regarded as three-instruction repeat. rptdtct: instr0 ; an instruction prior to the repeat start instruction is regarded as a repeat detection instruction. rptstart: instr1 ; [repeat start instruction] instr2 ; rptend: instr3 ; [repeat end instruction] ? example 3: repeat loop consisting of two instructions ldrs rptdtct +6; sets (repeat detection instruction address + 6) to the rs register ldre rptdtct +4 ; sets (repeat detection instruction address + 4) to the re register setrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register ; if re-rs==-2 during setrc instruction execution, the repeat loop is regarded as two-instruction repeat. rptdtct: instr0 ; an instruction prior to the repeat start instruction is regarded as a repeat detection instruction. rptstart: instr1 ; [repeat start instruction] rptend: instr2 ; [repeat end instruction] section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 92 of 1458 rej09b0033-0300 ? example 4: repeat loop consisting of one instruction ldrs rptdtct +8; sets (repeat detection instruction address + 8) to the rs register ldre rptdtct +4 ; sets (repeat detection instruction address + 4) to the re register setrc #4 ; sets the number of repetitions (4) to the rc[11:0] bits of the sr register ; if re-rs==-4 during setrc instruction execution, the repeat loop is regarded as one-instruction repeat. rptdtct: instr0 ; an instruction prior to the repeat start instruction is regarded as a repeat detection instruction. rptstart: rptend: instr1 ; [repeat start instruction]==[repeat end instruction] in repeat loops consisting of three instructions , two instructions and on e instruction, specific addresses are specified in the rs register. re ? rs is calculated during setrc instruction execution, and the number of instructions included in the repeat loop is determined according to the result. a value of 0, ?2,and ?4 in the result correspond to three instructions, two instructions, and one instructi on, respectively. if repeat instruction execution is completed without branching and if rc[11:0] > 0, an instruction following the repeat detection instruction is regarded as a repeat start instruction and instruction execution is repeated for the nu mber of times corresponding to the recognized number of instructions. if rc[11:0] 2 when the repeat end instruction is completed, the rc[11:0] is decremented by 1 and then control is passed to the address specified by the rs register. if rc[11:0] ==1 (or 0) when the repeat end instruction is completed, the rc[11:0] is cleared to 0 and then the control is passed to the next instruction following the repeat end instruction. note: if re ? rs is a positive value, the cpu rega rds the repeat loop as a four-instruction repeat loop. (in a repeat loop consisting of four or more instructions, re ? rs is always a positive value. for details, refer to example 1 above.) if re ? rs is positive, or a value other than 0, ?2,and ?4, correct operation cannot be guaranteed. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 93 of 1458 rej09b0033-0300 table 3.4 shows the addresses to be specified in the repeat start register (rs) and repeat end register (re). table 3.4 rs and re setting rule number of instructions in repeat loop 1 2 3 4 rs rptstart0 + 8 rptstart0 + 6 rptstart0 + 4 rptstart re rptstart0 + 4 rptstart0 + 4 rptstart0 + 4 rptend3 + 4 note: the terms used above in table 3.2, are defined as follows. rptstart: address of the repeat start instruction rptstart0: address of the instruction one inst ruction prior to the r epeat start instruction rptend3: address of the instruction three inst ructions prior to the repeat end instruction (2) repeat control instructions and repeat control macros to describe a repeat loop, the rs and re regist ers must be specified ap propriately by the ldrs and ldrs instructions and then the number of repetitions must be specified by the sertc instruction. an 8-bit immediate data or a general register can be used as an operand of the setrc instruction. to specify the rc as a value greater than 256, use setrc rm type instructions. table 3.5 repeat control instructions instruction operation number of execution states ldrs @(disp,pc) calculates (disp x 2 + pc) and stores the result to the rs register 1 ldre @(disp,pc) calculates (disp x 2 + pc) and stores the result to the re register 1 setrc #imm sets 8-bit immediate data imm to the rc[11:0] bits of the sr register and sets the information related to the number of repetitions to the rf[1:0] bits of the sr. rc[11:0] can be specified as 0 to 255. 1 setrc rm sets the[11:0] bits of t he rm register to the rc[11:0] bits of the sr register and sets the information related to the number of repetitions to the rf[1:0] bits of the sr. rc[11:0] can be specified as 0 to 4095. 1 section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 94 of 1458 rej09b0033-0300 the rs and re registers mu st be specified appropriately accordin g to the rules shown in table 3.4. the sh assembler supports control macros (repeat) as shown in table 3.6 to solve problems. table 3.6 repeat control macros instruction operation number of execution states repeat rptstart, rptend, #imm specifies rptstart as repeat start instruction, rptend as repeat end instruction, and 8-bit immediate data #imm as number of repetitions. this macro is extended to three instructions: ldrs, ldre, and setrc which are converted correctly. 3 repeat rptstart, rptend, rm specifies rptstart as repeat start instruction, rptend as repeat end instruction, and t he [11:0] bits of rm as number of repetitions. this macro is extended to three instructions: ldrs, ldre, and setrc which are converted correctly. 3 using the repeat macros shown in table 3.4, examples 1 to 4 shown above can be simplified to examples 5 to 8 as shown below. ? example 5: repeat loop consisting of 4 or more instructions (extended to the instruction stream shown in example 1, above) repeat rptstart, rptend, #4 instr0 ; rptstart: instr1 ; [repeat start instruction] ... ... ; ... ... ; instr(n-3) ; instr(n-2) ; instr(n-1) ; rptend: instrn ; [repeat end instruction] section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 95 of 1458 rej09b0033-0300 ? example 6: repeat loop consisting of three instructions (extended to the instruction stream shown in example 2, above) repeat rptstart, rptend, #4 instr0 ; rptstart: instr1 ; [repeat start instruction] instr2 ; rptend: instr3 ; [repeat end instruction] ? example 7: repeat loop consisting of two instructions (extended to the instruction stream shown in example 3, above) repeat rptstart, rptend, #4 instr0 ; rptstart: instr1 ; [repeat start instruction] rptend: instr2 ; [repeat end instruction] ? example 8: repeat loop consisting of one instruction instructions (extended to the instruction stream shown in example 4, above) repeat rptstart, rptend, #4 instr0 ; rptstart: rptend: instr1 ; [repeat start instruction]==[repeat end instruction] in the dsp mode, the system cont rol instructions (ldc and stc) that handle the rs and re registers are extended. the rc[11:0] bits and rf[1:0] bits of the sr can be controlled by the ldc and stc instructions for the sr register. these instructions should be used if an exception is enabled during repeat loop executio n. the repeat loop can be resu med correctly by storing the rs and re register values and rc[11:0] bits and rf[1:0] bits of the sr register before exception handling and by restoring the stored values after exception handling. however, note that there are some restrictions on exception acceptance during repeat loop execution. for details refer to restrictions on repeat loop control in section 3.3.1, dsp repeat control and section 7, exception handling. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 96 of 1458 rej09b0033-0300 table 3.7 dsp mode extended system control instructions instruction operation number of execution states stc rs, rn rs rn 1 stc re, rn re rn 1 stc.l rs, @-rn rn-4 rn, rs (rn) 1 stc.l re, @-rn rn-4 rn, re (rn) 1 ldc.l @rn+, rs (rn) rs, rn+4 rn 4 ldc.l @rn+, re (rn) re, rn+4 rn 4 ldc rn,rs rn rs 4 ldc rn, re rn re 4 (3) restrictions on repeat loop control (a) repeat control in struction assignment the setrc instruction must be executed after ex ecuting the ldrs and ldre instructions. in addition, note that at least one instruction is required between the setrc instruction and a repeat start instruction. (b) illegal instruction one or more instructions following th e repeat detection instruction if one of the following instructions is executed between an instruction following a repeat detection instruction to a repeat end instruction, an illegal instruction exception occurs. ? branch instructions bra, bsr, bt, bf, bt/s, bf/s, bsrf, rts, braf, rte, jsr, jmp, trapa ? repeat control instructions setrc, ldrs, ldre ? load instructions for sr, rs, and re registers ldc rn,sr, ldc @rn+,sr, ldc rn,re, ldc @rn+,re, ldc rn,rs, ldc @rn+,rs note: this restriction applies to all instructions for a repeat loop consisting of one to three instructions and to three instructions including a repeat end instruction. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 97 of 1458 rej09b0033-0300 (c) instructions prohibited duri ng repeat loop (in a repeat loop consisting of four or more instructions) the following instructions must not be placed between the repeat start instruction and repeat detection instruction in a repeat loop consisting of four or more instructions. otherwise, the correct operation ca nnot be guaranteed. ? repeat control instructions setrc, ldrs, ldre ? load instructions for sr, rs, and re registers ldc rn,sr, ldc @rn+,sr, ldc rn,re, ldc @rn+,re, ldc rn,rs, ldc @rn+,rs note: multiple repeat loops cannot be guaranteed. describe the inner loop by repeat control instructions, and the external loop by other instructions such as dt or bf/s. (d) branching to an instruction following th e repeat detection instru ction and restriction on an exception acceptance execution of a repeat detection instruction must be completed without any branch so that the cpu can recognize the repeat loop. therefore, when the execution branches to an instruction following the repeat detection instruction, the control will not be passed to a repeat start instruction after executing a repeat end instruction because the repeat loop is not recognized by the cpu. in this case, the rc[11:0] bits of the sr register will not be changed. ? if a conditional branch instruction is used in th e repeat loop, an instru ction before a repeat detection instruction must be speci fied as a branch destination. ? if a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine call instruction must be pl aced before a repeat de tection instruction. here, a branch includes a return from an excep tion processing routine. if an exception whose return address is placed in an instruction following the repeat detection instruc tion occurs, the repeat control cannot be returned correctly. accordingly, an ex ception acceptance is restricted from the repeat detection instruc tion to the repeat end instruction. exceptions such as interrupts that can be retained by the cpu are retained. for ex ceptions that cannot be retained by the cpu, a transition to an exception occurs but a program cannot be returned to the previous execution state correctly. for details, refer to section 7, exception handling. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 98 of 1458 rej09b0033-0300 notes: 1. if a trapa instruction is used as a repeat detection instruction, an instruction following the repeat detection instruction is re garded as a return address. in this case, a control cannot be returned to the repeat co ntrol correctly. in a trapa instruction, an address of an instruction following the repeat detection address is regarded as return address. accordingly, to return to the repeat contro l correctly, place a return address prior to the repeat detection instruction. 2. if a sleep instruction is placed following a repeat detection instru ction, a transition to the low-power consumption state or an exce ption acceptance such as interrupts can be performed correctly. in this case, however, the repeat control cannot be returned correctly. to return to the repeat contro l correctly, the sleep instruction must be placed prior to th e repeat detection instruction. (e) branch from a repeat detection instruction if a repeat detection instruction is a delayed slot instruction of a delayed branch instruction or a branch instruction, a repeat loop can be ac knowledged when a branch does not occur in a branch instruction. if a branch occurs in a bran ch instruction, a repeat control is not performed and a branch destination instruction is executed. (f) program counter du ring repeat control if rc[11:0] 2, the program counter (pc) value is not correct for instructions two instructions following a repeat detecti on instruction. in a repeat loop consisting of one to three instructions, the pc indicates the correct value (instruction address + 4) for an in struction (repeat start instruction) following a repeat detect ion instruction but the pc continues to indicate the same address (repeat start in struction address) from the subseq uent instruction to a repeat end instruction. in a repeat loop consisting of four or more instructions, the pc indicates the correct value (instruction address + 4) for an instruction following a repeat detect ion instruction, but pc indicates the rs and (rs +2 ) for instructions two and three instructions following the repeat detection instruction. here, rs indicates the value stored in the repeat start register (rs). the correct operation cannot be guaranteed for the incorrect pc values. accordingly, pc relative addressi ng instructions placed two or mo re instructions following the repeat detection instruction cannot be execute d correctly and the correct results cannot be obtained. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 99 of 1458 rej09b0033-0300 ? pc relative addressing instructions mov.a @(disp, pc), rn mov.w @(disp, pc), rn mov.l @(disp, pc), rn (including the case when the mov #imm,rn is extended to mov.w @(disp, pc), rn or mov.l @(disp, pc), rn) table 3.8 pc value during re peat control (when rc[11:0] 2) number of instructions in repeat loop 1 2 3 4 rptdtct rptdtct + 4 rptdtct + 4 rptdtct + 4 rptdtct +4 rptdtct1 rptdtct1 + 4 rptdtct1 + 4 rptdtct1 + 4 rptdtct1 + 4 rptdtct2 D rptdtct1+ 4 rptdtct1 + 4 rs rptdtct3 D D rptdtct1 + 4 rs + 2 note: in table 3.8, the following labels are used. rptdtct: an address of the repeat detection instruction rptdtct1: an address of the instruction one instruction following the repeat start instruction (in a repeat loop consisting of one to three instructions, rptstart is a repeat start instruction) rptdtct2: an address of the instruction two instruction following the repeat start instruction rptdtct3: an address of the instruction thr ee instruction following the repeat start instruction (g) repeat counter and repeat control the cpu always executes a program with comparin g the repeat end register (re) and the program counter (pc). if the pc matches the re while the rc[11:0] bits of the sr register are other than 0, the repeat control function is initiated. ? if rc 2, a control is passed to a repeat start inst ruction after a repeat en d instruction has been executed. the rc is decremented by 1 at the completion of the repeat end instruction. in this case, restrictions (1) to (6) are also applied. ? if rc == 1, the rc is decremented to 0 at the co mpletion of the repeat end instruction and a control is passed to the subsequent instruction. in this case, restrictions (1) to (6) are also applied. ? if rc == 0, the repeat control function is not initi ated even if a repeat detection instruction is executed. the repeat loop is executed once as normal instructions and a control is not be passed to a repeat start instruction even if a repeat end instruction is executed. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 100 of 1458 rej09b0033-0300 3.4 dsp data transfer instructions in dsp mode, data transfer instructions are added for the dsp unit registers. the newly added instructions are classified into the following three groups. 1. double data transfer instructions the dsp unit is connected to the x memory an d y memory via the specific buses called x bus and y bus. by using the data tr ansfer instructions using the x and y buses, two data items can be transferred between the dsp unit and x/y memo ries simultaneously. th ese instructions are called double data transfer instructions. thes e double data transfer instructions can be described in combination with the dsp operation in structions to execute data transfer and data operation in parallel, 2. single data transfer instructions the dsp unit is also connected to the l bus that is used by the cpu. the dsp registers other than the dsr can access any virtual addresses gene rated by the cpu. in this case, the single data transfer instructions are us ed. the single data transfer instructions cannot be used in combination with the dsp operation instructions and can access only one data item at a time. 3. system control instructions some of the dsp unit registers are handled as the cpu system registers. to control these system registers, the system c ontrol registers are supported. th e dsp registers are connected to the cpu general registers via the data transfer bus (c bus). in any dsp data transfer instru ctions, an address to be accessed is generated and output by the cpu. for dsp data transfer instructions, some of the cpu general registers are used for address generation and specific addressing modes are used. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 101 of 1458 rej09b0033-0300 x memory dsp unit xdb [15:0] xab [15:0] cpu ya b [15:0] cdb [31:0] dsr a0 a1 m0 m1 x0 x1 y0 y1 a0g a1g lab [31:0] ldb [31:0] ydb [15:0] y memory legend xab xdb ya b ydb lab ldb cdb : x bus (address) : x bus (data) : y bus (address) : y bus (data) : l bus (address) : l bus (data) : c bus (data) figure 3.4 dsp registers and bus connections (1) double data transfer instructions (movx.w, movy.w) with double data tran sfer instructions, x memory and y memory can be accessed in parallel. in this case, the specific buses called x bus and y bus are used to access x memory and y memory, respectively. to fetch the cpu instructions, the l bus is used. accordingly, no conflict occurs among x, y, and l buses. load instructions for x memory specify the x0 or x1 register as the de stination operand. load instructions for y memory specify the y0 or y1 register as the destination operand. store registers for x or y memory specify the a0 or a1 register as the source operand. these instructions use only word data (16 bits). when a word data transfer instruction is executed, the upper word of register operand is used. to load word data, data is loaded to the upper word of the destination register and the lower word of the destinatio n register is automatically cleared to 0. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 102 of 1458 rej09b0033-0300 double data transfer instructions can be described in parallel to the dsp operation instructions. even if a conditional operation instruction is specified in parallel to a double data transfer instruction, the specified condition does not affect th e data transfer operations. for details, refer to section 3.5, dsp data operation instructions. double data transfer instruc tions can access only the x memory or y memory and cannot access other memory space. the x bus and y bus are 16 bits and support 64-byte address spaces corresponding to address area s h'a5000000 to h'a500ffff an d h'a5010000 to h'a501ffff, respectively. because these areas are included in the p2/uxy area, they ar e not affected by the cache and address translation unit. (2) single data transfer instructions the single data transfer instructions access any me mory location. all dsp registers other than the dsr can be specified as source and destination operands.* guard bit registers a0g and a1g can also be specified as two independ ent registers. because these instructions use the l bus (lab and ldb), these instructions can access any virtual sp ace handled by the cpu. if these instructions access the cacheable area while the cache is enabled, the area accessed by these instructions are cached. the x memory and y memory are mapped to the virtual address space and can also be accessed by the single data transfer instructions. in this case, bus conflict may occur between data transfer and instruction fetch because the cpu also uses the l bus for instruction fetches. the single data transfer instructions can handle both word and longword data. in word data transfer, only the upper word of the operand register is valid. in word data load, word data is loaded into the upper word of the destination registers and the lower word of the destination is automatically cleared to 0. if the guard bits are supported, the sign bit is extended before storage. in longword data load, longword data is loaded into the upper and lower word of the destination register. if the guard bits are supported, the sign bit is extended before storage. when the guard register is stored, the sign bit is extended to the upper 24 bits of the ldb and are loaded onto the ldb bus. notes: * since the dsr register is defined as th e system register, it can be accessed by the lds or sts instruction. 1. any data transfer instruction is ex ecuted at the ma stage of the pipeline. 2. any data transfer instruction does not modify the condition code bits of the dsr register. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 103 of 1458 rej09b0033-0300 (3) system control instructions the dsr, a0, x0, x1, y0, and y1 registers in the dsp unit can also be used as the cpu system registers. accordingly, data transfer operations between these dsp system registers and general registers or memory can be executed by the sts and lds instructions. these dsp system registers can be treated as the cpu system regist er such as pr, mach and macl and can use the same addressing modes. table 3.9 extended system cont rol instructions in dsp mode instruction operation execution states sts dsr,rn dsr rn 1 sts a0,rn a0 rn 1 sts x0,rn x0 rn 1 sts x1,rn x1 rn 1 sts y0,rn y0 rn 1 sts y1,rn y1 rn 1 sts.l dsr,@-rn rn ? 4 rn, dsr (rn) 1 sts.l a0,@-rn rn ? 4 rn, a0 (rn) 1 sts.l x0,@-rn rn ? 4 rn, x0 (rn) 1 sts.l x1,@-rn rn ? 4 rn, x1 (rn) 1 sts.l y0,@-rn rn ? 4 rn, y0 (rn) 1 sts.l y1,@-rn rn ? 4 rn, y1 (rn) 1 lds.l @rn+,dsr (rn) dsr, rn + 4 rn 1 lds.l @rn+,a0 (rn) a0, rn + 4 rn 1 lds.l @rn+,x0 (rn) x0, rn + 4 rn 1 lds.l @rn+,x1 (rn) x1, rn + 4 rn 1 lds.l @rn+,y0 (rn) y0, rn + 4 rn 1 lds.l @rn+,y1 (rn) y1, rn + 4 rn 1 lds rn,dsr rn dsr 1 lds rn,a0 rn a0 1 lds rn,x0 rn x0 1 lds rn,x1 rn x1 1 lds rn,y0 rn y0 1 lds rn,y1 rn y1 1 section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 104 of 1458 rej09b0033-0300 3.4.1 general registers the dsp instructions 10 general registers in the 16 general registers are used as address pointers or index registers for double data transfers and single data transfers. in the following descriptions, another register function in the dsp instructions is also indicated within parentheses [ ]. ? double data transfer instru ctions (x memory and y memory are accessed simultaneously) in double data transfers, x memory y memory can be accessed simultaneously. to specify x and y memory addresses, two address pointers are supported. address pointer index register x memory (movx.w) r4,r5[ax] r8 [ix] y memory (movy.w) r6,r7[ay] r9 [iy] ? single data transfer instructions in single data transfer, any virtual address sp ace can be accessed via the l bus. the following address pointers and index registers are used. address pointer index register any virtual space (movs.w/l) r4,r5, r2, r3[as] r8 [is] 31 general registers (dsp mode) x and y double data transfers: r4, 5 r8 single data transfers: r4, 5, 2, 3 r8 r6, 7 r9 [ax] [ix] [as] [is] [ay] [iy] : address register set for the x data memory : index register for x address register set ax : address register set for all data memories : index register used for single data transfers : address register set for the y data memory : index register for y address register set ay r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 [as2] [as3] [as0] [as1, ax1] [ay0] [ay1] [ix, is] [iy] 0 figure 3.5 general registers (dsp mode) section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 105 of 1458 rej09b0033-0300 in assembler, r0 to r9 are used as symbols. in the dsp data tr ansfer instructions, the following register names (alias) can also be used. in assembler, described as shown below. ix: .reg (r8) ix indicates the alias of register 8. other aliases are shown below. ax0: .reg (r4) ax1: .reg (r5) ix: .reg (r8) ay0: .reg (r6) ay1: .reg(r7) iy: .reg (r9) as0: .reg (r4); this definition is used for if the alias is required in the single data transfer as1: .reg (r5); this definition is used for if the alias is required in the single data transfer as2: .reg (r2) as3: .reg (r3) is: .reg (r8); this definition is used for if th e alias is required in the single data transfer section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 106 of 1458 rej09b0033-0300 3.4.2 dsp data addressing table 3.10 shows the relationship between the double data transfer instructions and single data transfer instructions. table 3.10 overview of da ta transfer instructions double data transfer instructions single data transfer instructions movx.w movy.w movs.w, movs.l address register ax: r4, r5 ay: r6, r7 as: r2, r3, r4, r5 index register ix: r8, iy: r9 is: r8 addressing nop/inc (+2)/index addition: post-increment nop/inc (+2, +4)/index addition: post- increment ? dec (?2, ?4): pre-decrement modulo addressing possible not possible data bus xdb, ydb ldb data length 16 bits (word) 16/32 bits (word/longword) bus conflict no yes memory x/y data memory entire memory space source register da: a0, a1 ds: a0/a1, m0/m1, x0/x1, y0/y1, a0g, a1g destination register dx: x0/x1 dy: y0/y1 ds: a0/a1, m0/m1, x0/x1, y0/y1, a0g, a1g section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 107 of 1458 rej09b0033-0300 (1) addressing mode for doubl e data transfer instructions the double data transfer instructions supports the following three addressing modes. ? non-update address register addressing the ax and ay register s are address po inters. they are not updated. ? increment address register addressing the ax and ay registers are address pointers. af ter a data transfer, they are each incremented by 2 (post-increment). ? addition index register addressing the ax and ay registers are address poin ters. after a data transfer, the value of the ix or iy register is added to each (post-increment). the double da ta transfer instructions do not supports decrement addressing mode. to perform decrement, ?2 or ?4 is set in the index register and addition index register addressing is specified. when using x/y data addressing, bit 0 of the address pointer is invalid; bits 0 and 1 of the address pointer are invalid in word access. accordingly, bit 0 of the address pointer and index register must be cleared to 0 in x/y data addressing. when accessing x and y memory using the x and y buses, the upper word of ax and ay is ignored. the result of ay+ or ay+iy is stored in the lower word of ay, while the upper word retains its original value. the ax and ax +ix oper ations are executed in longword (32 bits) and the upper word may be changed according to the result. (2) single data addressing the following four kinds of addressing can be used with single data transfer instructions. ? non-update address register addressing the as register is an address pointer. an acce ss to @as is performed but as is not updated. ? increment address register addressing: the as register is an address pointer. after an access to @as, the as register is incremented by 2 or 4 (post-increment). ? addition index register addressing: the as register is an address pointer. after an access to @as, the value of the is register is added to the as register (post-increment). ? decrement address register addressing: the as register is an address pointer. before a data transfer, ?2 or ?4 is added to the as register (i.e. 2 or 4 is s ubtracted) (pre-decrement). section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 108 of 1458 rej09b0033-0300 in single data transfer instructions, all bits in 32-bit address are valid. 3.4.3 modulo addressing in double data transfer instructions, a module addressing can be used. if the address pointer value reaches the preset modulo end address while a modulo addressi ng mode is specified,, the address pointer value becomes the modulo start address. to control modulo addressing, the modulo register (mod) extended in the dsp mode and the dmx and dmy bits of the sr register are used. the mod register is provided to set the start and end addresses of the modulo address area. the upper and lower words of the mod register store modulo start address (ms) and modulo end address (me), respectively. the ldc and stc in structions are extended for mod register handling. if the dmx bit in the sr register is set, the modulo addressing is speci fied for the x address register. if the dmy bit in the sr register is se t, the modulo addressing is specified for the y address register. modulo addressi ng is valid for either the x or the y address register, only; it cannot be set for both at the same time. therefore, dmx and dmy cannot both be set simultaneously (if they are, the dmy setting will be valid). ( in the future, this specification may be changed.) the mdx and mdy bits of the sr ca n be specified by the stc or ldc instruction for the sr register. if an exception is accepted during modulo addres sing, the mdx and mdy bits of the sr and mod register must be saved. by restoring these register values, a control is returned to the modulo addressing after an exception handling. table 3.11 modulo addressing control instructions instruction operation execution states stc mod,rn mod rn 1 stc.l mod,rn rn ? 4 rn, mod (rn) 1 ldc.l @rn+,mod (rn) rn, rn + 4 rn 4 ldc rn,mod rn mod 4 section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 109 of 1458 rej09b0033-0300 an example of the use of modulo addressing is shown below. mov.l #h?70047000, r10 ;specify ms=h?7000 me = h?7004 ldc r10,mod ;specify me:ms to mod register stc sr, r10 ; mov.l #h?fffff3ff, r11; mov.l #h?00000400, r12; and r11, r10 ; or r12, r10 ; ldc r10, sr ; specify sr.mdx=1, sr.mdy=0, and x modulo addressing mode mov.l #h?a5007000, r4 movx.w @r4+,x0 ; r4: h?a5007000 h?a5007002 movx.w @r4+,x0 ; r4: h?a5007002 h?a5007004 movx.w @r4+,x0 ; r4: h?a5007004 h?a5007000 (matches to me and ms is set) movx.w @r4+,x0 ; r4: h?a5007000 h?a5007002 the start and end addresses are specified in ms and me, then the dmx or dmy bit is set to 1. when the x or y data transfer instruction specifi ed by the dmx or dmy is executed, the address register contents before updating are compared with me*, and if they match, start address ms is stored in the address register as the value after updating. when the addressing type of the x/y data transfer instruction is no-update, the x/y data transfer instruction is not returned to ms even if they match me. when the addressing type of the x/y data transfer instruction is addition index regist er addressing, the address pointed may not match the address pointer me, and exceed it. in this cas e, the address pointer value does not become the modulo start address. the maximum modulo size is 64 kbytes. this is sufficient to access the x and y data memory. note: not only with modulo addressing, but when x and y data addressing is used, bit 0 is ignored. 0 must always be written to bit 0 of the address pointer, index register, ms, and me. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 110 of 1458 rej09b0033-0300 3.4.4 memory data formats memory data formats that can be used in the dsp instructions are classified into byte and longword. an address error will occur if word data starting from an address other than 2n or longword data starting from an address other than 4n is accessed by movs.l, lds.l, or sts.l instruction. in such cases, the data accessed cannot be guaranteed an address error will not occur if word data starting from an addres s other than 2n is accessed by the movx.w or movy.w instruction. when using the movx.w or movy.w instruction, an address must be specified on the boundary 2n. if an address is sp ecified other than 2n, the data accessed cannot be guaranteed. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 111 of 1458 rej09b0033-0300 3.4.5 instruction formats of double and single transfer instructions the format of double data transfer instructions is shown in tables 3.12 and that of single data transfer instructions in table 3.13. table 3.12 double data tr ansfer instruction formats type mnemonic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nopx 0 0 0 0 0 movx.w @ax,dx 1 1 1 1 0 0 ax dx 0 0 1 movx.w @ax+,dx 1 0 movx.w @ax+ix,dx 1 1 movx.w da,@ax da 1 0 1 movx.w da,@ax+ 1 0 x memory data transfer movx.w da,@ax+ix 1 1 nopy 0 0 0 0 0 movy.w @ay,dy 1 1 1 1 0 0 ay dy 0 0 1 movy.w @ay+,dy 1 0 movy.w @ay+iy,dy 1 1 movy.w da,@ay da 1 0 1 movy.w da,@ay+ 1 0 y memory data transfer movy.w da,@ay+iy 1 1 note: ax: 0 = r4, 1 = r5 ay: 0 = r6, 1 = r7 dx: 0 = x0, 1 = x1 dy: 0 = y0, 1 = y1 da: 0 = a0, 1 = a1 section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 112 of 1458 rej09b0033-0300 table 3.13 single data tr ansfer instruction formats type mnemonic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 movs.w @-as,ds 1 1 1 1 0 1 as ds 0:( * ) 0 0 0 0 movs.w @as,ds 0:r4 1:( * ) 0 1 movs.w @as+,ds 1:r5 2:( * ) 1 0 movs.w @as+is,ds 2:r2 3:( * ) 1 1 movs.w ds,@-as 3:r3 4:( * ) 0 0 0 1 movs.w ds,@as 5:a1 0 1 movs.w ds,@as+ 6:( * ) 1 0 movs.w ds,@as+is 7:a0 1 1 movs.l @-as,ds 8:x0 0 0 1 0 movs.l @as,ds 9:x1 0 1 movs.l @as+,ds a:y0 1 0 movs.l @as+is,ds b:y1 1 1 movs.l ds,@-as c:m0 0 0 1 1 movs.l ds,@as d:a1g 0 1 movs.l ds,@as+ e:m1 1 0 single data transfer movs.l ds,@as+is f:a0g 1 1 note: * codes reserved for system use. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 113 of 1458 rej09b0033-0300 3.5 dsp data operation instructions 3.5.1 dsp registers this lsi has eight data registers (a0, a1, x0, x1, y0, y1, m0 and m1) and one control register (dsr) as dsp registers (figure 3.3). four kinds of operation access the dsp data regist ers. the first is dsp da ta processing. when a dsp fixed-point data operation uses a0 or a1 as th e source register, it uses the guard bits (bits 39 to 32). when it uses a0 or a1 as the destination register, guard bits 39 to 32 are valid. when a dsp fixed-point data operation uses a dsp register other than a0 or a1 as the source register, it sign-extends the source value to bits 39 to 32. when it uses one of these registers as the destination register, bits 39 to 32 of the result are discarded. the second kind of operation is an x or y da ta transfer operation, movx.w, movy.w. this operation accesses the x and y memories through the 16-bit x and y data bu ses (figure 3.4). the register to be loaded or stored by this operation always comprises the upper 16 bits (bits 31 to 16). x0 or x1 can be the destination of an x memory load and y0 or y1 can be the destination of a y memory load, but no other register can be the destination register in this operation. when data is read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits 15 to 0) are automatically cleared. a0 an d a1 can be stored in the x or y memory by this operation, but no other registers can be stored. the third kind of operation is a single-data transfer instruct ion, movs.w or movs.l. these instructions access any memory location through the ldb (figure 3.4). all dsp registers connect to the ldb and can be the source or destination register of the data transfer. these instructions have word and longword access modes. in word mode, registers to be loaded or stored by this instruction comprise the upper 16 bits (bits 31 to 16) for dsp registers except a0g and a1g. when data is loaded into a register other than a0g and a1g in word mode, the lower half of the register is cleared. when a0 or a1 is used, the data is sign-extended to bits 39 to 32 and the lower half is cleared. when a0g or a1g is the destinati on register in word mode, data is loaded into an 8-bit register, but a0 or a1 is not cleared. in longword mode, when the destination register is a0 or a1, it is sign-extended to bits 39 to 32. the fourth kind of operation is system control in structions such as lds, sts, lds.l, or sts.l. the dsr, a0, x0, x1, y0, and y1 registers of the ds p register can be treated as system registers. for these registers, data transfer instructions between the cpu general registers and system registers or memory access instructions are supported. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 114 of 1458 rej09b0033-0300 tables 3.14 and 3.15 show the data type of registers used in dsp instructions. some instructions cannot use some registers shown in the tables because of instruction code limitations. for example, pmuls can use a1 as the source regist er, but cannot use a0. these tables ignore details of register selectability. table 3.14 destination regi ster in dsp instructions guard bits register bits registers instructions 39 32 31 16 15 0 fixed-point, psha, pmuls sign-extended 40-bit result integer, pdmsb sign-extended 24-bit result cleared dsp operation logical, pshl cleared 16-bit result cleared movs.w sign-extended 16-bit data cleared a0, a1 data transfer movs.l sign-extended 32-bit data movs.w data no update a0g, a1g data transfer movs.l data no update fixed-point, psha, pmuls 32-bit result dsp operation integer, logical, pdmsb, pshl 16-bit result cleared movx/y.w, movs.w 16-bit result cleared x0, x1 y0, y1 m0, m1 data transfer movs.l 32-bit data section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 115 of 1458 rej09b0033-0300 table 3.15 source register in dsp operations guard bits register bits registers instructions 39 32 31 16 15 0 fixed-point, pdmsb, psha 40-bit data integer 24-bit data dsp operation logical, pshl, pmuls 16-bit data movx/y.w, movs.w 16-bit data a0, a1 data transfer movs.l 32-bit data movs.w data a0g, a1g data transfer movs.l data fixed-point, pdmsb, psha sign * 32-bit data integer sign * 16-bit data dsp logical, pshl, pmuls 16-bit data movs.w 16-bit data x0, x1 y0, y1 m0, m1 data transfer movs.l 32-bit data note: * the data is sign-extended and input to the alu. the dsp unit incorporates one cont rol register and dsp status regi ster (dsr). the dsr register stores the dsp data operation result (zero, negative, others). the dsp register also has the dc bit whose function is similar to the t bit in the cpu register. the dc bit functions as status flag. conditional dsp data operations are controlled based on the dc bit. these operation control affects only the dsp unit instructions. in other words, these operations control affects only the dsp registers and does not affect address register update and cpu instructions such as load and store instructions. a condition to be reflected on the dc bit should be specified to the dc status selection bits (cs[2:0]). the unconditional dsp type data instructions other than pmuls, movx, movy, and movs change the condition flag and dc bit. howeve r, the cpu instructions including the mac instruction do not modify the dc bit. in addition, conditional dsp instructions do not modify the dsr. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 116 of 1458 rej09b0033-0300 table 3.16 dsr register bits bits bit name initial value r/w function 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 gt 0 r/w signed greater bit indicates that the operation re sult is positive (except 0), or that operand 1 is greater than operand 2 1: operation result is posit ive, or operand 1 is greater than operand 2 6 z 0 r/w zero bit indicates that the operation re sult is zero (0), or that operand 1 is equal to operand 2 1: operation result is zero (0), or operands are equal 5 n 0 r/w negative bit indicates that the operation re sult is negative, or that operand 1 is smaller than operand 2 1: operation result is negat ive, or operand 1 is smaller than operand 2 4 v 0 r/w overflow bit indicates that the operation result has overflowed 1: operation result has overflowed section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 117 of 1458 rej09b0033-0300 bits bit name initial value r/w function 3 to 1 cs all 0 r/w dc bit status selection designate the mode for select ing the operation result status to be set in the dc bit 000: carry/borrow mode 001: negative value mode 010: zero mode 011: overflow mode 100: signed greater mode 101: signed greater than or equal to mode 110: reserved (setting prohibited) 111: reserved (setting prohibited) 0 dc 0 r/w dsp status bit sets the status of the oper ation result in the mode designated by the cs bits 0: designated mode status has not occurred 1: designated mode status has occurred indicates the operation result by carry or borrow regardless of the cs bit status after the paddc or psubc instruction has been executed. the dsr is assigned to the syst em registers. for the dsr, the following load and store instructions are supported. sts dsr,rn; sts.l dsr,@-rn; lds rn,dsr; lds.l @rn+,dsr; if the dsr is read by the sts instruction, upper bits (bits 31 to 16) are all 0. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 118 of 1458 rej09b0033-0300 3.5.2 dsp operation instruction set dsp operation instructions are instructions for digital signal processing performed by the dsp unit. these instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. the instruction code is divided into a field a and field b; a parallel data transfer instruction is specified in the field a, and a single or double data operation instruction in the field b. instructions can be specified independently, and are also executed independently. b-field data operation instructions are of three kinds: double data operation instructions, conditional single data operation instructions, and unconditional single data operation instructions. the formats of the dsp operation instructions are shown in table 3.17 . the respective operands are selected independently from the dsp regist ers. the correspondence between dsp operation instruction operands and registers is shown in table 3.18. table 3.17 dsp operation instruction formats type instruction formats double data operation instructions aluop. sx, sy, du mltop. se, df, dg conditional single data operation instructions dct aluop. sx, sy, dz dcf aluop. sx, sy, dz dct aluop. sx, dz dcf aluop. sx, dz dct aluop. sy, dz dcf aluop. sy, dz unconditional single data operation instructions aluop. sx, sy, dz aluop. sx, dz aluop. sy, dz mltop. se, sf, dg section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 119 of 1458 rej09b0033-0300 table 3.18 correspondence between dsp instruction operands and registers alu operations multiply operations register sx sy dz du se sf dg a0 yes yes yes yes a1 yes yes yes yes yes yes m0 yes yes yes m1 yes yes yes x0 yes yes yes yes yes x1 yes yes yes y0 yes yes yes yes yes y1 yes yes yes when writing parallel instructions, the field-b instruction is written first, followed by the field-a instruction. a sample parallel processing program is shown in figure 3.6. padd pinc pcmp dcf movx.w movx.w movx.w @r4+, @r5+r8, @r4, x0 x0 x1 movy.w movy.w [nopy] @r6+, @r7+, y0 y1 a0, m1, m1, m0, a1 m0 a0 pmuls x0, y0, m0 figure 3.6 sample parallel instruction program square brackets mean that the contents can be omitted. the no operation instructions nopx and nopy can be omitted. for details on the field b in dsp data operation instructions, refer to s ection 3.6.4, dsp operation instructions. the dsr register condition code bit (dc) is always updated on the basis of the result of an unconditional alu or shift operation instruction. conditional instructions do not update the dc bit. multiply instructions, also, do not update the dc bit. dc bit updating is performed by means of the cs[2:0] bits in the dsr register. the dc bit update rules are shown in table 3.19. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 120 of 1458 rej09b0033-0300 table 3.19 dc bit update definitions cs [2:0] condition mode description 0 0 0 carry or borrow mode the dc bit is set if an alu arithm etic operation generates a carry or borrow, and is cleared otherwise. when a psha or pshl shift instruction is executed, the last bit data shifted out is copied into the dc bit. when an alu logical operation is executed, the dc bit is always cleared. 0 0 1 negative value mode when an alu or shift (psha) arit hmetic operation is executed, the msb of the result, including the guard bits, is copied into the dc bit. when an alu or shift (pshl) logical operation is executed, the msb of the result, excluding the guard bits, is copied into the dc bit. 0 1 0 zero value mode the dc bit is set if t he result of an alu or shift operation is all- zeros, and is cleared otherwise. 0 1 1 overflow mode the dc bit is set if the re sult of an alu or shift (psha) arithmetic operation exceeds the destination register range, excluding the guard bits, and is cleared otherwise. when an alu or shift (pshl) logical operation is executed, the dc bit is always cleared. 1 0 0 signed greater-than mode this mode is similar to signed greater-or-equal mode, but dc is cleared if the result is all-zeros. dc = ~{(negative value ^ over-range) | zero value}; in case of arithmetic operation dc = 0; in case of logical operation 1 0 1 signed greater-or- equal mode if the result of an alu or shi ft (psha) arithmetic operation exceeds the destination register range, including the guard bits (over-range), the definition is the same as in negative value mode. if the result is not over-range, the definition is the opposite of that in negative value mode. when an alu or shift (pshl) logical operation is executed, the dc bit is always cleared. dc = ~(negative value ^ over-range); in case of arithmetic operation dc = 0 ; in case of logical operation 1 1 0 reserved (setting prohibited) 1 1 1 reserved (setting prohibited) section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 121 of 1458 rej09b0033-0300 ? conditional operations and data transfer some instructions belonging to this class can be executed conditionally, as described earlier. the specified condition is valid only for the b field of the instruction, and is not valid for data transfer instructions for which a parallel specif ication is made. examples are shown in figure 3.7. dct padd x0,y0,a0 movx.w @r4+,x0 movy.w a0,@r6+r9 when condition is true before execution: after execution: x0=h'33333333, y0=h'55555555, a0=h'123456789a, r4=h'00008000, r6=h'00005000, r9=h'00000004 (r4)=h'1111, (r6)=h'2222 x0=h'11110000, y0=h'55555555, a0=h'0088888888, r4=h'00008002, r6=h'00005004, r9=h'00000004 (r4)=h'1111, (r6)=h'3456 when condition is false before execution: after execution: x0=h'33333333, y0=h'55555555, a0=h'123456789a, r4=h'00008000, r6=h'00005000, r9=h'00000004 (r4)=h'1111, (r6)=h'2222 x0=h'11110000, y0=h'55555555, a0=h'123456789a, r4=h'00008002, r6=h'00005004, r9=h'00000004 (r4)=h'1111, (r6)=h'3456 figure 3.7 examples of conditional operations and data transfer instructions ? assignment of nopx and nopy instruction codes when there is no data transfer instruction to be parallel-processed simultaneously with a dsp operation instruction, an nopx or nopy instru ction can be written as the data transfer instruction, or the instruction can be omitted. the instruction code is the same whether an nopx or nopy instruction is written or the in struction is omitted. examples of nopx and nopy instruction codes are shown in table 3.20. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 122 of 1458 rej09b0033-0300 table 3.20 examples of nopx and nopy instruction codes instruction code padd x0,y0,a0 movx.w @r4+,x0 movy.w @r6+r9,y0 1111100000001011 1011000100000111 padd x0,y0,a0 nopx movy.w @r6+r9,y0 1111100000000011 1011000100000111 padd x0,y0,a0 nopx nopy 1111100000000000 1011000100000111 padd x0,y0,a0 nopx 1111100000000000 1011000100000111 padd x0,y0,a0 1111100000000000 1011000100000111 movx.w @r4+,x0 movy.w @r6+r9,y0 1111000000001011 movx.w @r4+,x0 nopy 1111000000001000 movs.w @r4+,x0 1111010010001000 nopx movy.w @r6+r9,y0 1111000000000011 movy.w @r6+r9,y0 1111000000000011 nopx nopy 1111000000000000 nop 0000000000001001 section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 123 of 1458 rej09b0033-0300 3.5.3 dsp-type data formats this lsi has several different data formats that depend on the instruction. this section explains the data formats for dsp type instructions. figure 3.8 shows three dsp-type data formats with different binary point positions. a cpu-type data format with the binary point to the right of bit 0 is also shown for reference. the dsp-type fixed point data format has the binary point between bit 31 and bit 30. the dsp- type integer format has the binary point between bit 16 and bit 15. the dsp-type logical format does not have a binary point. the valid data lengths of the data formats depend on the instruction and the dsp register. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 124 of 1458 rej09b0033-0300 39 s 31 30 0 ?2 8 to +2 8 ? 2 ?31 39 s 32 31 0 ?2 23 to +2 23 ? 1 39 s s 31 30 16 15 16 15 0 ?1 to +1 ? 2 ?15 39 31 16 15 0 s 31 0 ?2 15 to +2 15 ? 1 16 15 31 22 0 ?32 to +32 16 15 s 31 21 0 ?16 to +16 16 15 s 31 30 0 ?1 to +1 ? 2 ?31 s 31 0 ?2 31 to +2 31 ? 1 dsp type fixed point with guard bits without guard bits multiplier input dsp type integer dsp type logical with guard bits cpu type integer s: sign bit longword : binary point : does not affect the operations without guard bits shift amount for arithmetic shift (psha) shift amount for logical shift (pshl) figure 3.8 data formats the shift amount for the arithmetic shift (psha) instruction has a 7-bit field that can represent values from ?64 to +63, but ?32 to +32 are va lid numbers for the instruction. also the shift amount for a logical shift operation has a 6-bit field, but ?16 to +16 are valid numbers for the instruction. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 125 of 1458 rej09b0033-0300 3.5.4 alu fixed-point arithmetic operations figure 3.9 shows the alu arithmetic operation flow. table 3.21 shows the variation of this type of operation and table 3.22 shows the correspondence between each operand and registers. 39 31 31 39 31 0 source 1 0 destination alu dsr 39 0 source 2 guard guard guard gt z n v dc figure 3.9 alu fixed-point arithmetic operation flow note: the alu fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the base precision and 8 bits of the guard-bit parts. so the signed bit is copied to the guard-bit parts when a register not providing the guard-bit parts is specified as the source operand. when a register not providing the guard-bit part s is specified as a de stination operand, the lower 32 bits of the operation result are input into the destination register. alu fixed-point operations are executed between registers. each source and destination operand are selected independently from one of the dsp registers. when a register providing guard bits is specified as an operand, the guard bits are activat ed for this type of ope ration. these operations are executed in the dsp stage, as shown in figure 3.10. the dsp stage is the same stage as the ma stage in which memory access is performed. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 126 of 1458 rej09b0033-0300 table 3.21 variation of alu fixed-point operations mnemonic function source 1 source 2 destination padd addition sx sy dz (du) psub subtraction sx sy dz (du) paddc addition with carry sx sy dz psubc subtraction with borrow sx sy dz pcmp comparison sx sy ? sx all 0 dz pcopy data copy all 0 sy dz sx all 0 dz pabs absolute all 0 sy dz sx all 0 dz pneg negation all 0 sy dz pclr clear all 0 all 0 dz table 3.22 correspondence be tween operands and registers register sx sy dz du a0 yes yes yes a1 yes yes yes m0 yes yes m1 yes yes x0 yes yes yes x1 yes yes y0 yes yes yes y1 yes yes as shown in figure 3.10, data loaded from the memory at the ma stage, which is programmed at the same line as the alu operation, is not used as a source operand for this operation, even though the destination operand of the data load operation is identical to the source operand of the alu operation. in this case, previous operation results are used as the source operands for the alu operation, and then updated as the destination operand of the data load operation. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 127 of 1458 rej09b0033-0300 if 12 movx movx movx movx & padd movx & padd movx & padd 3456 id ex ma/dsp padd x0, y0, a0 movx.w @r4 + x0 movx.w @r4 + x0 slot stage operation sequence example addressing addressing previous cycle result is used. figure 3.10 operation sequence example every time an alu arithmetic operation is execute d, the dc, n, z, v, and gt bits in dsr are basically updated in accordance with the operati on result. however, in case of a conditional operation, they are not updated ev en though the specified condition is true and the operation is executed. in case of an unconditional operation, they are always updated in accordance with the operation result. the definition of a dc bit is sel ected by cs[2:0] (condition selection) bits in dsr. the dc bit result is as follows: section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 128 of 1458 rej09b0033-0300 (1) carry or borrow mode: cs[2:0] = b'000 the dc bit indicates that carry or borrow is generated from the most significant bit of the operation result, except the guard-bit parts. some examples are shown in figure 3.11. this mode is the default condition. when the input data is negative in a pabs or pneg instruction, carry is generated. example 1 carry detecting point guard bits carry is detected 0000 0000 +) 0000 0000 1111 0000 1111 0000 1111 0000 1111 0001 0000 0001 0000 0000 0000 0000 example 2 carry detecting point guard bits carry is not detected 1111 0011 +) 1111 1111 0111 0001 0000 0000 0000 0000 0000 0000 0011 (1) 11101000 0000 0000 0000 example 3 borrow detecting point guard bits borrow is not detected 0000 0000 ?) 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0000 0000 0000 0000 0000 0000 example 4 borrow detecting point guard bits borrow is detected 0000 0000 ?) 0000 0000 0001 0001 0000 0000 0000 0000 0001 0010 111111111111111111111111 figure 3.11 dc bit generation examples in carry or borrow mode section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 129 of 1458 rej09b0033-0300 (2) negative value mode: cs[2:0] = b'001 the dc flag indicates the same value as the msb of the operation result. when the result is a negative number, the dc bit shows 1. when it is 0 or a positive number, the dc bit shows 0. the alu always executes 40-bit arithmetic operation, so the sign bit to detect whether positive or negative is always got from the msb of the operation result regardless of the destination operand. some examples are shown in figure 3.12. example 1 sign bit guard bits negative value 1100 0000 +) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1100 0000 0000 0000 0000 0001 example 2 sign bit guard bits positive value 0011 0000 +) 0000 0000 0000 1000 0000 0000 0000 0000 0000 0001 0011 0000 1000 0000 0000 0001 figure 3.12 dc bit generation examples in negative value mode (3) zero value mode: cs[2:0] = b'010 the dc flag indicates whether the operation result is 0 or not. when the result is 0, the dc bit shows 1. when it is not 0, the dc bit shows 0. (4) overflow mode: cs[2:0] = b'011 the dc bit indicates whether or not overflow occurs in the result. when an operation yields a result beyond the range of the destination register, except the guard-bit parts, the dc bit is set. even though guard bits are provided in the destination register, the dc bit always indicates the result of when no guard bits are provided. so, the dc bit is always set to 1 if the guard-bit parts are used for large number represen tation. some dc bit generation examples in overflow mode are shown in figure 3.13. example 1 overflow detecting field guard bits overflow case 1111 1111 +) 1111 1111 1111 1000 1111 0000 1111 0000 1111 0000 11111111 0111 111111111111 example 2 overflow detecting field guard bits non overflow case 1111 1111 +) 1111 1111 1111 1000 1111 0000 1111 0000 1111 0001 11111111 1000 0000 0000 0000 figure 3.13 dc bit generation examples in overflow mode section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 130 of 1458 rej09b0033-0300 (5) signed greater than mode: cs[2:0] = b'100 the dc bit indicates whether or not the source 1 da ta (signed) is greater than the source 2 data (signed) as the result of comp are operation pcmp. the pcmp op eration should be executed before executing the conditional operation under th is condition mode. this mode is similar to the negative value mode described before, because the result of a compare operation is a positive value if the source 1 data is greater than the so urce 2 data. however, the signed bit of the result shows a negative value if the compare operation yields a result beyond the range of the destination operand, including the guard-bit parts (called ?over-range?), even though the source 1 data is greater than the source 2 data. the dc bit is updated concerning this type of special case in this condition mode. the equation below shows the definition of getting this condition: dc = ~ {(negative ^ over-range) | zero} when the pcmp operation is executed under this condition mode, the result of the dc bit is the same as the t bit?s result of the cmp/ gt operation of the cpu instruction. (6) signed greater than or equal mode: cs[2:0] = b'101 the dc bit indicates whether the source 1 data (signed) is greater than or equal to the source 2 data (signed) as the result of compare operation pc mp. this mode is similar to the signed greater than mode described before but the equal case is also included in this mode. the equation below shows the definition of getting this condition: dc = ~ (negative ^ over-range) when the pcmp operation is executed under this condition mode, the result of the dc bit is the same as the t bit?s result of a cmp/ge operation of the cpu instruction. the n bit always indicates the same state as the dc bit set in negative value mode by the cs[2:0] bits. see the negative value mode part above. the z bit always indicates th e same state as the dc bit set in zero value mode by the cs[2:0] bits. see the zero value mode part above. the v bit always indicates the same state as the dc bit se t in overflow mode by the cs[2:0] bits. see the overflow mode part above. the gt bit always indi cates the same state as the dc bit set in signed greater than mode by the cs[2:0] bits. see the signed greater than mode part above. note: the dc bit is always updat ed as the carry flag for ?paddc ? and is always updated as the carry/borrow flag for ?psubc? regardless of the cs[2:0] state. ? overflow protection the s bit in sr is effective for any alu fixed-point arithmetic operations in the dsp unit. see section 3.5.11, overflow protection, for details. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 131 of 1458 rej09b0033-0300 3.5.5 alu integer operations figure 3.14 shows the alu integer arithmetic operation flow. table 3.23 shows the variation of this type of operation. the correspondence betw een each operand and registers is the same as alu fixed-point operations as shown in table 3.22. 31 31 39 ignored cleared to 0 31 39 0 source 1 0 destination alu dsr 39 0 source 2 gt z n v dc guard guard guard figure 3.14 alu integer arithmetic operation flow table 3.23 variation of alu integer operations mnemonic function source 1 source 2 destination sx +1 dz pinc increment by 1 +1 sy dz sx ?1 dz pdec decrement by 1 ?1 sy dz note: the alu integer operations are basically 24 -bit operation, the upper 16 bits of the base precision and 8 bits of the guard-bits parts. so the signed bit is copied to the guard-bit parts when a register not providing the guard-bit pa rts is specified as the source operand. when a register not providing the guard-bit parts is specified as a destination operand, the upper word excluding the guard bits of the operation re sult are input into the destination register. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 132 of 1458 rej09b0033-0300 in alu integer arithmetic operations, the lower wo rd of the source operand is ignored and the lower word of the destination operand is automati cally cleared. the guard-bi t parts are effective in alu integer arithmetic operations if they are supp orted. others are basically the same operation as alu fixed-point arithmetic operations. as shown in table 3.23, however, this type of operation provides two kinds of instructions only, so that the second operand is actually either +1 or ?1. when a word data is loaded into one of the dsp un it?s registers, it is input as an upper word data. when a register providing guard bits is specified as an operand, the guard b its are also activated. these operations, as well as fixed-point operations , are executed in the dsp stage, as shown in figure 3.10. the dsp stage is the same stag e as the ma stage in which memory access is performed. every time an alu arithmetic operation is execute d, the dc, n, z, v, and gt bits in dsr are basically updated in accordance with the operatio n result. this is the same as fixed-point operations but the lower word of each source and destination operand is not used in order to generate them. see section 3.5.4, alu fixed-point arithmetic operations, for details. in case of a conditional operation, they are not updat ed even though the specified condition is true and the operation is execu ted. in case of an unconditional oper ation, they are always updated in accordance with the opera tion result. see section 3.5.4, alu fixed-point arithmetic operations, for details. ? overflow protection the s bit in sr is effective for any alu integer arithmetic operations in dsp unit. see section 3.5.11, overflow protection, for details. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 133 of 1458 rej09b0033-0300 3.5.6 alu logical operations figure 3.15 shows the alu logical operation flow. table 3.24 shows the variation of this type of operation. the correspondence be tween each operand and registers is the same as the alu fixed- point operations as shown in table 3.21. as shown in figure 3.15, this type of operation uses only the upper word of each operand. the lower word and guard-bit parts are ignored for the source operand and those of the destination operand are automatically cleared. these operations are also execute d in the dsp stage, as shown in figure 3.10. the ds p stage is the same stage as the ma stage in which memory access is performed. 31 31 31 39 39 39 ignored cleared to 0 0 source 1 0 destination alu dsr 0 source 2 gt z n v dc figure 3.15 alu logical operation flow table 3.24 variation of alu logical operations mnemonic function source 1 source 2 destination pand logical and sx sy dz por logical or sx sy dz pxor logical exclusive or sx sy dz section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 134 of 1458 rej09b0033-0300 every time an alu logical opera tion is executed, the dc, n, z, v, and gt bits in the dsr register are basically updated in accordance with the operation re sult. in case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. in case of an unconditional operation, they are always updated in accordance with the operation result. the definition of the dc bit is sel ected by the cs[2:0] (condition selection) bits in dsr. the dc bit result is: (1) carry or borrow mode: cs[2:0] = 000 the dc bit is always cleared. (2) negative value mode: cs[2:0] = 001 bit 31 of the operation result is loaded into the dc bit. (3) zero value mode: cs[2:0] = 010 the dc bit is set when the operation re sult is zero; otherwise it is cleared. (4) overflow mode: cs[2:0] = 011 the dc bit is always cleared. (5) signed greater than mode: cs[2:0] = 100 the dc bit is always cleared. (6) signed greater than or equal mode: cs[2:0] = 101 the dc bit is always cleared. the n bit always indicates the same state as the dc bit set in negative value mode by the cs[2:0] bits. see the negative value mode part above. the z bit always indicates th e same state as the dc bit set in zero value mode by the cs[2:0] bits. see the zero value mode part above. the v bit always indicates the same state as the dc bit se t in overflow mode by the cs[2:0] bits. see the overflow mode part above. the gt bit always indi cates the same state as the dc bit set in signed greater than mode by the cs[2:0] bits. see the signed greater than mode part above. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 135 of 1458 rej09b0033-0300 3.5.7 fixed-point multiply operation figure 3.16 shows the multiply operation flow. table 3.25 shows the variation of this type of operation and table 3.26 shows the correspondence between each operand and registers. the multiply operation of the dsp unit is single-wor d signed single-precision multiplication. these operations are executed in the dsp stage, as shown in figure 3.10. the dsp stage is the same stage as the ma stage in which memory access is performed. if a double-precision multiply operation is need ed, the cpu standard double-word multiply instructions can be made of use. 39 31 0 source 1 s 39 31 1 0 mac ignored s0 39 31 0 source 2 s destination 0 figure 3.16 fixed-point multiply operation flow table 3.25 variation of fixed-point multiply operation mnemonic function source 1 source 2 destination pmuls signed multiplication se sf dg section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 136 of 1458 rej09b0033-0300 table 3.26 correspondence be tween operands and registers register se sf dg a0 ? ? yes a1 yes yes yes m0 ? ? yes m1 ? ? yes x0 yes yes ? x1 yes ? ? y0 yes yes ? y1 ? yes ? note: the multiply operations basically generat e 32-bit operation results. so when a register providing the guard-bit parts are specified as a destination operand, the guard-bit parts will copy bit 31 of the operation result. the multiply operation of the dsp unit side is not integer but fixed-point arithmetic operation. so, the upper words of each multiplier and multiplicand are input into a mac unit as shown in figure 3.16. in the sh?s standard multiply operations, the lower words of both source operands are input into a mac unit. the operation result is also di fferent from the sh?s cas e. the sh?s multiply operation result is aligned to the lsb of the destination, but the fixed-point multiply operation result is aligned to the msb, so that the lsb of the fixed-point multiply operation result is always 0. the fixed-point multiply operation is executed in one cycle. multiply is always unconditional, but does not affect any condition code bits, dc, n, z, v, and gt , in dsr. ? overflow protection the s bit in sr is effective for this multiply operation in the dsp unit. see section 3.5.11, overflow protection, for details. if the s bit is 0, overflow occurs only when h'8000*h'8000 ((-1.0)*(-1.0)) operation is executed as signed fixed-point multiply. the result is h'00 8000 0000 but it does not mean (+1.0). if the s bit is 1, overflow is prevented and the result is h'00 7fff ffff. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 137 of 1458 rej09b0033-0300 3.5.8 shift operations shift operations can use either register or immediate value as the shift amount operand. other source and destination operands are specified by the register. there are two kinds of shift operations of arithmetic and logical shifts. table 3.27 shows the variation of this type of operation. the correspondence between each operand and registers, except fo r immediate operands, is the same as the alu fixed-point operations as shown in table 3.21. table 3.27 variation of shift operations mnemonic function source 1 source 2 destination psha sx, sy, dz arithmetic shift sx sy dz pshl sx, sy, dz logical shift sx sy dz psha #imm1, dz arithmetic shift with immediate. dz imm1 dz pshl #imm2, dz logical shift with immediate. dz imm2 dz ?32 <= imm1 <= +32, ?16 <= imm2 <= +16 (1) arithmetic shift figure 3.17 shows the arithmetic shift operation flow. dsr gt z n v dc updated 39 32 31 16 15 0 sy 39 32 31 16 15 0 0 shift out shift out (msb copy) ignored left shift right shift 39 32 31 23 22 16 imm1 60 15 0 shift amount data (source 2) >=0 <0 +32 to -32 figure 3.17 arithmetic shift operation flow section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 138 of 1458 rej09b0033-0300 note: the arithmetic shift operations are basically 40 -bit operation, that is, the 32 bits of the base precision and eight bits of the guard-bit parts. so the signed bit is copied to the guard- bit parts when a register not providing the guard-bit parts is specified as the source operand. when a register not providing the guard-bit parts is specified as a destination operand, the lower 32 bits of the operation result are input into the destination register. in this arithmetic shift operation, all bits of th e source 1 and destination operands are activated. the shift amount is specified by the source 2 operand as an inte ger data. the source 2 operand can be specified by either a register or immediate operand. the available shift range is from ?32 to +32. here, a negative value means the right shift, and a positive value means the left shift. it is possible for any source 2 operand to specify from ?64 to +63 but the result is unknown if an invalid shift value is specified. in case of a shift with an immediat e operand instruction, the source 1 operand must be the same register as the destination?s. this operation is executed in the dsp stage, as shown in figure 3.10 as well as in fixed-point operations. the dsp stage is the same stage as the ma stage in which memory access is performed. every time an arithmetic shift operation is execute d, the dc, n, z, v, and gt bits in dsr are basically updated in accordance with the operation result. in case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. in case of an unconditional operation, th ey are always updated in accord ance with the operation result. the definition of the dc bit is selected by the cs[2:0] (condition selection) bits in dsr. the dc bit result is: 1. carry or borrow mode: cs[2:0] = b'000 the dc bit indicates the last shifte d out data as the operation result. 2. negative value mode: cs[2:0] = b'001 the dc bit is set to 1 when the operation result is a negative value, and cleared to 0 when the operation result is zero or a positive value. 3. zero value mode: cs[2:0] = b'010 the dc bit is set when the operation result is zero; otherwise it is cleared. 4. overflow mode: cs[2:0] = b'011 the dc bit is set to 1 when an overflow occurs. 5. signed greater than mode: cs[2:0] = b'100 the dc bit is always cleared to 0. 6. signed greater than or equal mode: cs[2:0] = b'101 the dc bit is always cleared to 0. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 139 of 1458 rej09b0033-0300 the n bit always indicates the same state as the dc bit set in negative value mode by the cs[2:0] bits. see the negative value mode part above. the z bit always indicates th e same state as the dc bit set in zero value mode by the cs[2:0] bits. see the zero value mode part above. the v bit always indicates the same state as the dc bit se t in overflow mode by the cs[2:0] bits. see the overflow mode part above. the gt bit always indi cates the same state as the dc bit set in signed greater than mode by the cs[2:0] bits. see the signed greater than mode part above. ? overflow protection the s bit in sr is also effective for arithmetic shift operation in th e dsp unit. see section 3.5.11, overflow protection, for details. (2) logical shift figure 3.18 shows the logical shift operation flow. 39 32 31 16 15 0 sy 39 32 31 16 15 0 shift out shift out 0 0 cleared to 0 ignored left shift right shift 39 32 31 22 21 16 imm2 50 15 0 shift amount data (source 2) > = 0 < 0 +16 to -16 dsr gt z n v dc updated figure 3.18 logical shift operation flow as shown in figure 3.18, the logical shift operation uses the upper word of the source 1 operand and the destination operand. the lower word and guard-bit parts are ignored for the source operand and those of the destination operand ar e automatically cleared as in the alu logical operations. the shift amount is specified by the so urce 2 operand as an integer data. the source 2 operand can be specified by either the register or immediate operand. the available shift range is from ?16 to +16. here, a negative value means the right shift, and a positive value means the left shift. it is possible for any source 2 operand to specify from ?32 to +31, but the result is unknown if an invalid shift value is specified. in case of a shift with an immediate operand instruction, the source 1 operand must be the same register as the destination?s. these operations are executed in the dsp stage, as shown in figure 3.10. the dsp st age is the same stage as the ma stage in which memory access is performed. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 140 of 1458 rej09b0033-0300 every time a logical shift operati on is executed, the dc, n, z, v, and gt bits in dsr are basically updated in accordance with the operation result. in case of a conditional operation, they are not updated even though the specified condition is true and the operation is executed. in case of an unconditional operation, they are always updated in accordance with the operation result. the definition of the dc bit is selected by the cs[2:0] (condition selection) bits in dsr. the dc bit result is: 1. carry or borrow mode: cs[2:0] = b'000 the dc bit indicates the last shifted out data as the operation result. 2. negative value mode: cs[2:0] = b'001 bit 31 of the operation result is loaded into the dc bit. 3. zero value mode: cs[2:0] = b'010 the dc bit is set to 1 when the operation result is zero; otherwise it is cleared to 0. 4. overflow mode: cs[2:0] = b'011 the dc bit is always cleared to 0. 5. signed greater than mode: cs[2:0] = b'100 the dc bit is always cleared to 0. 6. signed greater than or equal mode: cs[2:0] = b'101 the dc bit is always cleared. the n bit always indicates the same state as the dc bit set in negative value mode by the cs[2:0] bits. see the negative value mode part above. the z bit always indicates th e same state as the dc bit set in zero value mode by the cs[2:0] bits. see the zero value mode part above. the v bit always indicates the same state as the dc bit set in overflow mode by the cs[2:0] bits, but it is always cleared in this oper ation. so is the gt bit. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 141 of 1458 rej09b0033-0300 3.5.9 most significant bit detection operation the pdmsb, most significant bit detection operation, is used to calculate the shift amount for normalization. figure 3.19 shows the pdmsb operation flow and table 3.28 shows the operation definition. table 3.29 shows the possible variations of this type of operation. the correspondence between each operand and registers is the same as for alu fixed-point operations, as shown in table 3.21. note: the result of the msb detection operation is basically 24 bits as well as alu integer operation, the upper 16 bits of the base precision and eight bits of the guard-bit parts. when a register not providing the guard-bit part s is specified as a de stination operand, the upper word of the operation result is input into the destination register. as shown in figure 3.19, the pdmsb operation uses all bits as a source operand, but the destination operand is treated as an integer op eration result because shift amount data for normalization should be integer data as descri bed in section 3.5.8, shift operations. these operations are executed in the dsp stage, as shown in figure 3.10. the dsp stage is the same stage as the ma stage in which memory access is performed. every time a pdmsb operation is executed, the dc, n, z, v, and gt bits in dsr are basically updated in accordance with the operation result. in case of a conditional operation, they are not updated, even though the specified condition is tr ue, and the operation is executed. in case of an unconditional operation, they are always updated with the operation result. 39 31 39 31 0 0 cleared to 0 priority encoder source 1 or 2 dsr gt z n v dc guard guard figure 3.19 pdmsb operation flow section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 142 of 1458 rej09b0033-0300 the definition of the dc bit is selected by the cs0 to cs2 (condition selection) bits in dsr. the dc bit result is (1) carry or borrow mode: cs[2:0] = b'000 the dc bit is always cleared to 0. (2) negative value mode: cs[2:0] = b'001 the dc bit is set when the operation result is a negative value, and cleared to 0 when the operation result is zero or a positive value. (3) zero value mode: cs[2:0] = b'010 the dc bit is set when the operation result is zero; otherwise it is cleared to 0. (4) overflow mode: cs[2:0] = b'011 the dc bit is always cleared to 0. (5) signed greater than mode: cs[2:0] = b'100 the dc bit is set to 1 when the operation result is a positive value; otherw ise it is cleared to 0. (6) signed greater than or equal mode: cs[2:0] = b'101 the dc bit is set to 1 when the operation result is zero or a positive value; otherwise it is cleared to 0. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 143 of 1458 rej09b0033-0300 table 3.28 operation definition of pdmsb source data result for dst guard bit upper word lower word guard bit upper word 39 38 ? 33 32 31 30 29 28 ? 3 2 1 0 39 to 32 31 to 22 21 20 19 18 17 16 decimal 0 0 ? 0 0 0 0 0 0 ? 0 0 0 0 all 0 all 0 0 1 1 1 1 1 +31 0 0 ? 0 0 0 0 0 0 ? 0 0 0 1 all 0 all 0 0 1 1 1 1 0 +30 0 0 ? 0 0 0 0 0 0 ? 0 0 1 * all 0 all 0 0 1 1 1 0 1 +29 0 0 ? 0 0 0 0 0 0 ? 0 1 * * all 0 all 0 0 1 1 1 0 0 +28 : : : 0 0 ? 0 0 0 0 0 1 ? * * * * all 0 all 0 0 0 0 0 1 0 +2 0 0 ? 0 0 0 0 1 * ? * * * * all 0 all 0 0 0 0 0 0 1 +1 0 0 ? 0 0 0 1 * * ? * * * * all 0 all 0 0 0 0 0 0 0 0 0 0 ? 0 0 1 * * * ? * * * * all 1 all 1 1 1 1 1 1 1 ?1 0 0 ? 0 1 * * * * ? * * * * all 1 all 1 1 1 1 1 1 0 ?2 : : : 0 1 ? * * * * * * ? * * * * all 1 all 1 1 1 1 0 0 0 ?8 1 0 ? * * * * * * ? * * * * all 1 all 1 1 1 1 0 0 0 ?8 : 1 1 ? 1 0 * * * * ? * * * * all 1 all 1 1 1 1 1 1 0 ?2 1 1 ? 1 1 0 * * * ? * * * * all 1 all 1 1 1 1 1 1 1 ?1 1 1 ? 1 1 1 0 * * ? * * * * all 0 all 0 0 0 0 0 0 0 0 1 1 ? 1 1 1 1 0 * ? * * * * all 0 all 0 0 0 0 0 0 1 +1 1 1 ? 1 1 1 1 1 0 ? * * * * all 0 all 0 0 0 0 0 1 0 +2 : : : 1 1 ? 1 1 1 1 1 1 ? 1 0 * * all 0 all 0 0 1 1 1 0 0 +28 1 1 ? 1 1 1 1 1 1 ? 1 1 0 * all 0 all 0 0 1 1 1 0 1 +29 1 1 ? 1 1 1 1 1 1 ? 1 1 1 0 all 0 all 0 0 1 1 1 1 0 +30 1 1 ? 1 1 1 1 1 1 ? 1 1 1 1 all 0 all 0 0 1 1 1 1 1 +31 note: * means don?t care. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 144 of 1458 rej09b0033-0300 table 3.29 variation of pdmsb operation mnemonic function source source 2 destination pdmsb msb detection sx ? dz ? sy dz the n bit always indicates the same state as the dc bit set in negative value mode by the cs[2:0] bits. see the negative value mode part above. the z bit always indicates th e same state as the dc bit set in zero value mode by the cs[2:0] bits. see the zero value mode part above. the v bit is always cleared. the gt bit always indicates the same state as the dc bit set in signed greater than mode by the cs[2:0] bits. see the signed greater than mode part above. 3.5.10 rounding operation the dsp unit provides the function that rounds from 32 bits to 16 bits. in case of providing guard- bit parts, it rounds from 40 bits to 24 bits. when a round instruction is executed, h'00008000 is added to the source operand data and then, the lower word is cleared. figure 3.20 shows the rounding operation flow and figure 3.21 shows the operation definition. table 3.30 shows the variation of this type of operation. the corresp ondence between each operand and registers is the same as alu fixed-point operations as shown in table 3.21. as shown in figure 3.21, the rounding operation uses full-size data for both source and destination operands. these operations are executed in the ds p stage as shown in figure 3.10. the dsp stage is the same stage as the ma stage in which memory access is performed. the rounding operation is always executed unconditionally, so that the dc, n, z, v, and gt bits in dsr are always updated in acco rdance with the operatio n result. the definition of the dc bit is selected by the cs0 to cs2 (condition selection) bits in dsr. the result of these condition code bits is the same as the alu-fixed point arithmetic operations. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 145 of 1458 rej09b0033-0300 31 31 0 alu h'00008000 39 39 0 cleared to 0 source 1 or 2 dsr gt z n v dc guard guard figure 3.20 rounding operation flow 0 h'00 0002 h'00 0001 h'00 0001 8000 h'00 0002 0000 h'00 0002 8000 rounded result analog value true value figure 3.21 definition of rounding operation table 3.30 variation of rounding operation mnemonic function source 1 source 2 destination prnd rounding sx ? dz ? sy dz ? overflow protection the s bit in sr is effective fo r any rounding operations in the dsp unit. see section 3.5.11, overflow protection, for details. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 146 of 1458 rej09b0033-0300 3.5.11 overflow protection the s bit in sr is effective for any arithmetic operations executed in the dsp unit, including the sh?s standard multiply and mac operations. the s bit in sr is used as the overflow protection enable bit. the arithmetic opera tion overflows when th e operation result exceeds the range of two?s complement representation without guard-bit parts. table 3.31 shows the definition of overflow protection for fixed-point arithmetic operations, including fixed-point signed by signed multiplication described in section 3.5.7, fixed-point multiply operation. table 3.32 shows the definition of overflow protection for integer arithmetic operations. the lower word of the saturation value of the integer arithmetic operatio n is don?t care. lower word value cannot be guaranteed. when the overflow protection is ef fective, overflow never occurs. so, the v bit is cleared, and the dc bit is also cleared when the overflow mode is selected by the cs[2:0] bits. table 3.31 definition of overflow protect ion for fixed-point arithmetic operations sign overflow condition fixed value hex representation positive result > 1 ? 2 ?31 1 ? 2 ?31 h'00 7fff ffff negative result < ?1 ?1 h'ff 8000 0000 table 3.32 definition of overflow prot ection for integer arithmetic operations sign overflow condition fixed value hex representation positive result > 2 15 ? 1 2 15 ? 1 00 7fff **** negative result < ?2 15 ?2 15 ff 8000 **** note: * means don?t care. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 147 of 1458 rej09b0033-0300 3.5.12 local data move instruction the dsp unit of this lsi provides additional two independent registers, macl and mach, in order to support cpu standard multiply/mac operations. they can be also used as temporary storage registers by local data move instructions between mach/l and other dsp registers. figure 3.22 shows the flow of seven local data move instructions. table 3.33 shows the variation of this type of instruction. plds psts cannot be used x0 y0 mach macl x1 y1 m1 a1 m0 a0 a0g a1g dsr figure 3.22 local data move instruction flow table 3.33 variation of local data move operations mnemonic function operand plds data move from dsp register to macl/mach dz psts data move from macl/mach to dsp register dz this instruction is very similar to other transfer instructions. if either the a0 or a1 register is specified as the destination operand of psts, the signed bit is sign-extended and copied into the corresponding guard-bit parts, a0g or a1g. the dc bit in dsr and other condition code bits are not updated regardless of the instruction result. this instruction can operate as a conditional. this instruction can operate with movx and movy in parallel. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 148 of 1458 rej09b0033-0300 3.5.13 operand conflict when an identical destination operand is specified with multiple parallel instructions, data conflict occurs. table 3.34 shows th e correspondence between eac h operand and registers. table 3.34 correspondence be tween operands and registers x-memory load y-memory load 6-instruction alu 3-instruction multiply 3-instruction alu ax ix dx ay iy dy sx sy du se sf dg sx sy dz a0 * 1 * 2 * 2 * 1 * 1 a1 * 1 * 2 * 1 * 1 * 2 * 1 * 1 m0 * 1 * 1 * 1 * 1 m1 * 1 * 1 * 1 * 1 x0 * 2 * 1 * 2 * 1 * 1 * 1 * 2 x1 * 2 * 1 * 1 * 1 * 2 y0 * 2 * 1 * 2 * 1 * 1 * 1 * 2 dsp registers y1 * 2 * 1 * 1 * 1 * 2 notes: 1. registers available for operands 2. registers available for operand s (when there is operand conflict) there are three cases of operand conflict problems. ? when alu operation and multiply instructions specify the same destination operand (du and dg) ? when x-memory load and alu operation specify the same destination operand (dx and du, or dz) ? when y-memory load and alu operation specify the same destination operand (dy and du, or dz) in these cases above, the result is not guaranteed. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 149 of 1458 rej09b0033-0300 3.6 dsp extended function instruction set 3.6.1 cpu extended instructions table 3.35 dsp mode extended system control instructions instruction instruction code operation execution states t bit setrc #imm 10000010iiiiiiii imm rc (of sr) 1 ? setrc rn 0100nnnn00010100 rn[11:0] rc(of sr) 1 ? ldrs @(disp,pc) 10001100dddddddd (disp x 2 + pc) rs 1 ? ldre @(disp,pc) 10001110dddddddd (disp x 2 + pc) re 1 ? stc mod,rn 0000nnnn01010010 mod rn 1 ? stc rs,rn 0000nnnn01100010 rs rn 1 ? stc re,rn 0000nnnn01110010 re rn 1 ? sts dsr,rn 0000nnnn01101010 dsr rn 1 ? sts a0,rn 0000nnnn01111010 a0 rn 1 ? sts x0,rn 0000nnnn10001010 x0 rn 1 ? sts x1,rn 0000nnnn10011010 x1 rn 1 ? sts y0,rn 0000nnnn10101010 y0 rn 1 ? sts y1,rn 0000nnnn10111010 y1 rn 1 ? sts.l dsr,@-rn 0100nnnn01100010 rn-4 rn, dsr (rn) 1 ? sts.l a0,@-rn 0100nnnn01110010 rn-4 rn, a0 (rn) 1 ? sts.l x0,@-rn 0100nnnn10000010 rn-4 rn, x0 (rn) 1 ? sts.l x1,@-rn 0100nnnn10010010 rn-4 rn, x1 (rn) 1 ? sts.l y0,@-rn 0100nnnn10100010 rn-4 rn, y0 (rn) 1 ? sts.l y1,@-rn 0100nnnn10110010 rn-4 rn, y1 (rn) 1 ? stc.l mod,@-rn 0100nnnn01010011 rn-4 rn, mod (rn) 1 ? stc.l rs,@-rn 0100nnnn01100011 rn-4 rn, rs (rn) 1 ? stc.l re,@-rn 0100nnnn01110011 rn-4 rn, re (rn) 1 ? lds.l @rn + ,dsr 0100nnnn01100110 (rn) dsr, rn + 4 rn 1 ? lds.l @rn + ,a0 0100nnnn01110110 (rn) a0, rn + 4 rn 1 ? lds.l @rn + ,x0 0100nnnn10000110 (rn) x0, rn + 4 rn 1 ? lds.l @rn + ,x1 0100nnnn10010110 (rn) x1, rn + 4 rn 1 ? lds.l @rn + ,y0 0100nnnn10100110 (rn) y0, rn + 4 rn 1 ? section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 150 of 1458 rej09b0033-0300 instruction instruction code operation execution states t bit lds.l @rn + ,y1 0100nnnn10110110 (rn) y1, rn + 4 rn 1 ? ldc.l @rn + ,mod 0100nnnn01010111 (rn) mod, rn + 4 rn 4 ? ldc.l @rn + ,rs 0100nnnn01100111 (rn) rs, rn + 4 rn 4 ? ldc.l @rn + ,re 0100nnnn01110111 (rn) re, rn + 4 rn 4 ? lds rn,dsr 0100nnnn01101010 rn dsr 1 ? lds rn,a0 0100nnnn01111010 rn a0 1 ? lds rn,x0 0100nnnn10001010 rn x0 1 ? lds rn,x1 0100nnnn10011010 rn x1 1 ? lds rn,y0 0100nnnn10101010 rn y0 1 ? lds rn,y1 0100nnnn10111010 rn y1 1 ? ldc rn,mod 0100nnnn01011110 rn mod 4 ? ldc rn,rs 0100nnnn01101110 rn rs 4 ? ldc rn,re 0100nnnn01111110 rn re 4 ? section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 151 of 1458 rej09b0033-0300 3.6.2 double-data tr ansfer instructions table 3.36 double data transfer instruction instruction instruction code operation execution states dc nopx 1111000*0*0*00** x memory no access 1 ? movx.w @ax,dx 111100a*d*0*01** (ax) msw of dx, 0 lsw of dx 1 ? movx.w @ax+,dx 111100a*d*0*10** (ax) msw of dx, 0 lsw of dx, ax + 2 ax 1 ? movx.w @ax+ix,dx 111100a*d*0*11** (ax) msw of dx, 0 lsw of dx, ax + ix ax 1 ? movx.w da,@ax 111100a*d*1*01** msw of da (ax) 1 ? movx.w da,@ax+ 111100a*d*1*10** msw of da (ax), ax + 2 ax 1 ? x memory data transfer movx.w da,@ax+ix 111100a*d*1*11** msw of da (ax), ax + ix ax 1 ? nopy 111100*0*0*0**00 y memory no access 1 ? movy.w @ay,dy 111100*a*d*0**01 (ay) msw of dy, 0 lsw of dy 1 ? movy.w @ay+,dy 111100*a*d*0**10 (ay) msw of dy, 0 lsw of dy, ay + 2 ay 1 ? movy.w @ay+iy,dy 111100*a*d*0**11 (ay) msw of dy, 0 lsw of dy, ay + iy ay 1 ? movy.w da,@ay 111100*a*d*1**01 msw of da (ay) 1 ? movy.w da,@ay+ 111100*a*d*1**10 msw of da (ay), ay + 2 ay 1 ? y memory data transfer movy.w da,@ay+iy 111100*a*d*1**11 msw of da (ay), ay + iy ay 1 ? section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 152 of 1458 rej09b0033-0300 3.6.3 single-data transfer instructions table 3.37 single data transfer instructions instruction instruction code operation execution states dc category movs.w @-as,ds 111101aadddd0000 as-2 as, (as) msw of ds, 0 lsw of ds 1 ? movs.w @as,ds 111101aadddd0100 (as) msw of ds, 0 lsw of ds 1 ? movs.w @as+,ds 111101aadddd1000 (as) msw of ds, 0 lsw of ds, as + 2 as 1 ? movs.w @as+ix,ds 111101aadddd1100 (asc) msw of ds, 0 lsw of ds, as + ix as 1 ? movs.w ds,@-as 111101aadddd0001 as-2 as, msw of ds (as) 1 ? * movs.w ds,@as 111101aadddd0101 msw of ds (as) 1 ? * movs.w ds,@as+ 111101aadddd1001 msw of ds (as), as + 2 as 1 ? * movs.w ds,@as+ix 111101aadddd1101 msw of ds (as), as + ix as 1 ? * movs.l @-as,ds 111101aadddd0010 as-4 as, (as) ds 1 ? movs.l @as,ds 111101aadddd0110 (as) ds 1 ? movs.l @as+,ds 111101aadddd1010 (as) ds, as + 4 as 1 ? movs.l @as+ix,ds 111101aadddd1110 (as) ds, as + ix as 1 ? movs.l ds,@-as 111101aadddd0011 as-4 as, ds (as) 1 ? movs.l ds,@as 111101aadddd0111 ds (as) 1 ? movs.l ds,@as+ 111101aadddd1011 ds (as), as + 4 as 1 ? movs.l ds,@as+ix 111101aadddd1111 ds (as), as + ix as 1 ? note: * if guard bit registers a0g and a1g are specified in source operand ds, the data is output to the ldb[7:0] bus and the sign bit is copied into the upper bits, [31:8]. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 153 of 1458 rej09b0033-0300 the correspondence between dsp da ta transfer operands and registers is shown in table 3.38. table 3.38 correspondence between dsp data transf er operands and registers register ax ix dx ay iy dy da as ds r0 r1 r2 (as2) yes r3 (as3) yes r4 (ax0) yes yes r5 (ax1) yes yes r6 (ay0) yes r7 (ay1) yes r8 (ix) yes sh register r9 (iy) yes a0 yes yes a1 yes yes m0 yes m1 yes x0 yes yes x1 yes yes y0 yes yes y1 yes yes a0g yes dsp register a1g yes section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 154 of 1458 rej09b0033-0300 3.6.4 dsp operation instructions table 3.39 dsp operation instructions instruction instruction code operation execution states dc pmuls se,sf, dg 111110 ********** 0100eeff0000gg00 se * sf dg (signed) 1 ? padd sx,sy,du pmuls se,sf,dg 111110 ********** 0111eeffxxyygguu sx + sy du se * sf dg (signed) 1 * psub sx,sy,du pmuls se,sf,dg 111110 ********** 0110eeffxxyygguu sy-sy du se * sf dg (signed) 1 * padd sx,sy,dz 111110 ********** 10110001xxyyzzzz sx + sy dz 1 * dct padd sx,sy,dz 111110 ********** 10110010xxyyzzzz if dc = 1, sx + sy dz if dc = 0, nop 1 ? dcf padd sx,sy,dz 111110 ********** 10110011xxyyzzzz if dc = 0, sx + sy dz if dc = 1, nop 1 ? psub sx,sy,dz 111110 ********** 10100001xxyyzzzz sx-sy dz 1 * dct psub sx,sy,dz 111110 ********** 10100010xxyyzzzz if dc = 1, sx-sy dz if dc = 0, nop 1 ? dcf psub sx,sy,dz 111110 ********** 10100011xxyyzzzz if dc = 0, sx-sy dz if dc = 1, nop 1 ? psha sx,sy,dz 111110 ********** 10010001xxyyzzzz if sy >= 0, sx< section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 155 of 1458 rej09b0033-0300 instruction instruction code operation execution states dc dct pshl sx,sy,dz 111110 ********** 10000010xxyyzzzz if dc = 1 & sy >= 0, sx< section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 156 of 1458 rej09b0033-0300 instruction instruction code operation execution states dc dcf pdmsb sy,dz 111110 ********** 1011111100yyzzzz if dc = 0, normalization count shift value sy dz if dc=1, nop 1 ? pinc sx,dz 111110 ********** 10011001xx00zzzz msw of sx + 1 dz 1 * pinc sy,dz 111110 ********** 1011100100yyzzzz msw of sy + 1 dz 1 * dct pinc sx,dz 111110 ********** 10011010xx00zzzz if dc = 1, msw of sx + 1 dz if dc = 0, nop 1 ? dct pinc sy,dz 111110 ********** 1011101000yyzzzz if dc = 1, msw of sy + 1 dz if dc = 0, nop 1 ? dcf pinc sx,dz 111110 ********** 10011011xx00zzzz if dc = 0, msw of sx + 1 dz if dc = 1, nop 1 ? dcf pinc sy,dz 111110 ********** 1011101100yyzzzz if dc = 0, msw of sy + 1 dz if dc = 1, nop 1 ? pneg sx,dz 111110 ********** 11001001xx00zzzz 0-sx dz 1 * pneg sy,dz 111110 ********** 1110100100yyzzzz 0-sy dz 1 * dct pneg sx,dz 111110 ********** 11001010xx00zzzz if dc = 1, 0-sx dz if dc = 0, nop 1 ? dct pneg sy,dz 111110 ********** 1110101000yyzzzz if dc = 1, 0-sy dz if dc = 0, nop 1 ? dcf pneg sx,dz 111110 ********** 11001011xx00zzzz if dc = 0, 0-sx dz if dc = 1, nop 1 ? dcf pneg sy,dz 111110 ********** 1110101100yyzzzz if dc = 0, 0-sy dz if dc = 1, nop 1 ? por sx,sy,dz 111110 ********** 10110101xxyyzzzz sx | sy dz 1 * dct por sx,sy,dz 111110 ********** 10110110xxyyzzzz if dc = 1, sx | sy dz if dc = 0, nop 1 ? dcf por sx,sy,dz 111110 ********** 10110111xxyyzzzz if dc = 0, sx | sy dz if dc = 1, nop 1 ? section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 157 of 1458 rej09b0033-0300 instruction instruction code operation execution states dc pand sx,sy,dz 111110 ********** 10010101xxyyzzzz sx & sy dz 1 * dct pand sx,sy,dz 111110 ********** 10010110xxyyzzzz if dc = 1, sx & sy dz if dc = 0, nop 1 ? dcf pand sx,sy,dz 111110 ********** 10010111xxyyzzzz if dc = 0, sx & sy dz if dc = 1, nop 1 ? pxor sx,sy,dz 111110 ********** 10100101xxyyzzzz sx ^ sy dz 1 * dct pxor sx,sy,dz 111110 ********** 10100110xxyyzzzz if dc = 1, sx ^ sy dz if dc = 0, nop 1 ? dcf pxor sx,sy,dz 111110 ********** 10100111xxyyzzzz if dc = 0, sx ^ sy dz if dc = 1, nop 1 ? pdec sx,dz 111110 ********** 10001001xx00zzzz sx [39:16]-1 dz 1 * dct pdec sx,dz 111110 ********** 10001010xx00zzzz if dc = 1, sx [39:16]-1 dz if dc = 0, nop 1 ? dcf pdec sx,dz 111110 ********** 10001011xx00zzzz if dc = 0, sx [39:16]-1 dz if dc = 1, nop 1 ? pdec sy,dz 111110 ********** 1010100100yyzzzz sy [31:16]-1 dz 1 * dct pdec sy,dz 111110 ********** 1010101000yyzzzz if dc = 1, sy [31:16]-1 dz if dc = 0, nop 1 ? dcf pdec sy,dz 111110 ********** 1010101100yyzzzz if dc = 0, sy [31:16]-1 dz if dc = 1, nop 1 ? pclr dz 111110 ********** 100011010000zzzz h ' 00000000 dz 1 * dct pclr dz 111110 ********** 100011100000zzzz if dc = 1, h ' 00000000 dz if dc = 0, nop 1 ? dcf pclr dz 111110 ********** 100011110000zzzz if dc = 0, h ' 00000000 dz if dc = 1, nop 1 ? psha #imm,dz 111110 ********** 00010iiiiiiizzzz if imm>=0, dz< section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 158 of 1458 rej09b0033-0300 instruction instruction code operation execution states dc pshl #imm,dz 111110 ********** 00000iiiiiiizzzz if imm>=0, dz< section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 159 of 1458 rej09b0033-0300 instruction instruction code operation execution states dc pabs sx,dz 111110 ********** 10001000xx00zzzz if sx<0, 0-sx dz if sx>=0, sx dz 1 * pabs sy,dz 111110 ********** 1010100000yyzzzz if sy<0, 0-sy dz if sy>=0, sy dz 1 * prnd sx,dz 111110 ********** 10011000xx00zzzz sx + h ' 00008000 dz lsw of dz h ' 0000 1 * prnd sy,dz 111110 ********** 1011100000yyzzzz sy + h ' 00008000 dz lsw of dz h ' 0000 1 * note: * see table 3.19. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 160 of 1458 rej09b0033-0300 3.6.5 operation code map in dsp mode table 3.40 shows the operation code map including an instruction codes extended in the dsp mode. table 3.40 operation code map instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0000 rn fx 0000 0000 rn fx 0001 0000 rn 00md 0010 stc sr, rn stc gbr, rn stc vbr, rn stc ssr, rn 0000 rn 01md 0010 stc spc, rn stc mod, rn stc rs, rn stc re, rn 0000 rn 10md 0010 stc r0_bank, rn stc r1_bank, rn stc r2_bank, rn stc r3_bank, rn 0000 rn 11md 0010 stc r4_bank, rn stc r5_bank, rn stc r6_bank, rn stc r7_bank, rn 0000 rm 00md 0011 bsrf rm braf rm 0000 rm 10md 0011 pref @rm 0000 rn rm 01md mov.b rm, @(r0, rn) mov.w rm, @(r0, rn) mov.l rm,@(r0, rn) mul.l rm, rn 0000 0000 00md 1000 clrt sett clrmac ldtlb 0000 0000 01md 1000 clrs sets 0000 0000 10md 1000 0000 0000 11md 1000 0000 0000 fx 1001 nop div0u 0000 0000 fx 1010 0000 0000 fx 1011 rts sleep rte 0000 rn fx 1000 0000 rn fx 1001 movt rn 0000 rn 00md 1010 sts mach, rn sts macl, rn sts pr, rn 0000 rn 01md 1010 sts dsr, rn sts a0, rn 0000 rn 10md 1010 sts x0, rn sts x1, rn sts y0, rn sts y1, rn 0000 rn fx 1011 section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 161 of 1458 rej09b0033-0300 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0000 rn rm 11md mov. b @(r0, rm), rn mov.w @(r0, rm), rn mov.l @(r0, rm), rn mac.l @rm+,@rn+ 0001 rn rm disp mov.l rm, @(disp:4, rn) 0010 rn rm 00md mov.b rm, @rn mov.w rm, @rn mov.l rm, @rn 0010 rn rm 01md mov.b rm, @ ? rn mov.w rm, @ ? rn mov.l rm, @ ? rn div0s rm, rn 0010 rn rm 10md tst rm, rn and rm, rn xor rm, rn or rm, rn 0010 rn rm 11md cmp/str rm, rn xtrct rm, rn mulu.w rm, rn mulsw rm, rn 0011 rn rm 00md cmp/eq rm, rn cmp/hs rm, rn cmp/ge rm, rn 0011 rn rm 01md div1 rm, rn dmulu.l rm,rn cmp/hi rm, rn cmp/gt rm, rn 0011 rn rm 10md sub rm, rn subc rm, rn subv rm, rn 0011 rn rm 11md add rm, rn dmuls.l rm,rn addc rm, rn addv rm, rn 0100 rn fx 0000 shll rn dt rn shal rn 0100 rn fx 0001 shlr rn cmp/pz rn shar rn 0100 rn fx 0010 sts.l mach, @ ? rn sts.l macl, @ ? rn sts.l pr, @ ? rn 0100 rn 00md 0011 stc.l sr, @ ? rn stc.l gbr, @ ? rn stc.l vbr, @ ? rn stc.l ssr, @ ? rn 0100 rn 01md 0011 stc.l spc, @ ? rn stc.l mod, @ ? rn stc.l rs, @ ? rn stc.l re, @ ? rn 0100 rn 10md 0011 stc.l r0_bank, @ ? rn stc.l r1_bank, @ ? rn stc.l r2_bank, @ ? rn stc.l r3_bank, @ ? rn 0100 rn 11md 0011 stc.l r4_bank, @ ? rn stc.l r5_bank, @ ? rn stc.l r6_bank, @ ? rn stc.l r7_bank, @ ? rn 0100 rn fx 0100 rotl rn setrc rn rotcl rn 0100 rn fx 0101 rotr rn cmp/pl rn rotcr rn 0100 rm 00md 0110 lds.l @rm+, mach lds.l @rm+, macl lds.l @rm+, pr 0100 rm 01md 0110 lds.l @rm+, dsr lds.l @rm+, a0 0100 rm 10md 0110 lds.l @rm+, x0 lds.l @rm+, x1 lds.l @rm+, y0 lds.l @rm+, y1 section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 162 of 1458 rej09b0033-0300 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 0100 rm 00md 0111 ldc.l @rm+, sr ldc.l @rm+, gbr ldc.l @rm+, vbr ldc.l @rm+, ssr 0100 rm 01md 0111 ldc.l @rm+, spc ldc.l @rm+, mod ldc.l @rm+, rs ldc.l @rm+, re 0100 rm 10md 0111 ldc.l @rm+, r0_bank ldc.l @rm+, r1_bank ldc.l @rm+, r2_bank ldc.l @rm+, r3_bank 0100 rm 11md 0111 ldc.l @rm+, r4_bank ldc.l @rm+, r5_bank ldc.l @rm+, r6_bank ldc.l @rm+, r7_bank 0100 rn fx 1000 shll2 rn shll8 rn shll16 rn 0100 rn fx 1001 shlr2 rn shlr8 rn shlr16 rn 0100 rm 00md 1010 lds rm, mach lds rm, macl lds rm, pr 0100 rm 01md 1010 lds rm, dsr lds rm, a0 0100 rm 10md 1010 lds rm, x0 lds rm, x1 lds rm, y0 lds rm, y1 0100 rm/rn fx 1011 jsr @rm tas.b @rn jmp @rm 0100 rn rm 1100 shad rm, rn 0100 rn rm 1101 shld rm, rn 0100 rm 00md 1110 ldc rm, sr ldc rm, gbr ldc rm, vbr ldc rm, ssr 0100 rm 01md 1110 ldc rm, spc ldc rm, mod ldc rm, rs ldc rm, re 0100 rm 10md 1110 ldc rm, r0_bank ldc rm, r1_bank ldc rm, r2_bank ldc rm, r3_bank 0100 rm 11md 1110 ldc rm, r4_bank ldc rm, r5_bank ldc rm, r6_bank ldc rm, r7_bank 0100 rn rm 1111 mac.w @rm+, @rn+ 0101 rn rm disp mov.l @ (disp:4, rm), rn 0110 rn rm 00md mov.b @rm, rn mov.w @rm, rn mov.l @rm, rn mov rm, rn 0110 rn rm 01md mov.b @rm+, rn mov.w @rm+, rn mov.l @rm+, rn not rm, rn 0110 rn rm 10md swap.b rm, rn swap.w rm, rn negc rm, rn neg rm, rn 0110 rn rm 11md extu.b rm, rn extu.w rm, rn exts.b rm, rn exts.w rm, rn 0111 rn imm add #imm : 8, rn rn disp 1000 00md imm mov.b r0, @(disp: 4, rn) mov.w r0, @(disp: 4, rn) setrc #imm section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 163 of 1458 rej09b0033-0300 instruction code fx: 0000 fx: 0001 fx: 0010 fx: 0011 to 1111 msb lsb md: 00 md: 01 md: 10 md: 11 1000 01md rm disp mov.b @(disp:4, rm), r0 mov.w @(disp: 4, rm), r0 1000 10md imm/disp cmp/eq #imm:8, r0 bt disp: 8 bf disp: 8 1000 11md imm/disp ldrs @(disp:8,pc) bt/s disp: 8 ldre @(disp:8,pc) bf/s disp: 8 1001 rn disp mov.w @ (disp : 8, pc), rn 1010 disp bra disp : 12 1011 disp bsr disp: 12 1100 00md imm/disp mov.b r0, @(disp: 8, gbr) mov.w r0, @(disp: 8, gbr) mov.l r0, @(disp: 8, gbr) trapa #imm: 8 1100 01md disp mov.b @(disp: 8, gbr), r0 mov.w @(disp: 8, gbr), r0 mov.l @(disp: 8, gbr), r0 mova @(disp: 8, pc), r0 1100 10md imm tst #imm: 8, r0 and #imm: 8, r0 xor #imm: 8, r0 or #imm: 8, r0 1100 11md imm tst.b #imm: 8, @(r0, gbr) and.b #imm: 8, @(r0, gbr) xor.b #imm: 8, @(r0, gbr) or.b #imm: 8, @(r0, gbr) 1101 rn disp mov.l @(disp: 8, pc), rn 1110 rn imm mov #imm:8, rn 1111 00 ** ******** movx.w, movy.w double data transfer instruction 1111 01 ** ******** movs.w, movs.l single data transfer instruction 1111 10 ** ******** movx.w, movy.w double data transfer instruction, with dsp parallel operation instruction (32- bit instruction ) 1111 11 ** ******** notes: 1. for details, refer to t he sh-3/sh-3e/sh3-dsp software manual. 2. instructions in the hatched areas are d sp extended instructions. these instructions can be executed only when the dsp bit in the sr register is set to 1. section 3 dsp operating unit rev. 3.00 jan. 18, 2008 page 164 of 1458 rej09b0033-0300 section 4 memory management unit (mmu) mmus300s_000020020300 rev. 3.00 jan. 18, 2008 page 165 of 1458 rej09b0033-0300 section 4 memory management unit (mmu) this lsi has an on-chip memory management unit (mmu) that supports a virtual memory system. the on-chip translation look-aside buffer (tlb ) caches information for user-created address translation tables located in exte rnal memory. it enables high-speed translation of virtual addresses into physical addresses. address translation uses the paging system and supports two page sizes (1 kbyte or 4 kbytes). the access rights to virtual addr ess space can be set for each of the privileged and user modes to provide memory protection. 4.1 role of mmu the mmu is a feature designed to make efficient use of physical memory. as shown in figure 4.1, if a process is smaller in size than the physical memory, the entire pro cess can be mapped onto physical memory. however, if the pr ocess increases in size to the exte nt that it no longer fits into physical memory, it becomes necessary to partiti on the process and to map those parts requiring execution onto memory as occasio n demands (figure 4.1 (1)). having the process itself consider this mapping onto physical memory would impose a large burden on the process. to lighten this burden, the idea of virtual memory was born as a means of performing en bloc mapping onto physical memory (figure 4.1 (2)). in a virtual memory system, substantially more virtual memory than physical memory is provided, and the process is mapped onto this virtual memory. thus a process only has to consider operation in virtual memory. mapping from virtual memory to physical memory is handled by the mmu. the mmu is normally controlled by the operating system, switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion. switching of physical memory is performed via secondary storage, etc. the virtual memory system that cam e into being in this way is particularly effective in a time- sharing system (tss) in which a number of processes are running simultaneously (figure 4.1 (3)). if processes running in a tss had to take mapping onto virtual memory into consideration while running, it would not be possible to increase efficiency. virtual memory is thus used to reduce this load on the individual processes and so improve efficiency (figure 4.1 (4)). in the virtual memory system, virtual memory is allocated to each process. the task of the mmu is to perform efficient mapping of these virtual memory areas onto physical memory. it also has a memory protection feature that prevents one proce ss from inadvertently accessing anot her process?s physical memory. when address translation from virtual memory to physical memory is performed using the mmu, it may occur that the relevant translation information is not recorded in the mmu, with the result that one process may inadvertently access the virtual memory allocated to another process. in this case, the mmu will generate an exception, change the physical memory mapping, and record the new address translation information. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 166 of 1458 rej09b0033-0300 although the functions of the mmu could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would result in poor efficiency. for this reason, a buffer for address translation (translation look-aside buffer: tlb) is provided in hardware to hold frequently used address translation information. the tlb can be described as a cach e for storing address translati on information. unlike cache memory, however, if address translation fails, that is, if an exception is generated, switching of address translation information is normally pe rformed by software. this makes it possible for memory management to be performed flexibly by software. the mmu has two methods of mapping from virtual memory to physical memory: a paging method using fixed-length address translation, and a segment method using variable-length address translation. with the paging method, the unit of translation is a fixed-size address space (usually of 1 to 64 kbytes) called a page. in the following text, the address space in virtual memory is referred to as virtual address space, and address space in physical me mory as physical memory space. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 167 of 1458 rej09b0033-0300 process 1 physical memory physical memory process 1 mmu physical memory process 1 process 3 process 2 process 1 process 1 process 2 process 3 virtual memory mmu (1) (2) (3) (4) physical memory physical memory virtual memory figure 4.1 mmu functions section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 168 of 1458 rej09b0033-0300 4.1.1 mmu of this lsi (1) virtual address space this lsi supports a 32-bit virtua l address space that en ables access to a 4-gbyte address space. as shown in figures 4.2 and 4.3, the virtual address space is divide d into several areas. in privileged mode, a 4-gbyte space comprising areas p0 to p4 ar e accessible. in user mode, a 2-gbyte space of u0 area is accessible, and a 16-mbyte space of uxy area is also accessible if the dsp bit in the sr register is set to 1. access to any area (excludi ng the u0 area and uxy area) in user mode will result in an address error. if the mmu is enabled by setting the at bit in th e mmucr register to 1, p0, p3, and u0 areas can be used as any physical addr ess area in 1- or 4-kbyte page units. by using an 8-bit address space identifier, p0, p2, and u0 ar eas can be increased to up to 256 areas. mapping from virtual address to 29-bit physi cal address can be achieved by the tlb. (a) p0, p3, and u0 areas the p0, p3, and u0 areas can be address translated by the tlb and can be accessed through the cache. if the mmu is enabled, these areas can be ma pped to any physical address space in 1- or 4- kbyte page units via the tlb. if the ce bit in th e cache control register (ccr1) is set to 1 and if the corresponding cache enable bit (c bit) of the tlb entry is set to 1, access via the cache is enabled. if the mmu is disabled, replacing the upper three bits of an address in these areas with 0s creates the address in the correspo nding physical address space. if the ce bit in the ccr1 register is set to 1, access via the cache is enabled. when the cache is used, either the copy-back or write- through mode is selected for wr ite access via the wt bit in ccr1. if these areas are mapped to the on-chip module co ntrol register area or on-chip memory area in area 1 in the physical address space via the tlb, the c bit of the corresponding page must be cleared to 0. (b) p1 area the p1 area can be accessed via the cache and canno t be address-translated by the tlb. whether the mmu is enabled or not, replaci ng the upper three bits of an address in these areas with 0s creates the address in the corres ponding physical addre ss space. use of the cach e is determined by the ce bit in the cache control re gister (ccr1). when the cache is used, either the copy-back or write-through mode is selected for write access by the cb bit in the ccr1 register. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 169 of 1458 rej09b0033-0300 (c) p2 area the p2 area cannot be accessed via the cache and cannot be address-tran slated by the tlb. whether the mmu is enabled or not, replacing the upper three bits of an address in this area with 0s creates the address in the corr esponding physical address space. (d) p4 area the p4 area is mapped to the on-chip i/o of th is lsi. this area cannot be accessed via the cache and cannot be addres s-translated by the tlb. figure 4.4 show s the configuration of the p4 area. h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff p0 area cacheable address translation possible u0 area cacheable address translation possible uxy area * p1 area cacheable address translation not possible p2 area non-cacheable address translation not possible p3 area cacheable address translation possible p4 area non-cacheable address translation not possible address error address error h'0000 0000 h'8000 0000 h'a500 0000 h'a5ff ffff h'ffff ffff h'0000 0000 privileged mode user mode area 0 area 1 area 2 area 3 area 4 area 5 area 7 area 6 external address space note: only exists when sr.dsp = 1 256 256 figure 4.2 virtual add ress space (mmucr.at = 1) section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 170 of 1458 rej09b0033-0300 h'8000 0000 h'a000 0000 h'c000 0000 h'e000 0000 h'ffff ffff p0 area cacheable u0 area cacheable uxy area * p1 area cacheable p2 area non-cacheable p3 area cacheable p4 area non-cacheable address error address error h'0000 0000 h'8000 0000 h'a500 0000 h'a5ff ffff h'ffff ffff h'0000 0000 privileged mode user mode area 0 area 1 area 2 area 3 area 4 area 5 area 7 area 6 external address space note: only exists when sr.dsp = 1 figure 4.3 virtual add ress space (mmucr.at = 0) section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 171 of 1458 rej09b0033-0300 h'f000 0000 h'f100 0000 h'f200 0000 h'f300 0000 h'f400 0000 h'ffff ffff h'fc00 0000 reserved reserved cache address array cache data array tlb address array tlb data array h'e000 0000 control register area figure 4.4 p4 area the area from h'f000 0000 to h'f0ff ffff is fo r direct access to the cache address array. for more information, see section 5.4, memory-mapped cache. the area from h'f100 0000 to h'f1ff ffff is for direct access to the cache data array. for more information, see section 5.4, memory-mapped cache. the area from h'f200 0000 to h'f2ff ffff is for direct access to the tlb address array. for more information, see section 4.6, memory-mapped tlb. the area from h'f300 0000 to h'f3ff ffff is fo r direct access to the tlb data array. for more information, see section 4.6, memory-mapped tlb. the area from h'fc00 0000 to h'ffff ffff is reserved for registers of the on-chip peripheral modules. for more information, see section 37, list of registers. (e) uxy area the uxy area is mapped to the on-chip memory of this lsi. this area is made usable in user mode when the dsp bit in the sr register is set to 1. in user mode, accessing this area when the dsp bit is 0 will result in an address error. this ar ea cannot be accessed via the cache and cannot be address-translated by the tlb. for more information on the uxy area, see section 6, x/y memory. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 172 of 1458 rej09b0033-0300 (2) physical address space this lsi supports a 29-bit physical address space. as shown in figu re 4.5, the physical address space is divided into eight areas. area 1 is mappe d to the on-chip module control register area and on-chip memory area. area 7 is reserved. for details on physical address space, refer to section 9, bus state controller (bsc). h'0400 0000 h'0800 0000 h'0c00 0000 h'1000 0000 h'1400 0000 h'1c00 0000 h'1fff ffff h'1800 0000 area 0 area 1 (on-chip registers and on-chip memories) area 2 area 3 area 4 area 5 area 6 area 7 (reserved) h'0000 0000 figure 4.5 physical address space (3) address transition when the mmu is enabled, the virtual address sp ace is divided into units called pages. physical addresses are translated in pa ge units. address translation tables in external memory hold information such as the physical address that corres ponds to the virtual address and memory protection codes. when an access to area p1 or p2 occurs, there is no tlb access and the physical address is defined uniquely by hardware. if it be longs to area p0, p3 or u0, the tlb is searched by virtual address and, if that virtual address is registered in the tlb, the access hits the tlb. the corresponding physical address and the page cont rol information are read from the tlb and the physical address is determined. if the virtual address is not registered in the tlb, a tlb miss exception occurs and processing will shift to the tlb miss handler. in the tlb miss handler, the tlb address translation table in external memory is searched and the correspon ding physical address and the page control section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 173 of 1458 rej09b0033-0300 information are registered in the tlb. after returning from the handler, the instruction that caused the tlb miss is re-executed. when the mmu is enabled, address transl ation information that results in a physical address space of h'2000 0000 to h'ffff ffff s hould not be registered in the tlb. when the mmu is disabled, masking the upper three bits of the virtual address to 0s creates the address in the corr esponding physical address space. since this lsi supports 29-bit address space as physical address space, the uppe r three bits of the virtual addr ess are ignored as shadow areas. for details, refer to section 9, bus state contro ller (bsc). for example, address h'0000 1000 in the p0 area, address h'8000 1000 in the p1 area, address h'a000 1 000 in the p2 area, and address h'c000 1000 in the p3 area are all mapped to the same physical memory. if these addresses are accessed while the cache is enabled, the upper three bits are always cleared to 0 to guarantee the continuity of addresses stored in the address array of the cache. (4) single virtual memory mode a nd multiple virtual memory mode there are two virtual memory modes: single virtual memory mode and multiple virtual memory mode. in single virtual memory mode, multiple processes run in parallel using the virtual address space exclusively and the physical address corresp onding to a given virtual address is specified uniquely. in multiple virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a given virtual address may be translated into different physical addresses depending on the process. by the value set to the mmu control register (mmucr), either single or multiple virtual mode is selected. in terms of operation, the only difference between single virtual memory mode and multiple virtual memory mode is in the tlb address comparison method (see section 4.3.3, tlb address comparison). (5) address space identifier (asid) in multiple virtual memory mode, the address space identifier (asid) is used to differentiate between processes running in para llel and sharing virtual address sp ace. the asid is eight bits in length and can be set by software setting of the asid of the currently running process in page table entry register high (pteh) within the mmu . when the process is switched using the asid, the tlb does not have to be purged. in single virtual memory mode, the asid is used to provide memory protection for processes running simultaneously and using the virtual addr ess space exclusively (see section 4.3.3, tlb address comparison). section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 174 of 1458 rej09b0033-0300 4.2 register descriptions there are four registers for mmu processing. these are all peri pheral module registers, so they are located in address space area p4 and can only be accessed from privileg ed mode by specifying the address. the mmu has the following registers. refer to section 37, list of registers, for more details on the addresses and access size of these registers. ? page table entry register high (pteh) ? page table entry register low (ptel) ? translation table ba se register (ttb) ? mmu control register (mmucr) 4.2.1 page table entry register high (pteh) the page table entry register high (pteh) register residing at address h'ffff fff0, which consists of a virtual page number (vpn) and asid. the vpn set is the vpn of the virtual address at which the exception is generated in case of an mmu exception or address error exception. when the page size is 4 kbytes, the vpn is the upper 20 bits of the virtual address, but in this case the upper 22 bits of the virtual address are set. the vpn can also be modifi ed by software. as the asid, software sets the number of the curre ntly executing process. the vpn and asid are recorded in the tlb by the ldtlb instruction. a program that modifies the asid in pteh s hould be allocated in the p1 or p2 areas. bit bit name initial value r/w description 31 to 10 vpn ? r/w the number of the logical page 9, 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 asid ? r/w address space identifier section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 175 of 1458 rej09b0033-0300 4.2.2 page table entry register low (ptel) the page table entry register low (ptel) register residing at address h'ffff fff4, and used to store the physical page number and page management information to be recorded in the tlb by the ldtlb instruction. the contents of this register are only modified in response to a software command. bit bit name initial value r/w description 31 to 29 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 28 to 10 ppn ? r/w the number of the physical page 9 ? 0 r 8 v ? r/w 7 ? 0 r 6, 5 pr ? r/w 4 sz ? r/w 3 c ? r/w 2 d ? r/w 1 sh ? r/w 0 ? 0 r page management information for more details, see section 4.3, tlb functions. 4.2.3 translation table base register (ttb) the translation table base regist er (ttb) residing at address h'ffff fff8, which points to the base address of the current page table. the hard ware does not set any value in ttb automatically. ttb is available to software for general purposes. the initial value is undefined. 4.2.4 mmu control register (mmucr) the mmu control register (mmucr) residing at address h'ffff ffe0. any program that modifies mmucr should reside in the p1 or p2 area. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 176 of 1458 rej09b0033-0300 bit bit name initial value r/w description 31 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 sv 0 r/w single virtual memory mode 0: multiple virtual memory mode 1: single virtual memory mode 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5, 4 rc all 0 r/w random counter a 2-bit random counter that is automatically updated by hardware according to the following rules in the event of an mmu exception. when a tlb miss exception occurs, all of tlb entry way corresponding to the virtual address at which the exception occurred are checked. if all ways are valid, 1 is added to rc; if there is one or more invalid way, they are set by priority from way 0, in the order way 0, way 1, way 2, way 3. in the event of an mmu exception other than a tlb miss exception, the way which caused the exception is set in rc. 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 tf 0 r/w tlb flush write 1 to flush the tlb (clear all valid bits of the tlb to 0). when they are read, 0 is always returned. 1 ix 0 r/w index mode 0: vpn bits 16 to 12 are used as the tlb index number. 1: the value obtained by ex-oring asid bits 4 to 0 in pteh and vpn bits 16 to 12 is used as the tlb index number. 0 at 0 r/w address translation enables/disables the mmu. 0: mmu disabled 1: mmu enabled section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 177 of 1458 rej09b0033-0300 4.3 tlb functions 4.3.1 configuration of the tlb the tlb caches address translation table informatio n located in the external memory. the address translation table stores the virtual page number and the corresponding physical number, the address space identif ier, and the control information for the page, which is the unit of address translation. figure 4.6 shows the overall tlb co nfiguration. the tlb is 4-way set associative with 128 entries. there are 32 entries for each way. figure 4.7 shows the configuration of virtual addresses and tlb entries. entry 1 address array data array entry 0 entry 1 entry 31 way 0 to 3 way 0 to 3 vpn(11 to 10) vpn(31 to 17) asid(7 to 0) v entry 0 entry 31 ppn(28 to 10) pr(1 to 0) sz c d sh figure 4.6 overall configuration of the tlb section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 178 of 1458 rej09b0033-0300 31 9 vpn virtual address (1-kbyte page) virtual address (4-kbyte page) tlb entry offset vpn vpn (31 to 17) vpn (11 to 10) asid v pr sz sh ppn c d offset 0 10 31 11 0 (15) (2) (2) (8) (1) (19) (1) (1) (1) (1) 12 [legend] vpn: virtual page number upper 19 bits of virtual address for a 1-kbyte page, or upper 20 bits of logical address for a 4-kbyte page. since vpn bits 16 to 12 are used as the index number, they are not stored in the tlb entry. attention must be paid to the synonym problem (see section 4.4.4, avoiding synonym problems). asid: address space identifier indicates the process that can access a virtual page. in single virtual memory mode and user mode, or in multiple virtual memory mode, if the sh bit is 0, the address is compared with the asid in pteh when address comparison is performed. sh: share status bit 0: page not shared between processes 1: page shared between processes sz: page-size bit 0: 1-kbyte page 1: 4-kbyte page v: valid bit indicates whether entry is valid. 0: invalid 1: valid cleared to 0 by a power-on reset. not affected by a manual reset. ppn: physical page number upper 22 bits of physical address. ppn bits 11 to10 are not used in case of a 4-kbyte page. pr: protection key field 2-bit field encoded to define the access rights to the page. 00: reading only is possible in privileged mode. 01: reading/writing is possible in privileged mode. 10: reading only is possible in privileged/user mode. 11: reading/writing is possible in privileged/user mode. c: cacheable bit indicates whether the page is cacheable. 0: non-cacheable 1: cacheable d: dirty bit indicates whether the page has been written to. 0: not written to 1: written to figure 4.7 virtual address and tlb structure section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 179 of 1458 rej09b0033-0300 4.3.2 tlb indexing the tlb uses a 4-way set associative scheme, so en tries must be selected by index. vpn bits 16 to 12 and asid bits 4 to 0 in pteh are used as the index number regardless of the page size. the index number can be generated in two different ways depending on the setting of the ix bit in mmucr. 1. when ix = 1, vpn bits 16 to 12 are ex-ored with asid bits 4 to 0 to generate a 5-bit index number 2. when ix = 0, vpn bits 16 to 12 alone are used as the index number the first method is used to prevent lowered tlb efficiency that results when multiple processes run simultaneously in the same virtual addre ss space (multiple virtual memory) and a specific entry is selected by indexing of each process. in single virt ual memory mode (mmucr.sv = 1), ix bit should be set to 0. figures 4.8 and 4.9 show the indexing schemes. 31 16 11 12 17 0 31 0 pteh register virtual address vpn 0 asid 7 10 index asid(4 to 0) exclusive-or way 0 to 3 vpn(31 to 17) vpn(11 to 10) asid(7 to 0) v 0 31 address array data array ppn(28 to 10) pr(1 to 0) sz c d sh figure 4.8 tlb indexing (ix = 1) section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 180 of 1458 rej09b0033-0300 31 16 11 12 17 0 virtual address index way 0 to 3 vpn(31 to 17) vpn(11 to 10) asid(7 to 0) v 0 31 address array data array ppn(28 to 10) pr(1 to 0) sz c d sh figure 4.9 tlb indexing (ix = 0) 4.3.3 tlb address comparison the results of address co mparison determine whether a specific virtual page number is registered in the tlb. the virtual page number of the vi rtual address that accesses external memory is compared to the virtual page number of the indexed tlb entry. the asid within the pteh is compared to the asid of the indexed tlb entry. all four ways are search ed simultaneously. if the compared values match, and the indexed tlb entry is valid (v bit = 1), the hit is registered. it is necessary to have software ensure that tlb hits do not occur simultaneously in more than one way, as hardware operation is not guaranteed if this occurs. an example of setting which causes tlb hits to occur simultaneously in more than one way is described below. it is necessary to ensure that this kind of setting is not made by software. 1. if there are two identical tlb entries with the same vpn and a setting is made such that a tlb hit is made only by a process with asid = h'ff when one is in the shared state (sh = 1) and the other in the non-shared state (sh = 0), then if the asid in pteh is set to h'ff, there is a possibility of simultaneous tlb hits in both these ways. 2. if several entries which have different asid with the same vpn are registered in single virtual memory mode, there is the possibility of simultaneous tlb hits in more than one way when accessing the corresponding page in privileged mode. several entr ies with the same vpn must not be registered in single virtual memory mode. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 181 of 1458 rej09b0033-0300 3. there is the possibility of simultaneous tlb hits in more than one way. these hits may occur depending on the contents of asid in pteh when a page to which sh is set 1 is registered in the tlb in index mode (mmucr.ix = 1). therefore a page to which sh is set 1 must not be registered in index mode. when memory is shared by several processings, different pages must be registered in each asid. the object compared varies depending on the page management information (sz, sh) in the tlb entry. it also varies depending on whether the system supports multiple virtual memory or single virtual memory. the page-size information determines whether vpn (11 to 10) is compared. vpn (11 to 10) is compared for 1-kbyte pages (sz = 0) but not for 4-kbyte pages (sz = 1). the sharing information (sh) de termines whether the pteh.asid and the asid in the tlb entry are compared. asids are comp ared when there is no sh aring between processes (sh = 0) but not when there is sharing (sh = 1). when single virtual memory is supported (mmucr.sv = 1) and privileged mode is engaged (sr.md = 1), all process resources can be accessed. this means that as ids are not compared when single virtual memory is supported and privileged mode is engaged. the objects of address comparison are shown in figure 4.10. sh = 1 or (sr.md = 1 and mmucr.sv = 1)? sz = 0? sz = 0? no no (4-kbyte) yes yes (1-kbyte) no (4-kbyte) yes (1-kbyte) bits compared: vpn 31 to 17 vpn 11 to 10 bits compared: vpn 31 to 17 bits compared: vpn 31 to 17 vpn 11 to 10 asid 7 to 0 bits compared: vpn 31 to 17 asid 7 to 0 figure 4.10 objects of address comparison section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 182 of 1458 rej09b0033-0300 4.3.4 page management information in addition to the sh and sz bits, the page management information of tlb entries also includes d, c, and pr bits. the d bit of a tlb entry indicates whether the page is dirty (i.e., has been written to). if the d bit is 0, an attempt to write to the page results in an initial page write exception. for physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. to record that there has been a write to a given page in the address translation table in memory, an initial page write exception is used. the c bit in the entry indicates whether the re ferenced page resides in a cacheable or non- cacheable area of memory. when th e control registers and on-chip memory in area 1 are mapped, set the c bit to 0. the pr field specifies the access rights for the pa ge in privileged and user modes and is used to protect memory . attempts at non-permitted acce sses result in tlb protection violation exceptions. access states designated by the d, c, and pr bits are shown in table 4.1. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 183 of 1458 rej09b0033-0300 table 4.1 access states designat ed by d, c, and pr bits privileged mode user mode reading writing reading writing d bit 0 permitted initial page write exception permitted initial page write exception 1 permitted permitted permitted permitted c bit 0 permitted (no caching) permitted (no caching) permitted (no caching) permitted (no caching) 1 permitted (with caching) permitted (with caching) permitted (with caching) permitted (with caching) pr bit 00 permitted tlb protection violation exception tlb protection violation exception tlb protection violation exception 01 permitted permitted tlb protection violation exception tlb protection violation exception 10 permitted tlb protection violation exception permitted tlb protection violation exception 11 permitted permitted permitted permitted 4.4 mmu functions 4.4.1 mmu hardware management there are two kinds of mmu hardware management as follows. 1. the mmu decodes the virtual address accessed by a process and perform s address translation by controlling the tlb in accordance with the mmucr settings. 2. in address translation, the mmu receives pa ge management informat ion from the tlb, and determines the mmu exception and whether the cache is to be accessed (using the c bit). for details of the determination method and the hardware processing, see section 4.5, mmu exceptions. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 184 of 1458 rej09b0033-0300 4.4.2 mmu software management there are three kinds of mmu software management, as follows. 1. mmu register setting mmucr setting, in particular, should be perfor med in areas p1 and p2 for which address translation is not performed. also, since sv and ix bit changes constitute address translation system changes, in this case, tlb flushing shou ld be performed by simultaneously writing 1 to the tf bit also. since mmu excep tions are not generated in the mmu disabled state with the at bit cleared to 0, use in the disabled state mu st be avoided with software that does not use the mmu. 2. tlb entry recording, deletion, and reading tlb entry recording can be done in two ways by using the ldtlb instruction, or by writing directly to the memory-mapped tlb. for tlb entry deletion and reading, the memory allocation tlb can be accessed. see section 4.4. 3, mmu instruction (ldtlb), for details of the ldtlb instruction, and section 4.6, memory-mapped tlb, for details of the memory- mapped tlb. 3. mmu exception processing when an mmu exception is generated, it is handled on the basis of information set from the hardware side. see section 4.5, mmu exceptions, for details. when single virtual memory mode is used, it is possible to create a state in which physical memory access is enabled in the privileged mode only by clearing the share stat us bit (sh) to 0 to specify recording of all tlb en tries. this strengthens inter- process memory protection, and enables special access levels to be cr eated in the privileged mode only. recording a 1- or 4- kbyte page tlb entry may result in a synonym problem. see section 4.4.4, avoiding synonym problems. 4.4.3 mmu instruction (ldtlb) the load tlb instruction (ldtlb) is used to record tlb entries. when the ix bit in mmucr is 0, the ldtlb instruction changes the tlb entry in the way specified by the rc bit in mmucr to the value specified by pteh and ptel, using vpn bits 16 to 12 speci fied in pteh as the index number. when the ix bit in mmucr is 1, the ex-or of vpn bits 16 to 12 specified in pteh and asid bits 4 to 0 in pteh are used as the index number. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 185 of 1458 rej09b0033-0300 figure 4.11 shows the case where the ix bit in mmucr is 0. when an mmu exception occurs, the virtual page number of the virtual address that caused the exception is set in pteh by hardware. the way is set in the rc bit in mmucr for each exception according to the rules (see section 4.2.4, mmu c ontrol register (mmucr)). consequently, if the ldtlb instruction is issued after setting only ptel in the mmu exception processing routine, tlb entry recording is possible. any tlb entry can be updated by software rewriting of pteh and the rc bits in mmucr. as the ldtlb instruction changes address translation information, there is a risk of destroying address translation information if this instruction is issued in the p0, u0, or p3 area. make sure, therefore, that this instruction is issued in the p1 or p2 area. also, an instru ction associated with an access to the p0, u0, or p3 area (such as the rte instruction) should be issued at least two instructions after the ldtlb instruction. vpn(31 to 17) vpn(11 to 10) asid(7 to 0) v vpn 0 asid vpn 0 sv 0 0 rc 0 tf ix at ppn 0 0v0prszcdsh 0 write ppn(28 to 10) pr(1 to 0) sz c d sh write data array address array way selection way 0 to 3 31 9 0 mmucr index 31 17 12 10 8 0 pteh register 31 29 28 10 0 ptel register 0 31 00 figure 4.11 operation of ldtlb instruction section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 186 of 1458 rej09b0033-0300 4.4.4 avoiding synonym problems when a 1- or 4-kbyte page is recorded in a tlb entry, a synonym problem may arise. if a number of virtual addresses are mapped onto a single physi cal address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity. the reason that this problem occurs is explained below with reference to figure 4.12. the relationship between bit n of the virtual address and cache size is shown in the following table. note that no synonym problems occur in 4-kbyte page when the cac he size is 16 kbytes. cache size bit n in virtual address 16 kbytes 11 32 kbytes 12 to achieve high-speed operation of this lsi?s cach e, an index number is created using virtual address bits 12 to 4. when a 1-kbyte page is used, virtual address bits 12 to 10 is subject to address translation and when a 4-kbyte page is used, a virtual address bit 12 is subject to address translation. therefore, th e physical address bits 12 to 10 may not be the same as the virtual address bits 12 to 10. for example, assume that, with 1-kbyte page tlb entries, tlb entries for which the following translation has been performed are recorded in two tlbs: virtual address 1 h'0000 0000 physical address h'0000 0c00 virtual address 2 h'000 00c00 physical address h'0000 0c00 virtual address 1 is recorded in cache entry h' 000, and virtual address 2 in cache entry h'0c0. since two virtual addresses are recorded in different cache entries despite the fact that the physical addresses are the same, memory inconsistency will o ccur as soon as a write is performed to either virtual address. consequently, the following restrictions apply to the recording of address translation information in tlb entries. 1. when address translation information whereby a number of 1-kbyte page tlb entries are translated into the same physical address is recorded in the tlb, en sure that the vpn bits 12 is the same. 2. when address translation information whereby a number of 4-kbyte page tlb entries are translated into the same physical address is recorded in the tlb, ensure that the vpn bit 12 is the same. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 187 of 1458 rej09b0033-0300 3. do not use the same physical addresses for ad dress translation information of different page sizes. the above restrictions apply only when performing accesses using the cache. note: when multiple items of address translation information use the same physical memory to provide for future superh risc engine family expansion, ensure that the vpn bits 20 to 10 are the same. when using a 4-kbyte page virtual address 31 vpn 0 12 13 11 10 offset physical address 28 ppn 0 offset virtual address 12 to 4 physical address 28 to 10 cache when using a 1-kbyte page virtual address 31 vpn 0 10 11 12 13 offset physical address 28 ppn 0 10 11 12 13 offset virtual address 12 to 4 physical address 28 to 10 cache 12 13 11 10 figure 4.12 synonym problem (32-kbyte cache) section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 188 of 1458 rej09b0033-0300 4.5 mmu exceptions when the address translation unit of the mmu is enabled, occurrence of the mmu exception is checked following the cpu address error check. there are four mmu exceptions: tlb miss, tlb invalid, tlb protection violation, and initial page write, and these mmu exceptions are checked in this order. 4.5.1 tlb miss exception a tlb miss results when the virtual address and th e address array of the selected tlb entry are compared and no match is found. tlb miss exception processing includes both hardware and software operations. ? hardware operations in a tlb miss, this hardware executes a se t of prescribed oper ations, as follows: a. the vpn field of the virtual address causing the exception is written to the pteh register. b. the virtual address causing the exce ption is written to the tea register. c. either exception code h'040 fo r a load access, or h'060 for a store access, is written to the expevt register. d. the pc value indicating the address of the instruction in which the exception occurred is written to the save program counter (spc). if the exception occurred in a delay slot, the pc value indicating the address of the related dela yed branch instruction is written to the spc. e the contents of the status register (sr) at the time of the exception are written to the save status register (ssr). f. the mode (md) bit in sr is set to 1 to place the privileged mode. g. the block (bl) bit in sr is set to 1 to mask any further exception requests. h. the register bank (rb) bit in sr is set to 1. i. the rc field in the mmu control register ( mmucr) is incremented by 1 when all entries indexed are valid. when some entries indexed are invalid, the smallest way number of them is set in rc. the setting priority is way0, way1, way2, and way3. j. execution branches to the address obtained by adding the value of the vbr contents and h'0000 0400 to invoke the user-written tlb miss exception handler. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 189 of 1458 rej09b0033-0300 ? software (tlb miss handler) operations the software searches the page ta bles in external memory and al locates the required page table entry. upon retrieving the required page tabl e entry, software must execute the following operations: a. write the value of the physical page number (ppn) field and the protection key (pr), page size (sz), cacheable (c), dirty (d), share status (sh), and valid (v) bits of the page table entry recorded in the address translation ta ble in the external memory into the ptel register. b. if using software for way sel ection for entry replacement, write the desired value to the rc field in mmucr. c. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. d. issue the return from exception handler (rte) instruction to terminate the handler routine and return to the instruction stream. issue the rte instruction after issuing two instructions from the ldtlb instruction. 4.5.2 tlb protection violation exception a tlb protection violation exception results when the virtual address and the address array of the selected tlb entry are compared an d a valid entry is found to matc h, but the type of access is not permitted by the access rights specified in the pr field. tlb protect ion violation exception processing includes both hardware and software operations. ? hardware operations in a tlb protection violation exception, this hardware executes a set of prescribed operations, as follows: a. the vpn field of the virtual address causing the exception is written to the pteh register. b. the virtual address causing the exce ption is written to the tea register. c. either exception code h'0a0 fo r a load access, or h'0c0 for a store access, is written to the expevt register. d. the pc value indicating the address of the instruction in which the exception occurred is written into spc (if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written into spc). e. the contents of sr at the time of the exception ar e written to ssr. f. the md bit in sr is set to 1 to place the privileged mode. g. the bl bit in sr is set to 1 to mask any further exception requests. h. the rb bit in sr is set to 1. i. the way that generated the exception is set in the rc field in mmucr. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 190 of 1458 rej09b0033-0300 j. execution branches to the address obtained by adding the value of the vbr contents and h'0000 0100 to invoke the tlb protection violation exception handler. ? software (tlb protection viol ation handler) operations software resolves the tlb protection violatio n and issues the rte (r eturn from exception handler) instruction to terminate the handler and return to the instruction stream. issue the rte instruction after issuing two instructions from the ldtlb instruction. 4.5.3 tlb invalid exception a tlb invalid exception results when the virtual address is compared to a selected tlb entry address array and a match is found but the entry is not valid (the v bit is 0). tlb invalid exception processing includes both hardware and software operations. ? hardware operations in a tlb invalid exception, this hardware execute s a set of prescribed op erations, as follows: a. the vpn field of the virtual address causing the exception is written to the pteh register. b. the virtual address causing the exce ption is written to the tea register. c. either exception code h'040 fo r a load access, or h'060 for a store access, is written to the expevt register. d. the pc value indicating the address of the instruction in which the exception occurred is written to the spc. if the exception occurred in a delay slot, the pc value indicating the address of the delayed branch inst ruction is written to the spc. e. the contents of sr at the time of the exception are written into ssr. f. the mode (md) bit in sr is set to 1 to place the privileged mode. g. the block (bl) bit in sr is set to 1 to mask any further exception requests. h. the rb bit in sr is set to 1. i. the way number causing the exception is written to rc in mmucr. j. execution branches to the address obtained by adding the value of the vbr contents and h'0000 0100, and the tlb protection violation exception handler starts. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 191 of 1458 rej09b0033-0300 ? software (tlb invalid exception handler) operations the software searches the page tables in external memory and assigns the required page table entry. upon retrieving the required page table entry, software must execute the following operations: a. write the values of the physical page number (ppn) field and the values of the protection key (pr), page size (sz), cacheable (c), dirty (d), share status (sh), and valid (v) bits of the page table entry recorded in the external memory to the ptel register. b. if using software for way sel ection for entry replacement, write the desired value to the rc field in mmucr. c. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. d. issue the rte instruction to terminate the ha ndler and return to the instruction stream. the rte instruction should be issued after two instructions form the ldtlb instruction. 4.5.4 initial page write exception an initial page write exception results in a wr ite access when the virtual address and the address array of the selected tlb entry are compared an d a valid entry with the appropriate access rights is found to match, but the d (dirty) bit of the entry is 0 (the page has not been written to). initial page write exception processing includes both hardware and software operations. ? hardware operations in an initial page write exception, this hardwa re executes a set of prescribed operations, as follows: a. the vpn field of the virtual address causing the exception is written to the pteh register. b. the virtual address causing the exce ption is written to the tea register. c. exception code h'080 is written to the expevt register. d. the pc value indicating the address of the instruction in which the exception occurred is written to the spc. if the exception occurred in a delay slot, the pc value indicating the address of the related delayed branch instruction is written to the spc. e. the contents of sr at the time of the exception ar e written to ssr. f. the md bit in sr is set to 1 to place the privileged mode. g. the bl bit in sr is set to 1 to mask any further exception requests. h. the rb bit in sr is set to 1. i. the way that caused the exception is set in the rc field in mmucr. j. execution branches to the address obtained by adding the value of the vbr contents and h'0000 0100 to invoke the user-written initial page write exception handler. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 192 of 1458 rej09b0033-0300 ? software (initial page write handler) operations the software must execute the following operations: a. retrieve the required page table entry from external memory. b. set the d bit of the page table entry in the external memory to 1. c. write the value of the ppn field and the pr, sz, c, d, sh, and v bits of the page table entry in the external memory to the ptel register. d. if using software for way sel ection for entry replacement, write the desired value to the rc field in mmucr. e. issue the ldtlb instruction to load the contents of pteh and ptel into the tlb. f. issue the rte instruction to terminate the ha ndler and return to the instruction stream. the rte instruction must be issued after two ldtlb instructions. 4.5.5 mmu exception in repeat loop if a cpu address error or mmu exception occurs in a specific instruction in the repeat loop, the spc may indicate an illegal address or the repeat loop cannot be reexecuted correctly even if the spc is correct. accordingly, if a cpu addres s error or mmu exception occurs in a specific instruction in the repeat loop, this lsi generate s a specific exception code to set the expevt to h 070 for a tlb miss exception, tlb invalid exceptio n, initial page write exception, and cpu address error and to h'0d0 for a tlb protection violation exception. in addition, a vector offset for tlb miss exception is h'100. for details, refer to section 7.4.3, exception in repeat control period. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 193 of 1458 rej09b0033-0300 start sh = 0 and (mmucr.sv = 0 or sr.md = 0)? vpns and asids match? v = 1? user or privileged? d = 1? c = 1? memory access cache access initial page write exception tlb protection violation exception pr? tlb protection violation exception r/w? r/w? r/w? r/w? pr? tlb invalid exception tlb miss exception cpu address error vpns match? no no no no (non-cacheable) yes (cacheable) yes yes yes yes yes no address error? yes no no user mode privileged mode 01/11 00/10 00/01 10 11 wwww r rr r figure 4.13 mmu exception generation flowchart section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 194 of 1458 rej09b0033-0300 4.6 memory-mapped tlb in order for tlb operations to be managed by software, tlb contents can be read or written to in the privileged mode using the mov instruction. the tlb is assigned to the p4 area in the virtual address space. the tlb address ar ray (vpn, v bit, and asid) is assigned to h'f200 0000 to h'f2ff ffff, and the data array (ppn, pr, sz, c, d, and sh bits) to h'f300 0000 to h'f3ff ffff. the v bit in the address array can also be accessed from the data array. only longword access is possible for both the addr ess array and the data array. however, the instruction data cannot be fetched from both arrays. 4.6.1 address array the address array is assigned to h'f200 0000 to h'f2ff ffff. to access an address array, the 32- bit address field (for read/write operations) and 32-bit data field (for write operations) must be specified. the address field specifi es information for se lecting the entry to be accessed; the data field specifies the vpn, v bit and asid to be written to the address array (figure 4.14 (1)). in the address field, specify th e entry address for selecting th e entry (bits 16 to 12), w for selecting the way (bits 9 to 8) and h f2 to indicate address array access (bits 31 to 24). the ix bit in mmucr indicates whether an ex-or is taken of the entry address and asid. the following two operations can be used on the address array: 1. address array read vpn, v, and asid are read from the tlb entr y corresponding to the entry address and way set in the address field. 2. tlb address array write the data specified in the data field are written to the tlb entry corresponding to the entry address and way set in the address field. 4.6.2 data array the data array is assigned to h'f300 0000 to h'f3ff ffff. to access a data array, the 32-bit address field (for read/write op erations), and 32-bit data field (for write operations) must be specified. the address section speci fies information for selecting th e entry to be accessed; the data section specifies the longword data to be written to the data array (figure 4.14 (2)). in the address section, specify the entry address for selecting the entry (bits 16 to 12), w for selecting the way (bits 9 to 8), and h'f3 to indicat e data array access (bits 31 to 24). the ix bit in mmucr indicates whether an ex-or is taken of the entry address and asid. section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 195 of 1458 rej09b0033-0300 both reading and writing use the longword of the data array specified by the entry address and way number. the access size of the da ta array is fixed at longword. 1 1 1 1 0 0 1 0 9 vpn: virtual page number v: valid bit w: way (00: way 0, 01: way 1, 10: way 2, 11: way 3) asid: address space identifier * : don?t care bit address field data field address field data field address field data field 31 24 23 17 16 12 1110 9 8 7 0 31 17 16 12 1110 9 8 7 0 31 24 23 17 16 12 11 11 10 9 8 7 0 31 17 16 12 10 9 8 7 0 31 24 23 29 28 17 16 12 1110 9 8 7 0 1 2 31 10 8 7 0 6 654321 0 0 0 vpn 1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 1 (1) tlb address array access read access write access (2) tlb data array access read/write access 6 * . . . . . . . . . . . . * vpn w 0 ** * . . . . . . . . . * vpn 0 . . . . . . . 0 vpn 0 v asid * . . . . . . . . . . . . * vpn * . . . . . . . * w0 * . . . . . . . . . * * * vpn v * asid * . . . . . . . . . . . . * vpn w * . . . . . . . . . . . * * * ppn xvx pr sz cd sh x ppn: physical page number pr: protection key field c: cacheable bit sh: share status bit vpn: virtual page number x: 0 for read, don?t care bit for write w: way (00: way 0, 01: way 1, 10: way 2, 11: way 3) v: valid bit sz: page-size bit d: dirty bit * : don?t care bit 00 1 2 00 1 2 00 figure 4.14 specifying address a nd data for memory-mapped tlb access section 4 memory management unit (mmu) rev. 3.00 jan. 18, 2008 page 196 of 1458 rej09b0033-0300 4.6.3 usage examples (1) invalidating specific entries specific tlb entries can be invalidated by writing 0 to the entry?s v bit. r0 specifies the write data and r1 specifies the address. ; r0=h'1547 381c r1=h'f201 3000 ; mmucr.ix=0 ; the v bit of way 0 of the entry selected by the vpn(16?12)=b'1 0011 ; index is cleared to 0,achieving invalidation. mov.l r0,@r1 (2) reading the data of a specific entry this example reads the data secti on of a specific tlb entry. the bit order indicated in the data field in figure 4.17 (2) is read. r0 specifies the address and the data section of a selected entry is read to r1. ; r0 = h'f300 4300 vpn(16-12)=b'00100 way 3 ; mov.l @r0,r1 4.7 usage note the following operations should be performed in the p1 or p2 area. in addition, when the p0, p3, or u0 area is accessed consecutively (this access includes instruction fetching), the instruction code should be placed at least two instructions after the instruction that executes the following operations. 1. modification of sr.md or sr.bl 2. execution of the ldtlb instruction 3. write to the memory-mapped tlb 4. modification of mmucr 5. modification of pteh.asid section 5 cache cach001a_000020020800 rev. 3.00 jan. 18, 2008 page 197 of 1458 rej09b0033-0300 section 5 cache 5.1 features ? capacity: 16 or 32 kbytes ? structure: instructions/data mixed, 4-way set associative ? locking: way 2 and way 3 are lockable ? line size: 16 bytes ? number of entries: 256 entries/way in 16-kbyte mode to 512 entries/way in 32-kbyte mode ? write system: write-back/write -through is selectable fo r spaces p0, p1, p3, and u0 group 1 (p0, p3, and u0 areas) group 2 (p1 area) ? replacement method: least-recen tly used (lru) algorithm note: after power-on reset or manual reset, initialized as 16-kbyte mode (256 entries/way). 5.1.1 cache structure the cache mixes instructions and data and uses a 4-way set associative syst em. it is composed of four ways (banks), and each of which is divided in to an address section and a data section. note that the following sections will be described for the 16-kbyte mode as an example. for other cache size modes, change the number of entries and size/ way according to table 5.1. each of the address and data sections is divided into 256 entries. the entry data is called a line. each line consists of 16 bytes (4 bytes 4). the data capacity per way is 4 kbytes (16 bytes 256 entries) in the cache as a whole (4 ways). the cache capacity is 16 kbytes as a whole. table 5.1 number of entries a nd size/way in each cache size cache size number of entries size/way 16 kbytes 256 4 kbytes 32 kbytes 512 8 kbytes section 5 cache rev. 3.00 jan. 18, 2008 page 198 of 1458 rej09b0033-0300 figure 5.1 shows the cache structure. 24 (1 + 1 + 22) bits 128 (32 4) bits 6 bits lw0 to lw3: longword data 0 to 3 entry 0 entry 1 entry 255 0 1 255 0 1 255 v u tag address lw0 lw1 lw2 lw3 address array (ways 0 to 3) data array (ways 0 to 3) lru . . . . . . . . . . . . . . . . . . figure 5.1 cache structure (1) address array the v bit indicates whether the entry data is valid. when the v bit is 1, data is valid; when 0, data is not valid. the u bit indicates whether the entry has been written to in write-back mode. when the u bit is 1, the entry has been written to; when 0, it has not. the tag address holds the physical address used in the external memory access. it is co mposed of 22 bits (address bits 31 to 10) used for comparison duri ng cache searches. in this lsi, the top three of 32 physical address bits are used as shadow bits (see section 9, bus state controller (bsc)), and theref ore the top three bits of the tag address are cleared to 0. the v and u bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. the tag address is not initialized by either a power-on or manual reset. (2) data array holds a 16-byte instruction or data. entries are regi stered in the cache in line units (16 bytes). the data array is not initialized by a power-on or manual reset. section 5 cache rev. 3.00 jan. 18, 2008 page 199 of 1458 rej09b0033-0300 (3) lru with the 4-way set associative syst em, up to four instructions or data with the same entry address can be registered in the cache. when an entry is registered, lru shows which of the four ways it is recorded in. there are six lru bits, controlled by hardware. a least-recently-used (lru) algorithm is used to select the way. six lru bits indicate the way to be replaced, when a cache miss occurs. table 5.2 shows the relationship between the lru bits and the way to be replaced when the cache locking mechanism is disabled. (for the relationship when the cach e locking mechanism is enabled, refer to section 5.2.2, cache control register 2 (ccr2).) if a bit pa ttern other than those listed in table 5.2 is set in the lru bits by software, the cache will not function correctly. when modifying the lru bits by software, set one of the patterns listed in table 5.2. the lru bits are initialized to h'000000 by a power-on reset, but are not initialized by a manual reset. table 5.2 lru and way replacement (when cache locking mechanism is disabled) lru (bits 5 to 0) way to be replaced 000000, 000100, 010100, 100000, 110000, 110100 3 000001, 000011, 001011, 100001, 101001, 101011 2 000110, 000111, 001111, 010110, 011110, 011111 1 111000, 111001, 111011, 111100, 111110, 111111 0 5.2 register descriptions the cache has the following registers. refer to section 37, list of registers, for more details on the addresses and access size of these registers. ? cache control register 1 (ccr1) ? cache control register 2 (ccr2) ? cache control register 3 (ccr3) section 5 cache rev. 3.00 jan. 18, 2008 page 200 of 1458 rej09b0033-0300 5.2.1 cache control register 1 (ccr1) the cache is enabled or disabled using the ce bit in ccr1. ccr1 also has a cf bit (which invalidates all cache entries), and wt and cb bits (which select either write-through mode or write-back mode). programs that change the cont ents of the ccr1 register should be placed in address space that is not cached. bit bit name initial value r/w description 31 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 cf 0 r/w cache flush writing 1 flushes all cache entries (clears the v, u, and lru bits of all cache entrie s to 0). this bit is always read as 0. write-back to external memory is not performed when the cache is flushed. 2 cb 0 r/w write-back indicates the cache?s operating mode for space p1. 0: write-through mode 1: write-back mode 1 wt 0 r/w write-through indicates the cache?s operating mode for spaces p0, u0, and p3. 0: write-back mode 1: write-through mode 0 ce 0 r/w cache enable indicates whether the cache function is used. 0: the cache function is not used. 1: the cache function is used. section 5 cache rev. 3.00 jan. 18, 2008 page 201 of 1458 rej09b0033-0300 5.2.2 cache control register 2 (ccr2) the ccr2 register controls the cache locking me chanism in cache lock mode only. the cpu enters the cache lock mode when the dsp bit (bit 12) in the status register (sr) is set to 1 or the lock enable bit (bit 16) in the cache control register 2 (ccr2) is set to 1. the cache locking mechanism is disabled in non- cache lock mode (dsp bit = 0). when a prefetch instruction (pref@rn) is issu ed in cache lock mode and a cache miss occurs, the line of data pointed to by rn will be loaded into the cache, according to the setting of bits 9 and 8 (w3load, w3lock) and bits 1 and 0 (w2load, w2lock in ccr2). table 5.3 shows the relationship between the settings of bits and the way that is to be replaced when the cache is missed by a prefetch instruction. on the other hand, when the cache is hit by a prefetch in struction, new data is not loaded into the cache and the valid entry is held. for example, a prefetch instruction is issued while bits w3load and w3lock are set to 1 and the line of data to which rn points is already in way 0, the cache is hit and new data is not loaded into way 3. in cache lock mode, bits w3lock and w2lock restrict the way that is to be replaced, when instructions other than the prefetch instruction are issued. table 5.4 shows the relationship between the settings of bits in ccr2 and the way that is to be replaced when the cache is missed by instructions other than the prefetch instruction. programs that change the contents of the ccr2 register should be placed in address space that is not cached. section 5 cache rev. 3.00 jan. 18, 2008 page 202 of 1458 rej09b0033-0300 bit bit name initial value r/w description 31 to 17 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 16 le 0 r/w lock enable (le) controls cache lock mode. 0: enters cache lock mode when the dsp bit in the sr register is set to 1. 1: enters cache lock mode regardless of the dsp bit value. 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 w3load w3lock 0 0 r/w r/w way 3 load (w3load) way 3 lock (w3lock) when the cache is missed by a prefetch instruction while in cache lock mode and when bits w3load and w3lock in ccr2 are set to 1, the data is always loaded into way 3. under any other condition, the prefetched data is loaded into the way to which lru points. 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 w2load w2lock 0 0 r/w r/w way 2 load (w2load) way 2 lock (w2lock) when the cache is missed by a prefetch instruction while in cache lock mode and when bits w2load and w2lock in ccr2 are set to 1, the data is always loaded into way 2. under any other condition, the prefetched data is loaded into the way to which lru points. note: w2load and w3load should not be set to 1 at the same time. section 5 cache rev. 3.00 jan. 18, 2008 page 203 of 1458 rej09b0033-0300 table 5.3 way replacement when a pref instruction misses the cache dsp bit w3load w3lock w2load w2lock way to be replaced 0 * * * * determined by lru (table 5.2) 1 * 0 * 0 determined by lru (table 5.2) 1 * 0 0 1 determined by lru (table 5.5) 1 0 1 * 0 determined by lru (table 5.6) 1 0 1 0 1 determined by lru (table 5.7) 1 0 * 1 1 way 2 1 1 1 0 * way 3 note: * don?t care w3load and w2load should not be set to 1 at the same time. table 5.4 way replacement when instructions other than the pref instruction miss the cache dsp bit w3load w3lock w2load w2lock way to be replaced 0 * * * * determined by lru (table 5.2) 1 * 0 * 0 determined by lru (table 5.2) 1 * 0 * 1 determined by lru (table 5.5) 1 * 1 * 0 determined by lru (table 5.6) 1 * 1 * 1 determined by lru (table 5.7) note: * don?t care w3load and w2load should not be set to 1 at the same time. table 5.5 lru and way replacement (when w2lock = 1 and w3lock =0) lru (bits 5 to 0) way to be replaced 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 3 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 1 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 0 section 5 cache rev. 3.00 jan. 18, 2008 page 204 of 1458 rej09b0033-0300 table 5.6 lru and way replacement (when w2lock = 0 and w3lock =1) lru (bits 5 to 0) way to be replaced 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 2 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 1 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 table 5.7 lru and way replacement (when w2lock = 1 and w3lock =1) lru (bits 5 to 0) way to be replaced 000000, 000001, 000011, 000100, 00 0110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 1 100000, 100001, 101001, 101011, 11 0000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 0 5.2.3 cache control register 3 (ccr3) the ccr3 register controls the cache size to be us ed. the cache size must be specified according to the lsi to be selected. if the specified cache size exceeds the size of ca che incorporated in the lsi, correct operation cannot be guaranteed. note th at programs that change the contents of the ccr3 register should be placed in un-cached address space. in addition, note that all cache entries must be invalidated by setting the cf bit in the ccr1 to 1 before acce ssing the cache after the ccr3 is modified. bit bit name initial value r/w description 31 to 24 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 23 to 16 csize7 to csize0 h'01 r/w cache size specify the cache size as shown below. 0000 0001: 16-kbyte cache 0000 0010: 32-kbyte cache settings other than above are prohibited. 15 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 5 cache rev. 3.00 jan. 18, 2008 page 205 of 1458 rej09b0033-0300 5.3 operation 5.3.1 searching the cache if the cache is enabled (the ce bit in ccr1 = 1), whenever instructions or data in spaces p0, p1, p3, and u0 are accessed the cache will be searched to see if the desired instruction or data is in the cache. figure 5.2 illustrates the method by which the cache is s earched. the cache is a physical cache and holds physical addresses in its address section. the example of operation in 16-kbyte mode is described below: entries are selected using bits 11 to 4 of the ad dress (virtual) of the access to memory and the tag address of that entry is read. in parallel with reading the tag address, the virtual address is converted into the physical addres s. the virtual address of the access to memory and the physical address (tag address) read from the address array are compared. the address comparison uses all four ways. when the comp arison shows a match and the selected entry is valid (v = 1), a cache hit occurs. when the comparison does not show a match or the selected entry is not valid (v = 0), a cache miss occurs. figure 5. 2 shows a hit on way 1. section 5 cache rev. 3.00 jan. 18, 2008 page 206 of 1458 rej09b0033-0300 0 1 255 v u tag address lw0 lw1 lw2 lw3 ways 0 to 3 ways 0 to 3 31 12 11 4 3 2 1 0 virtual address cmp0 cmp1 cmp2 cmp3 physical address cmp0: comparison circuit 0 cmp1: comparison circuit 1 cmp2: comparison circuit 2 cmp3: comparison circuit 3 hit signal 1 entry selection longword (lw) selection mmu figure 5.2 cache search scheme section 5 cache rev. 3.00 jan. 18, 2008 page 207 of 1458 rej09b0033-0300 5.3.2 read access (1) read hit in a read access, instructions and data are tran sferred from the cache to the cpu. the lru i s updated to indicate that the hit wa y is the most recently hit way. (2) read miss an external bus cycle starts and the entry is update d. the way to be replaced is shown in table 5.4. entries are updated in 16-byte units. when the desired instruction or data that caused the miss is loaded from external memory to the cache, the in struction or data is transferred to the cpu in parallel with being loaded to the cache. when it is loaded to the cache, the u bit is cleared to 0 and the v bit is set to 1 to indicate that the hit way is the most recently hit way. when the u bit for the entry which is to be replaced by entry updating in write-back mode is 1, the cache-update cycle starts after the entry is transferred to the write -back buffer. after the cac he completes its update cycle, the write-back buff er writes the entry back to the memory. transfer is in 16-byte units. 5.3.3 prefetch operation (1) prefetch hit the lru is updated to indicate that the hit way is the most recently hit way. the other contents of the cache are not changed. instructions and data are not tran sferred from the cache to the cpu. (2) prefetch miss instructions and data are not transferred from the cac he to the cpu. the way that is to be replaced is shown in table 5.3. the other operations are the same as those for a read miss. 5.3.4 write access (1) write hit in a write access in write-back mode, the data is written to the cache and no external memory write cycle is issued. the u bit of the entry that has been written to is set to 1, and the lru is updated to indicate that the hit way is the most r ecently hit way. in write-through mode, the data is written to the cache and an external memory write cycle is issued. the u bit of the entry that has been written to is not updated, and the lru is updated to indicate that the hit way is the most recently hit way. section 5 cache rev. 3.00 jan. 18, 2008 page 208 of 1458 rej09b0033-0300 (2) write miss in write-back mode, an external write cycle star ts when a write miss occurs, and the entry is updated. the way to be replaced is shown in table 5.4. when the u bit of th e entry which is to be replaced by entry updating is 1, th e cache-update cycle starts after th e entry has been transferred to the write-back buffer. data is written to the cache and the u bit and the v bit are set to 1. the lru is updated to indicate that the replaced way is the most recen tly updated way. after the cache has completed its update cycle, the write-back buffer writes the entry back to the memory. transfer is in 16-byte units. in write-through mo de, no write to cache occu rs in a write miss; the write is only to the external memory. 5.3.5 write-back buffer when the u bit of the entry to be replaced in write-back mode is 1, the entry must be written back to the external memory. to increas e performance, the entry to be re placed is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. after the fetching of new entrie s to the cache completes, the write-back buffer writes the entry back to the external memory. du ring the write-back cycles, the cache can be accessed. the write-back buffer can hold one line of cache data (16 bytes) and its physical address. figure 5.3 shows the configuration of the write-back buffer. longword 0 longword 1 longword 2 longword 3 pa (31 to 4) pa (31 to 4): longword 0 to 3: physical address written to external memory one line of cache data to be written to external memory figure 5.3 write-back buffer configuration 5.3.6 coherency of cach e and external memory use software to ensure coherency between the cache and the external memory. when memory shared by this lsi and another device is placed in an address space to which caching applies, use the memory-mapped cache to make the data invalid and written back, as required. memory that is shared by this lsi?s cpu and dmac should also be handled in this way. section 5 cache rev. 3.00 jan. 18, 2008 page 209 of 1458 rej09b0033-0300 5.4 memory-mapped cache to allow software management of the cache, cache contents can be read and written by means of mov instructions in pr ivileged mode. the cache is mapped ont o the p4 area in virtual address space. the address array is mapped onto addre sses h'f0000000 to h'f0ffffff, and the data array onto addresses h'f1000000 to h'f1ffffff. on ly longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 5.4.1 address array the address array is mapped onto h'f0000000 to h'f0ffffff. to access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. the address field specifi es information for se lecting the entry to be accessed; the data field specifies the tag address, v bit, u bit, an d lru bits to be written to the address array. in the address field, specify the entry address for selecting the en try, w for selecting the way, a for enabling or disabling the associative operati on, and h'f0 for indicating address array access. as for w, b'00 indicates way 0, b'01 indicates way 1, b'10 indicates way 2, and b'11 indicates way 3. in the data field, specify the tag address, lru bits, u bit, and v bit. figure 5.4 shows the address and data formats in 16-byte mode. for other cach e size modes, change the entry address and was shown in table 5.8. the following three oper ations are available in the address array. (1) address-array read read the tag address, lru bits, u bit, and v bit fo r the entry that corresponds to the entry address and way specified by the address fi eld of the read instru ction. in reading, th e associative operation is not performed, regardless of whether the associative bit (a bit) specified in the address is 1 or 0. (2) address-array write (non-associative operation) write the tag address, lru bits, u bit, and v bit, specified by the data field of the write instruction, to the entry that corresponds to the entry address and way as specified by the address field of the write instruction. ensure that the associative bit (a bit) in the address field is set to 0. when writing to a cache line for which the u bit = 1 and the v bit =1, write the contents of the cache line back to memory, then write the tag addr ess, lru bits, u bit, and v bit specified by the data field of the write instruction. always clear the uppermost 3 bits (bits 31 to 29) of the tag address to 0. when 0 is written to the v bit, 0 mu st also be written to the u bit for that entry. section 5 cache rev. 3.00 jan. 18, 2008 page 210 of 1458 rej09b0033-0300 (3) address-array write (associative operation) when writing with the associative bit (a bit) of th e address = 1, the addresses in the four ways for the entry specified by th e address field of the write instructi on are compared with the tag address that is specified by the data field of the write instruction. if the mmu is enabled in this case, a virtual address specified by data is translated into a physical addr ess via the tlb before comparison. write the u bit and the v bit specified by the data field of the write instruction to the entry of the way that has a hit. however, the tag address and lru bits remain unchanged. when there is no way that receives a h it, nothing is written and there is no operation. this function is used to invalidate a specific entry in the cache. wh en the u bit of the entry that has received a hit is 1 at this point, writing back should be perform ed. however, when 0 is written to the v bit, 0 must also be written to the u bit of that entry. 5.4.2 data array the data array is mapped onto h'f1000000 to h'f1ffffff. to access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write acce sses) must be specified. the address field specifies info rmation for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. in the address field, specify the entry address for selecting the entry, l for indicating the longword position within the (16-byte) line, w for selecti ng the way, and h'f1 for indicating data array access. as for l, b'00 indicates longword 0, b'01 indicates longword 1, b' 10 indicates longword 2, and b'11 indicates longword 3. as for w, b'00 indicates way 0, b 01 indicates way 1, b'10 indicates way 2, and b 11 indicates way 3. since access size of the data array is fixed at longwo rd, bits 1 and 0 of the address field should be set to b'00. figure 5.4 shows the address and data formats in 16-kbyte mode. for other cache size modes, change the entry address and w as shown in table 5.8. the following two operations on the data array ar e available. the information in the address array is not affected by these operations. (1) data-array read read the data specified by l of the address filed, from the entry that corresponds to the entry address and the way that is sp ecified by the address filed. section 5 cache rev. 3.00 jan. 18, 2008 page 211 of 1458 rej09b0033-0300 (2) data-array write write the longword data specified by the data file d, to the position specifi ed by l of the address field, in the entry that correspo nds to the entry address and the wa y specified by the address field. (1) address array access (a) address specification read access write access (b) data specification (both read and write accesses) (2) data array access (both read and write accesses) (a) address specification 31 24 23 14 13 12 11 4 3 0 1111 0000 * -------- * w entry address 31 24 23 14 13 12 11 4 3 0 1111 0000 * -------- * w entry address 2 a 31 10 4 3 0 lru 2 xx 9 tag address (31 to 10) u v 1 31 24 23 14 13 12 11 4 3 0 1111 0001 * -------- * w entry address 1 2 l (b) data specification 31 0 longword * : don?t care bit x: 0 for read, don?t care for write 0 * 0 0 * 0 0 2 00 figure 5.4 specifying address and data for memory-m apped cache access (16-kbyte mode) table 5.8 address format based on the si ze of cache to be assigned to memory cache size entry address bits w bit 16 kbytes 11 to 4 13 and 12 32 kbytes 12 to 4 14 to 13 section 5 cache rev. 3.00 jan. 18, 2008 page 212 of 1458 rej09b0033-0300 5.4.3 usage examples (1) invalidating specific entries specific cache entries can be invalidated by writin g 0 to the entry?s v bit in the memory-mapped cache access. when the a bit is 1, the tag address specified by the write data is compared to the tag address within the cache sel ected by the entry address, and a match is found, the entry is written back if the entry?s u bit is 1 and the v bit and u bit specified by the write data are written. if no match is found, there is no operation. in the example shown below, r0 specifies the write data and r1 specifies the address. ; r0 = h'01100010; vpn = b'0000 0001 0001 0000 0000 00, u = 0, v = 0 ; r1 = h'f0000088; address array access, entry = b'00001000, a = 1 ; mov.l r0,@r1 (2) reading the data of a specific entry to read the data field of a specific entry is enabled by the memory-mapped cache access. the longword indicated in the data field of the data array in figure 5.4 is read into the register. in the example shown below, r0 specifies the address and r1 shows what is read. ; r0 = h'f100 004c; data array access, entry = b'00000100 ; way = 0, longword address = 3 ; mov.l @r0,r1 ; longword 3 is read. section 6 x/y memory xym0000s_000020020300 rev. 3.00 jan. 18, 2008 page 213 of 1458 rej09b0033-0300 section 6 x/y memory this lsi has on-chip x-memory and y-memory which can be used to store instructions or data. 6.1 features ? page there are four pages. the x memory is divided into two pages (pages 0 and 1) and the y memory is divided into two pages (pages 0 and 1). ? memory map the x/y memory is located in the virtual addr ess space, physical addre ss space, and x-bus and y-bus address spaces. in the virtual address space, this memory is locat ed in the addresses show n in table 6.1. these addresses are included in space p2 (when sr.md = 1) or uxy (when sr.md = 0 and sr.dsp = 1) according to the cpu operating mode. table 6.1 x/y memory virtual addresses page memory size (total four pages) 16 kbytes page 0 of x memory h' a5007000 to h'a5007fff page 1 of x memory h' a5008000 to h'a5008fff page 0 of y memory h' a5017000 to h'a5017fff page 1 of y memory h' a5018000 to h'a5018fff on the other hand, this memory is located in a pa rt of area 1 in the physi cal address space. when this memory is accessed from the physical address space, addresses in which the upper three bits are 0 in addresses shown in table 6.1 are used. in the x-bus and y-bus addr ess spaces, addresses in which the upper 16 bits are ignored in addresses of x memory and y memory shown in table 6.1 are used. ? ports each page has three independent read/write ports and is connected to each bus. the x memory is connected to the i bus, x bus, and l bus. the y memory is c onnected to the i bus, y bus, and l bus. the l bus is used when this memo ry is accessed from the virtual address space. the i bus is used when this memory is accesse d from the physical address space. the x bus and y bus are used when this memory is accessed from the x- bus and y-bus address spaces. section 6 x/y memory rev. 3.00 jan. 18, 2008 page 214 of 1458 rej09b0033-0300 ? priority order in the event of simultaneous accesses to the sa me page from different buses, the accesses are processed according to the priority order. the priority order is: i bus > x bus > l bus in the x memory and i bus > y bus > l bus in the y memory. 6.2 operation 6.2.1 access from cpu methods for accessing by the cpu are directly vi a the l bus from the virtual addresses, and via the i bus after the virtual addresses are converted to be the physical addresses using the mmu. as long as a conflict on the page does not occur, access via the l bus is performed in one cycle. several cycles are necessary fo r accessing via the i bus. accordin g to the cpu operating mode, access from the cpu is as follows: (1) privileged mode and privileged dsp mode (sr. md = 1) the x/y memory can be accessed by the cpu dir ectly from space p2. the mmu can be used to map the virtual addresses in spaces p0 and p3 to this memory. (2) user dsp mode (sr.md = 0 and sr.dsp = 1) the x/y memory can be accessed by the cpu dir ectly from space uxy. the mmu can be used to map the virtual addresses in space u0 to this memory. (3) user mode (sr.md = 0 and sr.dsp = 0) the mmu can be used to map the virtual addresses in space u0 to this memory. 6.2.2 access from dsp methods for accessing from the ds p differ according to instructions. with a x data transfer instruction and a y data transfer instruction, the x/y memory is always accessed via the x bus or y bus. as long as a conflict on the page does not occur, access via the x bus or y bus is performed in one cycle. the x memory access via the x bus and the y memory access via the y bus can be performed simultaneously. in the case of a single data transfer instructio n, methods for accessing from the dsp are directly via the l bus from the virtual addresses, and via th e i bus after the virtual addresses are converted to be the physical addresses using the mmu. as long as a conflict on the page does not occur, section 6 x/y memory rev. 3.00 jan. 18, 2008 page 215 of 1458 rej09b0033-0300 access via the l bus is performed in one cycle. se veral cycles are necessary for accessing via the i bus. according to the cpu operating mode, access from the cpu is as follows: (1) privileged dsp mode (sr. md = 1 and sr.dsp = 1) the x/y memory can be accessed by the dsp dir ectly from space p2. the mmu can be used to map the virtual addresses in spaces p0 and p3 to this memory. (2) user dsp mode (sr.md = 0 and sr.dsp = 1) the x/y memory can be accessed by the dsp dir ectly from space uxy. the mmu can be used to map the virtual addresses in space u0 to this memory. 6.2.3 access from bus master module the x/y memory is always accessed by bus master modules such as the dmac and usb host via the i bus, which is a physical address bus. addr esses in which the upper three bits are 0 in addresses shown in table 6.1 must be used. 6.3 usage notes 6.3.1 page conflict in the event of simultaneous accesses to the same page from different buses, the conflict on the pages occurs. although each access is completed corr ectly, this kind of co nflict tends to lower x/y memory accessibility. therefore it is advisable to provide software measures to prevent such conflict as far as possible. for example, conflic t will not arise if different memory or different pages are accessed by each bus. 6.3.2 bus conflict the i bus is shared by several bus master mo dules. when the x/y memo ry is accessed via the i bus, a conflict between the other i-bus master modules may occur on the i bus. this kind of conflict tends to lower x/y memo ry accessibility. therefore it is advisable to provide software measures to prevent such conflic t as far as possible. for exampl e, by accessing the x/y memory by the cpu not via the i bus but directly from space p2 or uxy, conflict on the i bus can be prevented. section 6 x/y memory rev. 3.00 jan. 18, 2008 page 216 of 1458 rej09b0033-0300 6.3.3 mmu and cache settings when the x/y memory is accessed via the i bus using the cache from the cpu and dsp, correct operation cannot be guaranteed. if the x/y me mory is accessed while the cache is enabled (ccr1.ce = 1), it is advisable to access the x/y me mory via the l bus from space p2 or uxy. if the x/y memory is accessed from space p0, p3, or u0, it is advisable to access the x/y memory via the i bus, which does not use the cache, with mmu setting enabled (mmucr.at = 1) and cache disabled (c bit = 0) as page attributes. since access using the mmu occurs via the i bus, several cycles are necessary (the number of necessary cycles varies according to the ratio between the internal clock (i ) and bus clock (b ) or the operation state of th e dmac). in a program that requires high performance, it is advisable to access the x/y me mory from space p2 or uxy. the relationship described above is summarized in table 6.2. table 6.2 mmu an d cache settings setting virtual address space a nd access enabled or disabled ccr1.ce mmucr.at p0, u0 p1 p2, uxy p3 0 0 b b a b 0 1 b b a b 1 0 x x a x 1 1 c x a c note: a: accessible (recommended) b: accessible c: accessible (note that mmu page attribute must be specified as cache disabled by clearing the c bit to 0.) x: not accessible 6.3.4 sleep mode in sleep mode, i bus master modules such as the dmac cannot access the x/y memory. section 7 exception handling rev. 3.00 jan. 18, 2008 page 217 of 1458 rej09b0033-0300 section 7 exception handling exception handling is separate from normal program processing, and is performed by a routine separate from the normal program. for example, if an attempt is made to execute an undefined instruction code or an instruction protected by the cpu processing mode, a control function may be required to return to the source program by executing the appropriate operation or to report an abnormality and carry out end processing. in additio n, a function to control processing requested by lsi on-chip modules or an lsi external module to the cpu may also be required. transferring control to a user-defined exception processing routine and executing the process to support the above functions are called exception handling. this lsi has two types of exceptions: general exceptions and interrupts. the user can execute the required processing by assigning exception handling routines corresponding to the requ ired exception processing and then return to the source program. a reset input can terminate the normal program execution and pass control to the reset vector after register initialization. this reset operation can also be regarded as an exception handling. this section describes an overview of the exception handling operation. here, general exceptions and interrupts are referred to as exception handling. for interrupts, this section describes only the process executed for interrupt requests. for details on how to generate an interrupt request, refer to section 8, interrupt controller (intc). 7.1 register descriptions there are five registers for exception handling. a register with an undefined initial value should be initialized by the software. refer to section 37, list of registers, for more details on the addresses and access size of these registers. ? trapa exception register (tra) ? exception event register (expevt) ? interrupt event register (intevt) ? interrupt event register 2 (intevt2) ? exception address register (tea) section 7 exception handling rev. 3.00 jan. 18, 2008 page 218 of 1458 rej09b0033-0300 figure 7.1 shows the bit configuration of each register. 31 tra expevt intevt2 tra expevt intevt2 tea tea 10 9 2 1 0 31 12 11 0 0 0 0 0 31 12 11 0 intevt intevt 0 31 12 11 0 31 0 figure 7.1 register bit configuration 7.1.1 trapa exception register (tra) tra is assigned to address h'ffffffd0 and consis ts of the 8-bit immediate data (imm) of the trapa instruction. tra is automatically specified by the hardware when the trapa instruction is executed. only bits 9 to 2 of the tra can be re-written using the software. bit bit name initial value r/w description 31 to 10 ? ? r reserved these bits are always read as 0. the write value should always be 0. 9 to 2 tra ? r/w 8-bit immediate data 1, 0 ? ? r reserved these bits are always read as 0. the write value should always be 0. section 7 exception handling rev. 3.00 jan. 18, 2008 page 219 of 1458 rej09b0033-0300 7.1.2 exception event register (expevt) expevt is assigned to address h'ffffffd4 and consists of a 12-bit exception code. exception codes to be specified in expevt are those for resets and general exceptions. these exception codes are automatically specified the hardware when an exception occurs. only bits 11 to 0 of expevt can be re-written using the software. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 expevt * r/w 12-bit exception code note: initialized to h'000 at power-on reset and h'020 at manual reset. 7.1.3 interrupt even t register (intevt) intevt is assigned to addres s h'ffffffd8 and stor es an exception code or a code which indicates interrupt priority order. a code to be sp ecified when an interrupt occurs is determined by an interrupt source. (for details, see section 8.4.6, interrupt exception handling and priority.) these exception and interrupt priority order code s are automatically specified by the hardware when an exception occurs. intevt can be modified using the software. only bits 11 to 0 of intevt can be modified using the software. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 intevt ? r 12-bit exception code section 7 exception handling rev. 3.00 jan. 18, 2008 page 220 of 1458 rej09b0033-0300 7.1.4 interrupt event register 2 (intevt2) intevt2 is assigned to address h'a4000000 and consists of a 12-bit exception code. exception codes to be specified in intevt2 are those for interrupt requests. these exception codes are automatically specified by the hardware when an exception occurs. intevt2 cannot be modified using the software. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 intevt2 ? r 12-bit exception code 7.1.5 exception address register (tea) tea is assigned to address h'fffffffc and the vi rtual address for an exception occurrence is stored in this register when an exception relate d to memory accesses occurs. tea can be modified using the software. bit bit name initial value r/w description 31 to 0 tea all 0 r/w the virtual address for an exception occurrence section 7 exception handling rev. 3.00 jan. 18, 2008 page 221 of 1458 rej09b0033-0300 7.2 exception handling function 7.2.1 exception handling flow in exception handling, the contents of the program counter (pc) and status register (sr) are saved in the saved program counter (spc) and saved status register (ssr), respectively, and execution of the exception handler is invoked from a vector address. by executing th e return from exception handler (rte) in the exception handler routine, it restores the contents of pc and sr, and returns to the processor state at the poi nt of interruption and the addre ss where the exception occurred. a basic exception handling sequence consists of the following operations. if an exception occurs and the cpu accepts it, operations 1 to 8 are executed. 1. the contents of pc is saved in spc. 2. the contents of sr is saved in ssr. 3. the block (bl) bit in sr is set to 1, masking any subsequent exceptions. 4. the mode (md) bit in sr is set to 1 to place the privileged mode. 5. the register bank (rb) bit in sr is set to 1. 6. an exception code identifying the exception event is written to bits 11 to 0 of the exception event register (expevt); an excep tion code identifying the interrupt request is written to bits 11 to 0 of the interrupt event register (in tevt) or interrupt event register 2 (intevt2). 7. if a trapa instruction is executed, an 8-bit immediate data specified by the trapa instruction is set to tra. for an exception related to memory accesses, the logic address where the exception occurred is written to tea.* 1 8. instruction execution jumps to the designated exception vector address to invoke the handler routine. the above operations from 1 to 8 are executed in sequence. during these operations, no other exceptions may be accepted unless multiple exception accepta nce is enabled. in an exception handling routine for a general ex ception, the appropriate exception handling must be executed based on an exception source determined by the expevt. in an interrupt exception handling routine, the appropriate exception handlin g must be executed based on an exception source determined by the intevt or intevt2. after the exception handling routine has been completed, program execution can be resumed by executing an rte instruction. the rte instruction causes the following operations to be executed. section 7 exception handling rev. 3.00 jan. 18, 2008 page 222 of 1458 rej09b0033-0300 1. the contents of the ssr are restored into the sr to return to the pro cessing state in effect before the exception handling took place. 2. a delay slot instruction of the rte instruction is executed.* 2 3. control is passed to the address stored in the spc. the above operations from 1 to 3 are executed in sequence. during these operations, no other exceptions may be accepted. by changing the spc and ssr before executing the rte instruction, a status different from that in effect before the exception handling can also be specified. notes: 1. the mmu registers are also modified if an mmu exception occurs. 2. for details on the cpu processing mode in which rte delay slot instructions are executed, please refer to s ection 7.5, usage notes. 7.2.2 exception vector addresses a vector address for general exceptions is determined by adding a vector offset to a vector base address. the vector offset for general exce ptions other than the tlb miss exception is h'00000100. the vector offset for interrupts is h'00000600. the vector base address is loaded into the vector base register (vbr) using the software. the vector base address should reside in the p1 or p2 fixed physical address space. 7.2.3 exception codes the exception codes are written to bits 11 to 0 of the expevt (for reset or general exceptions) or the intevt and intevt2 (for interrupt requests) to identify each specific exception event. see section 8, interrupt controller (intc), for details of the exception codes for interrupt requests. table 7.1 lists exception codes for resets and general exceptions. 7.2.4 exception request and bl bit (multiple exception prevention) the bl bit in sr is set to 1 when a reset or exce ption is accepted. while th e bl bit is set to 1, acceptance of general exceptions is restricted as de scribed below, making it possible to effectively prevent multiple excep tions from being accepted. if the bl bit is set to 1, an interrupt request is not accepted and is retained. the interrupt request is accepted when the bl bit is clear ed to 0. if the cpu is in low power consum ption mode, an interrupt is accepted even if the bl bit is set to 1 and the cpu returns from the low power consumption mode. section 7 exception handling rev. 3.00 jan. 18, 2008 page 223 of 1458 rej09b0033-0300 a dma error is not accepted and is retained if the bl bit is set to 1 and accepted when the bl bit is cleared to 0. user break requests generated while the bl bit is set are ignored and are not retained. accordingly, user breaks are not accep ted even if the bl bit is cleared to 0. if a general exception other than a dma address error or user break occurs wh ile the bl bit is set to 1, the cpu enters a state similar to that in e ffect immediately after a re set, and passes control to the reset vector (h'a0000000) (multiple exception). in this case, unlike a normal reset, modules other than the cpu are not initialized, the contents of expevt, spc, and ssr are undefined, and this status is not detected by an external device. to enable acceptance of multiple exceptions, the contents of spc and ssr must be saved while the bl bit is set to 1 after an exception has been accepted, and then the bl bit must be cleared to 0. before restoring the spc and ssr, the bl bit must be set to 1. 7.2.5 exception source accepta nce timing and priority (1) exception request of instruction synchr onous type and instruction asynchronous type resets and interrupts are requested asynchronously regardless of the program flow. in general exceptions, a dma address error and a user break under the specific condition are also requested asynchronously. the user cannot expect on whic h instruction an exception is requested. for general exceptions other than a dma address error and a user break under a specific condition, each general exception corresponds to a specific instruction. (2) re-execution type and proce ssing-completion type exceptions all exceptions are classified into two types: a re-execution type and a processing-completion type. if a re-execution type exception is accepted, the curr ent instruction executed when the exception is accepted is terminated and the in struction address is saved to the spc. after returning from the exception processing, program execution resumes from the instruction wh ere the exception was accepted. in a processing-comple tion type exception, th e current instruction executed when the exception is accepted is completed, the next instru ction address is saved to the spc, and then the exception processing is executed. during a delayed branch instruction and delay slot, the following operations are executed. a re- execution type exception detected in a delay slot is accepted before executing the delayed branch instruction. a processing-completion type exception detected in a delayed branch instruction or a delay slot is accepted when the delayed branch in struction has been executed. in this case, the acceptance of delayed branch instru ction or a delay slot precedes the execution of the branch destination instruction. in the above description, a delay slot indicates an instruction following an section 7 exception handling rev. 3.00 jan. 18, 2008 page 224 of 1458 rej09b0033-0300 unconditional delayed branch instruction or an instruction following a conditional delayed branch instruction whose branch condition is satisfied. if a branch does not occur in a conditional delayed branch, the normal processing is executed. (3) acceptance priority and test priority acceptance priorities are determin ed for all exception requests. the priority of resets, general exceptions, and interrupts are determin ed in this order: a reset is always accepted regardless of the cpu status. interrupts are accepted only when re sets or general exceptions are not requested. if multiple general exceptions occur simultaneously in the same instruction, the priority is determined as follows. 1. a processing-completion type exception generated at the previous instruction* 2. a user break before instruction execution (re-execution type) 3. an exception related to an instruction fetch (cpu address error and mmu related exceptions: re-execution type) 4. an exception caused by an instruction decode (general illegal instru ction exceptions and slot illegal instruction exceptions: re-execution ty pe, unconditional trap: processing-completion type) 5. an exception related to data access (cpu address error and mmu related exceptions: re- execution type) 6. unconditional trap (processing-completion type) 7. a user break other than one before instruction execution (processing-completion type) 8. dma address error (processing-completion type) note: * if a processing-completion type excepti on is accepted at an instruction, exception processing starts before the next instruction is executed. this exception processing executed before an exception generated at the next instruction is detected. only one exception is accepted at a time. acceptin g multiple exceptions sequ entially results in all exception requests being processed. section 7 exception handling rev. 3.00 jan. 18, 2008 page 225 of 1458 rej09b0033-0300 table 7.1 exception event vectors exception type current instruction exception event priority * 1 exception order process at bl=1 vector code vector offset power-on reset 1 1 reset h'000 ? reset (asynchro- nous) aborted manual reset 1 2 reset h'020 ? user break(before instruction execution) 2 0 ignored h'1e0 h'00000100 cpu address error (instruction access) * 4 2 1 reset h'0e0 h'00000100 tlb miss (instruction access) * 4 * 5 2 1-1 reset h'040 h'00000400 tlb invalid (instruction access) * 4 * 5 2 1-2 reset h'040 h'00000100 tlb protection violation (instruction access) * 4 * 5 2 1-3 reset h'0a0 h'00000100 illegal general instruction exception 2 2 reset h'180 h'00000100 illegal slot instruction exception 2 2 reset h'1a0 h'00000100 cpu address error (data access) * 4 2 3 reset h'0e0/ h'100 h'00000100 re-executed tlb miss (data access) * 4 * 5 2 3-1 reset h'040/ h'060 h'00000400 tlb invalid (data access) * 4 * 5 2 3-2 reset h'040/ h'060 h'00000100 tlb protection violation (data access) * 4 * 5 2 3-3 reset h'0a0/ h'0c0 h'00000100 re-executed initial page write (data access) * 4 * 5 2 3-4 reset h'080 h'00000100 unconditional trap (trapa instruction) 2 4 reset h'160 h'00000100 general exception events (synchro- nous) completed user breakpoint (after instruction execution, address) 2 5 ignored h'1e0 h'00000100 section 7 exception handling rev. 3.00 jan. 18, 2008 page 226 of 1458 rej09b0033-0300 exception type current instruction exception event priority * 1 exception order process at bl=1 vector code vector offset user breakpoint (data break, i-bus break) 2 5 ignored h'1e0 h'00000100 general exception events (asynchro- nous) completed dma address error 2 6 retained h'5c0 h'00000100 general interrupt requests (asynchro- nous) completed interrupt requests 3 ? * 2 retained ? * 3 h'00000600 notes: 1. priorities are indicated from high to low, 1 being the highest and 3 the lowest. a reset has the highest priority. an interrupt is accepted only when general exceptions are not requested. 2. for details on priorities in multiple in terrupt sources, refer to section 8, interrupt controller (intc). 3. if an interrupt is accepted, the exceptio n event register (expevt) is not changed. the interrupt source code is specified in the interrupt event registers (intevt and intevt2). for details, refer to secti on 8, interrupt controller (intc). 4. if one of these exceptions occurs in a specif ic part of the repeat loop, a specific code and vector offset are specified. 5. these exception codes are valid when the mmu is used. section 7 exception handling rev. 3.00 jan. 18, 2008 page 227 of 1458 rej09b0033-0300 7.3 individual exception operations this section describes the conditions for specific exception handling, and the processor operations. this section describes resets and general exceptio ns. for interrupt operations, refer to section 8, interrupt controller (intc). 7.3.1 resets (1) power-on reset ? conditions power-on reset is request ? operations set expevt to h'000, initialize the cpu and on-chip peripheral modules, and branch to the reset vector h'a0000000. for details, refer to the register descriptions in the relevant sections. (2) manual reset ? conditions manual reset is request ? operations set expevt to h'020, initialize the cpu and on-chip peripheral modules, and branch to the reset vector h'a0000000. for details, refer to the register descriptions in the relevant sections. 7.3.2 general exceptions (1) cpu address error ? conditions ? instruction is fetched from odd address (4n + 1, 4n + 3) ? word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3) ? longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) ? the area ranging from h'8000000 0 to h'ffffffff in virtual space is accessed in user mode ? types instruction synchronous, re-execution type section 7 exception handling rev. 3.00 jan. 18, 2008 page 228 of 1458 rej09b0033-0300 ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an ex ception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code an exception occurred during read: h'0e0 an exception occurred during write: h'100 ? remarks the virtual address (32 bits) that caused the exception is set in tea. (2) illegal general in struction exception ? conditions ? when undefined code not in a delay slot is decoded delayed branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s note: for details on undefined code, refer to table 2.12. when an undefined code other than h'f000 to h'ffff is decoded, operation cannot be guaranteed. ? when a privileged instruction not in a delay slot is decoded in user mode privileged instructions: ldc, stc, rte, ldtlb, sleep; instructions that access gbr with ldc/stc are not privileged instructions. ? types instruction synchronous, re-execution type ? save address an instruction address wh ere an exception occurs ? exception code h'180 ? remarks none section 7 exception handling rev. 3.00 jan. 18, 2008 page 229 of 1458 rej09b0033-0300 (3) illegal slot instruction ? conditions ? when undefined code in a delay slot is decoded delayed branch instructions: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt/s, bf/s ? when a privileged instruction in a delay slot is decoded in user mode privileged instructions: ldc, stc, rte, ldtlb, sleep; instructions that access gbr with ldc/stc are not privileged instructions. ? when an instruction that rewrites pc in a delay slot is decoded instructions that rewrite pc: jmp, jsr, bra, braf, bsr, bsrf, rts, rte, bt, bf, bt/s, bf/s, trapa, ldc rm, sr, ldc.l @rm+, sr ? types instruction synchronous, re-execution type ? save address a delayed branch instruction address ? exception code h'1a0 ? remarks none (4) unconditional trap ? conditions trapa instruction executed ? types instruction synchronous, processing-completion type ? save address an address of an instruction following trapa ? exception code h'160 ? remarks the exception is a processing-completion type, so an instruction after the trapa instruction is saved to spc. the 8-bit immediate value in the trapa instruction is set in tra[9:2]. section 7 exception handling rev. 3.00 jan. 18, 2008 page 230 of 1458 rej09b0033-0300 (5) user break point trap ? conditions when a break condition set in the us er break controller is satisfied ? types break (l bus) before instruction execution: instruction synchronous, re-execution type operand break (l bus): instruction synchronous, processing-completion type data break (l bus): instruction asynchronous, processing-completion type i bus break: instruction asynchronous, processing-completion type ? save address re-execution type: an address of the instruction where a break occurs (a delayed branch instruction address if an instruc tion is assigned to a delay slot) processing-completion type: an address of the instruction following the instruction where a break occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) ? exception code h'1e0 ? remarks for details on user break controller, refer to section 33, user break controller (ubc). (6) dma address error ? conditions ? word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) ? longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) ? types instruction asynchronous, processing-completion type ? save address an address of the instruction following the inst ruction where a break occurs (a delayed branch instruction destination address if an instruction is assigned to a delay slot) ? exception code h'5c0 section 7 exception handling rev. 3.00 jan. 18, 2008 page 231 of 1458 rej09b0033-0300 ? remarks an exception occurs when a dma transfer is ex ecuted while an exception instruction address described above is specified in the dmac. since the dma transfer is performed asynchronously with the cpu instruction op eration, an exception is also requested asynchronously with the instruction execution. for details on dmac, refer to section 10, direct memory acce ss controller (dmac). 7.3.3 general exceptio ns (mmu exceptions) when the address translation unit of the memory management unit (mmu) is valid, mmu exceptions are checked after a cpu address er ror has been checked. four types of mmu exceptions are defined: tlb miss exception, tlb invalid exception, tlb protection exception, initial page write exception. these exceptions are checked in this order. a vector offset for a tlb miss exception is defi ned as h'00000400 to simplify exception source determination. for details on mmu exception opera tions, refer to section 4, memory management unit (mmu). (1) tlb miss exception ? conditions comparison of tlb addresses shows no address match. ? types instruction synchronous, re-execution type ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an ex ception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code an exception occurred during read: h'040 an exception occurred during write: h'060 ? remarks ? the virtual address (32 bits) that caused the excep tion is set in tea, an d the mmu register is updated. the vector address for tlb miss exception is vbr + h'0400. to speed up tlb miss processing, the offset differs from other exceptions. section 7 exception handling rev. 3.00 jan. 18, 2008 page 232 of 1458 rej09b0033-0300 (2) tlb invalid exception ? conditions comparison of tlb addresses shows address match but v = 0. ? types instruction synchronous, re-execution type ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an ex ception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code an exception occurred during read: h'040 an exception occurred during write: h'060 ? remarks the virtual address (32 bits) that caused the excep tion is set in tea, and the mmu register is updated. (3) tlb protection exception ? conditions when a hit access violates the tlb protection information (pr bits). ? types instruction synchronous, re-execution type ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an ex ception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code an exception occurred during read: h'0a0 an exception occurred during write: h'0c0 ? remarks the virtual address (32 bits) that caused the excep tion is set in tea, and the mmu register is updated. section 7 exception handling rev. 3.00 jan. 18, 2008 page 233 of 1458 rej09b0033-0300 (4) initial page write exception ? conditions a hit occurred to the tlb for a store access, but d = 0. ? types instruction synchronous, re-execution type ? save address instruction fetch: an instruction address to be fetched when an exception occurred data access: an instruction address where an ex ception occurs (a delayed branch instruction address if an instruction is assigned to a delay slot) ? exception code h'080 ? remarks the virtual address (32 bits) that caused the excep tion is set in tea, an d the mmu register is updated. section 7 exception handling rev. 3.00 jan. 18, 2008 page 234 of 1458 rej09b0033-0300 7.4 exception processing while dsp extension function is valid when the dsp extension function is valid (the dsp bit in sr is set to 1), some exception processing acceptance conditions or exception processing may be changed. 7.4.1 illegal instruction exception and illegal slot instruction exception in the dsp mode, a dsp extension instruction can be executed. if a dsp ex tension instruction is executed when the dsp bit in sr is cleared to 0 (in a mode other than the dsp mode), an illegal instruction exception occurs. in the dsp mode, stc and ldc instructions for th e sr register can be executed even in user mode. (note, however, that only the rc[11:0], dmx, dmy, and rf[1:0] bits in the dsp extension bits can be changed.) 7.4.2 cpu address error in the dsp mode, a part of the space p2 (uxy area: h'a5000000 to h'a5ffffff) can be accessed in user mode and no cpu address error will occur even if the area is accessed. 7.4.3 exception in repeat control period if an exception is requested or an exception is accepted during repeat control, the exception may not be accepted correctly or a program executio n may not be returned correctly from exception processing that is different fr om the normal state. these rest rictions may occur from repeat detection instruction to repeat end instruction while the repeat counter is 1 or more. in this section, this period is called the repeat control period. the following shows program exampl es where the number of instructions in th e repeat loop are 4 or more, 3, 2, and 1, respectively. in this section, a repeat detection instruction and its instruction address are described as rptdtct. the first, seco nd, and third instructions following the repeat detection instruction are described as rptdtct1, rptdtct2, and rptdtct3. in addition, [a], [b], [c1], and [c2] in the following examples indicat e instructions where a re striction occurs. table 7.2 summarizes the instruction positions and restriction types. section 7 exception handling rev. 3.00 jan. 18, 2008 page 235 of 1458 rej09b0033-0300 table 7.2 instruction positi ons and restriction types instruction position spc * 1 illegal instruction * 2 interrupt, break * 3 cpu address error * 4 [a] [b] retained [c1] added retained instruction/data [c2] illegal added retained instruction/data notes: 1. a specific address is specified in the spc if an exception oc curs while sr.rc[11:0] 2. 2. there are a greater number of instructions that can be illegal instructions while sr.rc[11:0] 1. 3. an interrupt, break or dma address e rror request is retain ed while sr.rc[11:0] 1. 4. a specific exception code is specified while sr.rc[11:0] 1. ? example 1: repeat loop consisting of four or greater instructions ldrs rptstart ; [a] ldre rptdtct + 4 ; [a] setrc #4 ; [a] instr0 ; [a] rptstart: instr1 ; [a][repeat start instruction] ??? ; [a] ??? ; [a] rptdtct: rptdtct ; [b] a repeat detection instruction is an instruction three instructions before a repeat end instruction rptdtct1 ; [c1] rptdtct2 ; [c2] rptend: rptdtct3 ; [c2][repeat end instruction] instrnext ; [a] section 7 exception handling rev. 3.00 jan. 18, 2008 page 236 of 1458 rej09b0033-0300 ? example 2: repeat loop consisting of three instructions ldrs rptdtct + 4 ; [a] ldre rptdtct + 4 ; [a] setrc #4 ; [a] rptdtct: rptdtct ; [b] a repeat detection instruction is an instruction prior to a repeat start instruction rptstart: rptdtct1 ; [c1][repeat start instruction] rptdtct2 ; [c2] rptend: rptdtct3 ; [c2][repeat end instruction] instrnext ; [a] ? example 3: repeat loop consisting of two instructions ldrs rptdtct + 6 ; [a] ldre rptdtct + 4 ; [a] setrc #4 ; [a] rptdtct: rptdtct ; [b] a repeat detection instruction is an instruction prior to a repeat start instruction rptstart: rptdtct1 ; [c1][repeat start instruction] rptend: rptdtct2 ; [c2][repeat end instruction] instrnext ; [a] ? example 4: repeat loop consisting of one instruction ldrs rptdtct + 8 ; [a] ldre rptdtct + 4 ; [a] setrc #4 ; [a] rptdtct: rptdtct ; [b] a repeat detection instruction is an instruction prior to a repeat start instruction rptstart: rptend: rptdtct1 ; [c1][repeat start instruction]== [repeat end instruction] instrnext ; [a] section 7 exception handling rev. 3.00 jan. 18, 2008 page 237 of 1458 rej09b0033-0300 (1) spc saved by an exception in repeat control period if an exception is accepted in the repeat control pe riod while the repeat counter (rc[11:0]) in the sr register is two or greater, the program counter to be saved may not indicate the value to be returned correctly. to execute the repeat control after returning from an exception processing, the return address must indicate an in struction prior to a repeat detect ion instruction. accordingly, if an exception is accepted in repeat control period, an exception other than re-execution type exception by a repeat detection instruction cannot return to the repeat control correctly. table 7.3 spc value when a re-execution ty pe exception occurs in repeat control (sr.rc[11:0] 2) number of instructions in a repeat loop instruction where an exception occurs 1 2 3 4 or greater rptdtct rptdtct rptd tct rptdtct rptdtct rptdtct1 rptdtct1 rptdtc t1 rptdtct1 rptdtct1 rptdtct2 ? rptdtct1 rptdtct1 rs-4 rptdtct3 ? ? rptdtct1 rs-2 note: the following labels are used here. rptdtct: repeat detection instruction address rptdtct1: instruction addr ess immediately after the repeat detect instruction rptdtct2: second instruction addre ss from the repeat detect instruction rptdtct3: third instruction address from the repeat detect instruction rs: repeat start instruction address if a re-execution type exception is accepted at an instruction in the hatched areas above, a return address to be saved in the spc is incorrec t. if sr.rc[11:0] is 1 or 0, a correct return address is saved in the spc. section 7 exception handling rev. 3.00 jan. 18, 2008 page 238 of 1458 rej09b0033-0300 (2) illegal instruction exception in repeat control period if one of the following instructions is executed at the address following rptdtct1, a general illegal instruction exception occurs. for details on an address to be saved in the spc, refer to spc saved by an exception in repeat control period in section 7.4.3, exception in repeat control period. ? branch instructions bra, bsr, bt, bf, bt/s, bf/s, bsrf, rts, braf, rte, jsr, jmp, trapa ? repeat control instructions setrc, ldrs, ldre ? load instructions for sr, rs, and re ldc rn,sr, ldc @rn+,sr, ldc rn,re, ld c @rn+,re, ldc rn,rs, ldc @rn+, rs note: an extension instruction of this lsi and is not disclosed to the user. in a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. in a repeat loop consisting of four or more instructions, restrictions apply to only the three instructions that include a repeat end instruction. (3) an exception retained in repeat control period in the repeat control period, an interrupt or so me exception will be retained to prevent an exception acceptance at an instruction where return ing from the exception cannot be performed correctly. for details, refer to repeat loop progra m examples 1 to 4. in the examples, exceptions generated at instructions indicated as [b], [c], ([c1], or [c2]), the following processing is executed. ? interrupt, dma address error an exception request is not accepted and retained at instructions [b] and [c]. if an instruction indicates as [a] is executed at the next time, an exception request is accepted.* as shown in examples 1 to 4, any interrupt or dma addre ss error cannot be accept ed in a repeat loop consisting of four instructions or less. note: an interrupt request or a dma address erro r exception request is retained in the interrupt controller (intc) and the direct memory access controller (dmac) until the cpu can accept a request. section 7 exception handling rev. 3.00 jan. 18, 2008 page 239 of 1458 rej09b0033-0300 ? user break before instruction execution a user break before instructio n execution is accepted at instruction [b], and an address of instruction [b] is saved in the spc. this exce ption cannot be accepted at instruction [c] but the exception request is retained until an instru ction [a] or [b] is executed at the next time. then, the exception request is accep ted before an instruction [a] or [b] is executed. in this case, an address of instruction [a] or [b] is saved in the spc. ? user break after instruction execution a user break after instruction execution cannot be accepted at instructions [b] and [c] but the exception request is retained until an instruction [a ] or [b] is executed at the next time. then, the exception request is accepted before an instruct ion [a] or [b] is executed. in this case, an address of instruction [a] or [b] is saved in the spc. table 7.4 exception accept ance in the repeat loop exception type instruction [b] instruction [c] interrupt not accepted not accepted dma address error not accepted not accepted user break before instruction ex ecution accepted not accepted user break after instruction exec ution not accepted not accepted (4) cpu address error in repeat control period if a cpu address error occurs in the repeat control period, th e exception is accepted but an exception code (h'070) indicating the repeat loop period is specified in the expevt. if a cpu address error occurs in instru ctions following a repeat detect ion instruction to repeat end instruction, an exception code for instruction access or data acce ss is specified in the expevt. the spc is saved according to the description, spc saved by an exception in repeat control period in section 7.4.3, exception in repeat control period. after the cpu address error exceptio n processing, the repeat control cannot be returned correctly. to execute a repeat loop correctly, care must be taken not to generate a cpu address error in the repeat control period. note: in a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. in a repeat loop consisting of four or more instructions, restrictions apply to only the three instructions that include a repeat end instruction. the restric tion occurs when sr.rc[11:0] 1. section 7 exception handling rev. 3.00 jan. 18, 2008 page 240 of 1458 rej09b0033-0300 table 7.5 instruction where a specific ex ception occurs when a memory access exception occurs in repe at control (sr.rc[11:0] 1) number of instructions in a repeat loop instruction where an exception occurs 1 2 3 4 or greater rptdtct ? ? ? ? rptdtct1 instruction/data access instruction/data access instruction/data access instruction/data access rptdtct2 ? instruction/data access instruction/data access instruction/data access rptdtct3 ? ? instruction/data access instruction/data access note: the following labels are used here. rptdtct: repeat detection instruction address rptdtct1: instruction addr ess immediately after the repeat detect instruction rptdtct2: second instruction addre ss from the repeat detect instruction rptdtct3: third instruction address from the repeat detect instruction (5) mmu exception in repeat control period if an mmu exception occurs in the repeat control period, a specific exception code is generated as well as a cpu address error. for a tlb miss exce ption, tlb invalid exception, and initial page write exception, an exception code (h'070) indicatin g the repeat loop period is specified in the expevt. for a tlb protection exception, an exception code (h'0d0) is specified in the expevt. in a tlb miss exception, vector offset is specified as h'00000100. an instruction where an exception occurs and the spc value to be saved are the same as those for the cpu address error. after this exception processing, the repeat cont rol cannot be returned correctly. to execute a repeat loop correctly, care must be taken not to generate an mmu related exception in the repeat control period. note: in a repeat loop consisting of one to three instructions, some restrictions apply to repeat detection instructions and all the remaining instructions. in a repeat loop consisting of four or more instructions, restrictions apply to only the three instructions that include a repeat end instruction. the restric tion occurs when sr.rc[11:0] 1. section 7 exception handling rev. 3.00 jan. 18, 2008 page 241 of 1458 rej09b0033-0300 7.5 usage notes 1. an instruction assigned at a delay slot of the rte instruction is executed after the contents of the ssr is restored into the sr. an acceptance of an exception related to instruction access is determined according to the sr before rest ore. an acceptance of other exceptions is determined by processing mode of the sr after restore, and bl bit value. a processing- completion type exception is accep ted before an instruction at the rte branch destination address is executed. however, no te that the correct operation ca nnot be guaranteed if a re- execution type exception occurs. 2. in an instruction assigned at a delay slot of the rte instruction, a user break cannot be accepted. 3. if the md and bl bits of the sr register are changed by the ldc instru ction, an exception is accepted according to the changed sr value fr om the next instruction.* a processing- completion type exception is accep ted before the next instructio n is executed. an interrupt and dma address error in re-execution type exceptions are accepted before the next instruction is executed. note: * if an ldc instruction is executed for the sr, the following instru ctions are re-fetched and an instruction fetch exception is accept ed according to the modified sr value. section 7 exception handling rev. 3.00 jan. 18, 2008 page 242 of 1458 rej09b0033-0300 section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 243 of 1458 rej09b0033-0300 section 8 interrupt controller (intc) the interrupt controller (intc) determines the prio rity of interrupt sources and controls interrupt requests to the cpu. the intc registers set the priority of each interrupt , allowing the user to process interrupt requests accordi ng to the user-set priority. 8.1 features ? 16 levels of interrupt priority can be set by setting the interrupt-priority registers, the pr iorities of on-chip peripheral modules, and irq and pint interrupts can be selected from 16 levels for individual request sources. ? nmi noise canceller function an nmi input-level bit indicates the nmi pin state. by reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as a noise canceller. ? irq interrupts can be set detection of low level, high level, rising edge, or falling edge ? interrupt request signal can be externally output ( irqout pin) by notifying the external bus ma ster that the extern al interrupt and on-chip peripheral module interrupt requests have been generated, the bus mastership can be requested. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 244 of 1458 rej09b0033-0300 figure 8.1 shows a block diagram of the interrupt controller. input/output control priority identifier com- parator interrupt request sr cpu bus interface internal bus intc i3 i2 i1 i0 (interrupt request) icr irr0 pinter 6 4 16 irq5 to irq0 nmi pint5 to pint0 irl3 to irl0 irlqout ipr [legend] interrupt control register interrupt priority register interrupt request register pint interrupt enable register refresh request in bus state controller icr: ipr: irr: pinter: ref: dmac scif siof tmu tpu wdt adc usbf usbh rtc sim lcdc pcc mmc i 2 c cmt afeif ssl sdhi ref figure 8.1 block diagram of intc section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 245 of 1458 rej09b0033-0300 8.2 input/output pins table 8.1 shows the intc pin configuration. table 8.1 pin configuration name abbreviation i/o description nonmaskable interrupt input pin nmi input input of interrupt request signal, not maskable by the interrupt mask bits in sr interrupt input pins irq5 to irq0 irl3 to irl0 * 1 input input of interrupt request signals port interrupt input pins pint15 to pint0 input input of port interrupt signals bus request signal pin irqout * 2 output bus request signal for an interrupt notes: 1. irl3 to irl0 and irq3 to irq0 cannot be used simultaneously because these pins are multiplexed. 2. when the nmi or h-udi interrupt requests are generated and the response time of cpu is short, this pin may not be asserted. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 246 of 1458 rej09b0033-0300 8.3 register descriptions the intc has the following registers. refer to section 37, list of registers, for more details on the addresses and access size of these registers. ? interrupt control register 0 (icr0) ? interrupt control register 1 (icr1) ? interrupt control register 2 (icr2) ? pint interrupt enable register (pinter) ? interrupt priority register a (ipra) ? interrupt priority register b (iprb) ? interrupt priority register c (iprc) ? interrupt priority register d (iprd) ? interrupt priority register e (ipre) ? interrupt priority register f (iprf) ? interrupt priority register g (iprg) ? interrupt priority register h (iprh) ? interrupt priority register i (ipri) ? interrupt priority register j (iprj) ? interrupt request register 0 (irr0) ? interrupt request register 1 (irr1) ? interrupt request register 2 (irr2) ? interrupt request register 3 (irr3) ? interrupt request register 4 (irr4) ? interrupt request register 5 (irr5) ? interrupt request register 6 (irr6) ? interrupt request register 7 (irr7) ? interrupt request register 8 (irr8) ? interrupt request register 9 (irr9) section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 247 of 1458 rej09b0033-0300 8.3.1 interrupt prio rity registers a to j (ipra to iprj) ipra to iprj are 16-bit r eadable/writable registers in which priority levels from 0 to 15 are set for on-chip peripheral module and irq interrupts. bit bit name initial value r/w description 15 14 13 12 ipr15 ipr14 ipr13 ipr12 0 0 0 0 r/w r/w r/w r/w 11 10 9 8 ipr11 ipr10 ipr9 ipr8 0 0 0 0 r/w r/w r/w r/w 7 6 5 4 ipr7 ipr6 ipr5 ipr4 0 0 0 0 r/w r/w r/w r/w 3 2 1 0 ipr3 ipr2 ipr1 ipr0 0 0 0 0 r/w r/w r/w r/w these bits set the priority level for each interrupt source in 4-bit units. for details, see table 8.2. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 248 of 1458 rej09b0033-0300 table 8.2 interrupt sou rces and ipra to iprj register bits 15 to 12 bits 11 to 8 bits 7 to 4 bits 3 to 0 ipra tmu0 tmu1 tmu2 rtc iprb wdt ref sim reserved * iprc irq3 irq2 irq1 irq0 iprd reserved * tmu (tmu_suni) irq5 irq4 ipre dmac (1) reserved * lcdc ssl iprf adc dmac (2) usbf cmt iprg scif0 scif1 reserved * reserved * iprh pinta pintb tpu i 2 c ipri siof0 siof1 mmc pcc iprj reserved * usbh sdhi afeif note: * reserved. always read as 0. the write va lue should always be 0. the ssl and sdhi- related bits are effective only for the mode ls that include them. reserved bits apply if they are not included. as shown in table 8.2, on-chip peripheral module or irq interrupts are assigned to four 4-bit groups in each register. these 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from h'0 (0000) to h'f (1111). setting h'0 means priority level 0 (masking is requested); h'f means priority level 15 (the highest level). section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 249 of 1458 rej09b0033-0300 8.3.2 interrupt contro l register 0 (icr0) icr0 is a register that sets the input signal detec tion mode of the external interrupt input pin nmi, and indicates the input sign al level at the nmi pin. bit bit name initial value r/w description 15 nmil 0/1 * r nmi input level sets the level of the signal in put at the nmi pin. this bit can be read from to determine the nmi pin level. this bit cannot be modified. 0: nmi input level is low 1: nmi input level is high 14 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 nmie 0 r/w nmi edge select selects whether the falling or rising edge of the interrupt request signal at the nmi pin is detected. 0: interrupt request is detected on falling edge of nmi input 1: interrupt request is detected on rising edge of nmi input 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. note: * the initial value is 1 when nmi input is high, 0 when nmi input is low. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 250 of 1458 rej09b0033-0300 8.3.3 interrupt contro l register 1 (icr1) icr1 is a 16-bit register that specifies the detection mode for external interrupt input pins irq5 to irq0 individually: rising edge, falling edge, high level, or low level. bit bit name initial value r/w description 15 mai 0 r/w all interrupt mask when this bit is set to 1, all interrupt requests are masked while low level is input to the nmi pin. the nmi interrupt is masked in standby mode. 0: when the nmi pin is low, a ll interrupt requests are not masked 1: when the nmi pin is low, all interrupt requests are masked 14 irqlvl 1 r/w interrupt request level detection enables or disables the use of pins irq3 to irq0 as four independent interrupt pins. the irq4 and irq5 are not affected. 0: use of pins irq3 to irq0 as four independent interrupt pins enabled 1: use of pins irl3 to irl0 as encoded 15 level interrupt pins 13 blmsk 0 r/w bl bit mask when the bl bit in the sr register is set to 1, specifies whether the nmi interrupt is masked. 0: when the bl bit is set to 1, the nmi interrupt is masked 1: the nmi interrupt is accepted regardless of the bl bit setting 12 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 251 of 1458 rej09b0033-0300 bit bit name initial value r/w description irqn sense select these bits select whether interrupt request signals corresponding to pins irq5 to irq0 are detected by a rising edge, falling edge, high level, or low level. bit 2n + 1 bit 2n irqn1s irqn0s 0 0 interrupt request is detected on falling edge of irqn input 0 1 interrupt request is detected on rising edge of irqn input 1 0 interrupt request is detected on low level of irqn input 1 1 interrupt request is detected on high level of irqn input 11 10 9 8 7 6 5 4 3 2 1 0 irq51s irq50s irq41s irq40s irq31s irq30s irq21s irq20s irq11s irq10s irq01s irq00s 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w [legend] n= 0 to 5 section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 252 of 1458 rej09b0033-0300 8.3.4 interrupt requ est register 0 (irr0) irr0 is an 8-bit register that indicates interrupt requests from the tmu and irq0 to irq5. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 tmu_ sunir 0 r/w tmu_suni interrupt request indicates whether the tmu_suni (tmu) interrupt request is generated. 0: tmu_suni interrupt request is not generated 1: tmu_suni interrupt request is generated 5 4 3 2 1 0 irq5r irq4r irq3r irq2r irq1r irq0r 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w irqn interrupt request indicates whether there is interrupt request input to the irqn pin. when edge-detecti on mode is set for irqn, an interrupt request is cleared by writing 0 to the irqnr bit after reading irqnr = 1. when level-detection mode is set for irqn, these bits indicate whether an interrupt request is input. the interrupt request is set/cleared by only 1/0 input to the irqn pin. irqnr 0: no interrupt request input to irqn pin 1: interrupt request input to irqn pin [legend] n = 0 to 5 section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 253 of 1458 rej09b0033-0300 8.3.5 interrupt requ est register 1 (irr1) irr1 is an 8-bit register that indicates whether interrupt requests from the dmac are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 dei3r 0 r/w dei3 interrupt request indicates whether the dei3 (dmac) interrupt is generated. 0: dei3 interrupt request is not generated 1: dei3 interrupt request is generated 2 dei2r 0 r/w dei2 interrupt request indicates whether the dei2 (dmac) interrupt request is generated. 0: dei2 interrupt request is not generated 1: dei2 interrupt request is generated 1 dei1r 0 r/w dei1 interrupt request indicates whether the dei1 (dmac) interrupt request is generated. 0: dei1 interrupt request is not generated 1: dei1 interrupt request is generated 0 dei0r 0 r/w dei0 interrupt request indicates whether the dei0 (dmac) interrupt request is generated. 0: dei0 interrupt request is not generated 1: dei0 interrupt request is generated section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 254 of 1458 rej09b0033-0300 8.3.6 interrupt requ est register 2 (irr2) irr2 is an 8-bit register that indicates whethe r interrupt requests from the ssl and lcdc are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. note: on the models not having the ssl, the ssl -related bits are reserved. the write value should always be 0. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 sslir 0 r/w ssli interrupt request indicates whether the ssli (ssl) interrupt request is generated. 0: ssli interrupt request is not generated 1: ssli interrupt request is generated note: on the models not having the ssl, this bit is reserved and always read as 0. the write value should always be 0. 3 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 lcdir 0 r/w lcdci interrupt request indicates whether the lcdci (lcdc) interrupt request is generated. 0: lcdci interrupt request is not generated 1: lcdci interrupt request is generated section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 255 of 1458 rej09b0033-0300 8.3.7 interrupt requ est register 3 (irr3) irr3 is an 8-bit register that indicates whet her interrupt requests from the rtc and sim are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 tendir 0 r/w tendi interrupt request indicates whether the tendi (sim) interrupt is generated. 0: tendi interrupt request is not generated 1: tendi interrupt request is generated 6 txir 0 r/w txi interrupt request indicates whether the txi (sim) interrupt request is generated. 0: txi interrupt request is not generated 1: txi interrupt request is generated 5 rxir 0 r/w rxi interrupt request indicates whether the rxi (sim) interrupt request is generated. 0: rxi interrupt request is not generated 1: rxi interrupt request is generated 4 erir 0 r/w eri interrupt request indicates whether the eri (sim) interrupt request is generated. 0: eri interrupt request is not generated 1: eri interrupt request is generated 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 cuir 0 r/w cui interrupt request indicates whether the cui (rtc) interrupt request is generated. 0: cui interrupt request is not generated 1: cui interrupt request is generated section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 256 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 prir 0 r/w pri interrupt request indicates whether the pri (rtc) interrupt request is generated. 0: pri interrupt request is not generated 1: pri interrupt request is generated 0 atir 0 r/w ati interrupt request indicates whether the ati (rtc) interrupt request is generated. 0: ati interrupt request is not generated 1: ati interrupt request is generated 8.3.8 interrupt requ est register 4 (irr4) irr4 is an 8-bit register that indicates whethe r interrupt requests from the ref, wdt, and tmu are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 ? 0 r reserved this bit always read as 0. the write value should always be 0. 6 tuni2r 0 r/w tuni2 interrupt request indicates whether the tuni2 (tmu) interrupt request is generated. 0: tuni2 interrupt requ est is not generated 1: tuni2 interrupt request is generated 5 tuni1r 0 r/w tuni 1interrupt request indicates whether the tuni1 (tmu) interrupt request is generated. 0: tuni1 interrupt requ est is not generated 1: tuni1 interrupt request is generated section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 257 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 tuni0r 0 r/w tuni0 interrupt request indicates whether the tuni0 (tmu) interrupt request is generated. 0: tuni0 interrupt requ est is not generated 1: tuni0 interrupt request is generated 3 itir 0 r/w iti interrupt request indicates whether the iti (wdt) interrupt request is generated. 0: iti interrupt request is not generated 1: iti interrupt request is generated 2, 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 rcmir 0 r/w rcmi interrupt request indicates whether the rcmi (ref) interrupt request is generated. 0: rcmi interrupt request is not generated 1: rcmi interrupt request is generated 8.3.9 interrupt requ est register 5 (irr5) irr5 is an 8-bit register that indicates whether interrupt requests from the scif0, scif1, dmac, and adc are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 258 of 1458 rej09b0033-0300 bit bit name initial value r/w description 7 adcir 0 r/w adci interrupt request indicates whether the adci (adc) interrupt request is generated. 0: adci interrupt request is not generated 1: adci interrupt request is generated 6 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 5 dei5r 0 r/w dei5 interrupt request indicates whether the dei5 (dmac) interrupt request is generated. 0: dei5 interrupt request is not generated 1: dei5 interrupt request is generated 4 dei4r 0 r/w dei4 interrupt request indicates whether the dei4 (dmac) interrupt request is generated. 0: dei4 interrupt request is not generated 1: dei4 interrupt request is generated 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 scif1ir 0 r/w scif1i interrupt request indicates whether the scif1i (scif1) interrupt request is generated. 0: scif1i interrupt request is not generated 1: scif1i interrupt request is generated 0 scif0ir 0 r/w scif0i interrupt request indicates whether the scif0i (scif0) interrupt request is generated. 0: scif0i interrupt request is not generated 1: scif0i interrupt request is generated section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 259 of 1458 rej09b0033-0300 8.3.10 interrupt requ est register 6 (irr6) irr6 is an 8-bit register that indicates whethe r interrupt requests from the pint, siof0, and siof1 are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7, 6 ? all 0 r reserved this bit is always read as 0. the write value should always be 0. 5 siof1ir 0 r/w siof1i interrupt request indicates whether the siof1i (siof1) interrupt request is generated. 0: siof1i interrupt r equest is not generated 1: siof1i interrupt request is generated 4 siof0ir 0 r/w siof0i interrupt request indicates whether the siof0i (siof0) interrupt request is generated. 0: siof0i interrupt r equest is not generated 1: siof0i interrupt request is generated 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 pintbr 0 r/w pintb interrupt request indicates whether the pintb (pint) interrupt request is generated. 0: pintb interrupt request is not generated 1: pintb interrupt request is generated 0 pintar 0 r/w pinta interrupt request indicates whether the pinta (pint) interrupt request is generated. 0: pinta interrupt request is not generated 1: pinta interrupt request is generated section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 260 of 1458 rej09b0033-0300 8.3.11 interrupt requ est register 7 (irr7) irr7 is an 8-bit register that indicates whet her interrupt requests from the tpu and iic are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 iicir 0 r/w iici interrupt request indicates whether the iici (iic) interrupt request is generated. 0: iici interrupt request is not generated 1: iici interrupt request is generated 3 tpi3r 0 r/w tpi3 interrupt request indicates whether the tpi3 (tpu) interrupt request is generated. 0: tpi3 interrupt request is not generated 1: tpi3 interrupt request is generated 2 tpi2r 0 r/w tpi2 interrupt request indicates whether the tpi2 (tpu) interrupt request is generated. 0: tpi2 interrupt request is not generated 1: tpi2 interrupt request is generated 1 tpi1r 0 r/w tpi1 interrupt request indicates whether the tpi1 (tpu) interrupt request is generated. 0: tpi1 interrupt request is not generated 1: tpi1 interrupt request is generated 0 tpi0r 0 r/w tpi0 interrupt request indicates whether the tpi0 (tpu) interrupt request is generated. 0: tpi0 interrupt request is not generated 1: tpi0 interrupt request is generated section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 261 of 1458 rej09b0033-0300 8.3.12 interrupt requ est register 8 (irr8) irr8 is an 8-bit register that indicates whet her interrupt requests from the sdhi, mmc, and afeif are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. note: note: on the models not having the sdhi, the sdhi-related bits are reserved. the write value should always be 0. bit bit name initial value r/w description 7 mmci3r 0 r/w mmci3 interrupt request indicates whether the mmci3 (mmc) interrupt request is generated. 0: mmci3 interrupt request is not generated 1: mmci3 interrupt request is generated 6 mmci2r 0 r/w mmci2 interrupt request indicates whether the mmci2 (mmc) interrupt request is generated. 0: mmci2 interrupt request is not generated 1: mmci2 interrupt request is generated 5 mmci1r 0 r/w mmci1 interrupt request indicates whether the mmci1 (mmc) interrupt request is generated. 0: mmci1 interrupt request is not generated 1: mmci1 interrupt request is generated 4 mmci0r 0 r/w mmci0 interrupt request indicates whether the mmci0 (mmc) interrupt request is generated. 0: mmci0 interrupt request is not generated 1: mmci0 interrupt request is generated 3 afecir 0 r/w afeci interrupt request indicates whether the afeci (afeif) interrupt request is generated. 0: afeci interrupt request is not generated 1: afeci interrupt request is generated section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 262 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2, 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 sdir 0 r/w sdi interrupt request indicates whether the sdi (sdhi) interrupt request is generated. 0: sdi interrupt request is not generated 1: sdi interrupt request is generated note: on the models not having the sdhi, this bit is reserved and always read as 0. the write value should always be 0. 8.3.13 interrupt requ est register 9 (irr9) irr9 is an 8-bit register that indicates whethe r interrupt requests from the pcc, usbh, usbf, and cmt are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 7 pccir 0 r/w pcci interrupt request indicates whether the pcci (pcc) interrupt request is generated. 0: pcci interrupt request is not generated 1: pcci interrupt request is generated 6 usbhir 0 r usbhi interrupt request indicates whether the usbhi (usbh) interrupt request is generated. 0: usbhi interrupt request is not generated 1: usbhi interrupt request is generated 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 263 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 cmir 0 r/w cmi interrupt request indicates whether the cmi (cmt) interrupt request is generated. 0: cmi interrupt request is not generated 1: cmi interrupt request is generated 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 usbfi1r 0 r usbfi1 interrupt request indicates whether the usbfi1 (usbf) interrupt request is generated. 0: usbfi1interrupt request is not generated 1: usbfi1 interrupt request is generated 1 usbfi0r 0 r usbfi0 interrupt request indicates whether the usbfi0 (usbf) interrupt request is generated. 0: usbfi0 interrupt request is not generated 1: usbfi0 interrupt request is generated 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 264 of 1458 rej09b0033-0300 8.3.14 pint interrupt enable register (pinter) pinter is a 16-bit register which enables interrupt requests input to the external interrupt input pins pint0 to pint15. this register is initialized to h'0000 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pint15e pint14e pint13e pint12e pint11e pint10e pint9e pint8e pint7e pint6e pint5e pint4e pint3e pint2e pint1e pint0e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w pintn interrupt enable select whether the interrupt requests input to the pins pint15 to pint0 is enabled. 0: disable pintn input interrupt requests 1: enable pintn input interrupt requests n = 0 to 15 section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 265 of 1458 rej09b0033-0300 8.3.15 interrupt cont rol register 2 (icr2) incr2 is a 16-bit register which specifies low or high detection mode to the external interrupt input pins pint0 to pint15 individually. this register is initialized to h'0000 by a power-on reset or manual reset, but is not initialized in standby mode. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pint15s pint14s pint13s pint12s pint11s pint10s pint9s pint8s pint7s pint6s pint5s pint4s pint3s pint2s pint1s pint0s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w pintn sense select selects whether to detect an interrupt request signal for the pins pint15 to pint0 by a high- level or low-level. 0: detects interrupt request by pintn input low 1: detects interrupt request by pintn input high n = 0 to 15 section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 266 of 1458 rej09b0033-0300 8.4 interrupt sources there are four types of interrup t sources: nmi, irq, irl, and on- chip peripheral modules. each interrupt has a priority level (0 to 16), with 1 th e lowest and 16 the highest. priority level 0 masks an interrupt, so the interrupt request is ignored. 8.4.1 nmi interrupt the nmi interrupt has the highest priority leve l of 16. when the blmsk bit in the interrupt control register 1 (icr1) is 1 or the bl bit in th e status register (sr) is 0, nmi interrupts are accepted if the mai bit in icr1 is 0. nmi interrupts are edge-det ected. in sleep or standby mode, the interrupt is accepted regardless of the bl setting. the nm i edge select bit (nmie) in the interrupt control register 0 (icr0) is used to select either rising or falling edge detection. when using edge-input detection for nmi interrupts, a pulse width of at least two p cycles (peripheral clock) is necessary. nmi interrupt exception handling does not affect the interrupt mask bits (i3 to i0) in the status register (sr). when the bl bit is 1, only an nmi interrupt is accepted if the blmsk b it in icr1 is 1. it is possible to wake the chip up from sleep mode or standby mode with an nmi interrupt. 8.4.2 irq interrupts irq interrupts are input by level or edge from pins irq0 to irq5. the priority level can be set by interrupt priority registers c and d (iprc and iprd) in a range from 0 to 15. when using edge-sensing for irq interrupts, clear the interrupt source by having software read 1 from the corresponding bit in irr0, then write 0 to the bit. when icr1 is rewritten, irq interrupts may be mistakenly detected, depending on the irq pin states. to prevent this, rewrite th e register while interrupts are ma sked, then release the mask after clearing the illegal interrupt by reading the interr upt request register 0 (irr0) and writing 0 to irr0. edge input interrupt detection requires input of a pulse width of more than two cycles on a p clock basis. when using level-sensing for irq interrupts, the pin levels must be retained until the cpu samples the pins. therefore, the interrupt source must be cleared by the interrupt handler. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 267 of 1458 rej09b0033-0300 the interrupt mask bits (i3 to i0) in the status register (sr) are not affected by irq interrupt handling. irq interrupts specified for edge detection can be used to recover from a standby state when the corresponding interrupt level is higher than that set in the i3 to i0 bits of the sr register. (however, when rtc is used, recovering from standby by using the clock for rtc is enabled.) 8.4.3 irl interrupts irl interrupts are input by pins irl3 to irl0 as level. the priority level is the higher level that is indicated by irl3 to irl0 pins. when the values of irl3 to irl0 pins are 0 (b'0000), it indicates the highest level interrupt request (interrupt priority level 15). when the values of the pins are 15 (b'1111), no interrupt is requested (interrupt priority level 0). figure 8.2 shows an example of connection for irl interrupt. irl interrupts are included with noise canceller function and detected when the sampled levels of each peripheral module clock keep same value for 2 cycles. this prevents sa mpling error level in irl pin changing. irl interrupts priority level should be kept until interrupt is accepte d and its handling is started. however, changing to higher level is enabled. the interrupt mask bits i3 to i0 in the status re gister (sr) are not affected by the irl interrupt handling. priority encoder 4 sh7720 / SH7721 group interrupt request irl3 to irl0 irl3 to irl0 figure 8.2 example of irl interrupt connection section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 268 of 1458 rej09b0033-0300 8.4.4 pint interrupts pint interrupts are input by level from pins pint0 to pint15. the priority level of pint0 to pint7 (pinta) and pint8 to pint15 (pintb) can be set by the interrupt priority level register h (iprh) in a range from 0 to 15. the pint interrupt level should be retained until the interrupt processing starts after an interrupt request has been accepted. the interrupt mask bits i3 to i0 in the status re gister (sr) are not affected by the pin interrupt processing routine. while an rtc clock is supplied, recovery from a standby state on a pint interrupt is possible if the interrupt level is higher than that set in the i3 to i0 bits of the sr register. 8.4.5 on-chip peripheral module interrupts on-chip peripheral module interrupts are generated by the following modules: ? dma controller (dmac) ? i 2 c bus interface (iic) ? smart card interface (sim) ? compare match timer (cmt) ? timer unit (tmu) ? timer pulse unit (tpu) ? watchdog timer (wdt) ? user debugging interface (h-udi) ? lcd controller (lcdc) ? secure sockets layer (ssl) ? analog front end interface (afeif) ? usb function controller (usbf) ? usb host controller (usbh) ? bus state controller (bsc) ? serial i/o with fifo 0 (siof0) ? serial i/o with fifo 1 (siof1) ? serial communication interf ace with fifo 0 (scif0) ? serial communication interf ace with fifo 1 (scif1) ? multimediacard interface (mmc) ? sd host interface (sdhi) section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 269 of 1458 rej09b0033-0300 ? realtime clock (rtc) ? a/d converter (adc) ? pc card controller (pcc) not every interrupt source is assigned a different interrupt vector. sources are reflected in the interrupt event registers (intevt and intevt2). it is easy to identify sources by using the value of intevt or intevt2 as a branch offset. a priority level (from 0 to 15) can be set for each module except h- udi by writing to the interrupt priority registers a, b, and e to j (ipra, iprb, and ipre to iprj). the priority level of the h- udi interrupt is 15 (fixed). the interrupt mask bits (i3 to i0) in the status register are not affected by on-chip peripheral module interrupt handling. 8.4.6 interrupt exceptio n handling and priority there are four types of interrup t sources: nmi, irq, irl, and on-chip peripheral modules. the priority of each interrupt source is set within prio rity levels 0 to 16; level 16 is the highest and level 1 is the lowest. when the priority is set to level 0, that interrupt is masked and the interrupt request is ignored. tables 8.3 and 8.4 list the interrupt sources, the codes for the interrupt event registers (intevt and intevt2), and the interrupt priority. each interrupt source is assign ed a unique code by intevt and intevt2. the start address of the exception handling routine is common for each interrupt source. this is why, for instance, the value of intevt or intevt2 is used as an offset at the start of the exception handling routine and branched to in order to identify the interrupt source. irq interrupt and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each module by setting interrupt priority regi sters a to j (ipra to iprj). a reset assigns priority level 0 to irq and on-chip peripheral module interrupts. if the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in tables 8.3 and 8.4. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 270 of 1458 rej09b0033-0300 table 8.3 interrupt except ion handling sources an d priority (irq mode) interrupt source interrupt code * 1 interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h'1c0 * 2 16 ? ? high h-udi h'5e0 * 2 15 ? ? irq irq0 h'600 * 3 0 to 15 (0) iprc (3 to 0) ? irq1 h'620 * 3 0 to 15 (0) iprc (7 to 4) ? irq2 h'640 * 3 0 to 15 (0) iprc (11 to 8) ? irq3 h'660 * 3 0 to 15 (0) iprc (15 to 12) ? irq4 h'680 * 3 0 to 15 (0) iprd (3 to 0) ? irq5 h'6a0 * 3 0 to 15 (0) iprd (7 to 4) ? tmu tmu_suni h'6c0 * 3 0 to 15 (0) iprd (11 to 8) ? dmac (1) dei0 h'800 * 3 0 to 15 (0) ipre (15 to 12) high dei1 h'820 * 3 0 to 15 (0) dei2 h'840 * 3 0 to 15 (0) dei3 h'860 * 3 0 to 15 (0) low lcdc lcdci h'900 * 3 0 to 15 (0) ipre (7 to 4) ? ssl ssli h'980 * 3 0 to 15 (0) ipre (3 to 0) ? usbf usbfi0 h'a20 * 3 0 to 15 (0) iprf (7 to 4) high usbfi1 h'a40 * 3 low usbh usbhi h'a60 * 3 0 to 15 (0) iprj (11 to 8) ? dmac (2) dei4 h'b80 * 3 0 to 15 (0) iprf (11 to 8) high dei5 h'ba0 * 3 low adc adci h'be0 * 3 0 to 15 (0) iprf (15 to 12) ? scif0 scifi0 h'c00 * 3 0 to 15 (0) iprg (15 to 12) ? scif1 scifi1 h'c20 * 3 0 to 15 (0) iprg (11 to 8) ? pint pinta h'c80 * 3 0 to 15 (0) iprh (15 to 12) ? pintb h'ca0 * 3 0 to 15 (0) iprh (11 to 8) ? siof0 siofi0 h'd00 * 3 0 to 15 (0) ipri (15 to 12) ? siof1 siofi1 h'd20 * 3 0 to 15 (0) ipri (11 to 8) ? low section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 271 of 1458 rej09b0033-0300 interrupt source interrupt code * 1 interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority tpu tpi0 h'd80 * 3 0 to 15 (0) iprh (7 to 4) high high tpi1 h'da0 * 3 tpi2 h'dc0 * 3 tpi3 h'de0 * 3 low iic iici h'e00 * 3 0 to 15 (0) iprh (3 to 0) ? mmc mmci0 h'e80 * 3 0 to 15 (0) ipri (7 to 4) high mmci1 h'ea0 * 3 mmci2 h'ec0 * 3 mmci3 h'ee0 * 3 low cmt cmi h'f00 * 3 0 to 15 (0) iprf (3 to 0) ? pcc pcci h'f60 * 3 0 to 15 (0) ipri (3 to 0) ? sdhi sdi h'f80 * 3 0 to 15 (0) iprj (7 to 4) ? afeif afeci h'fe0 * 3 0 to 15 (0) iprj (3 to 0) ? tmu0 tuni0 h'400 * 2 0 to 15 (0) ipra (15 to 12) ? tmu1 tuni1 h'420 * 2 0 to 15 (0) ipra (11 to 8) ? tmu2 tuni2 h'440 * 2 0 to 15 (0) ipra (7 to 4) ? rtc ati h'480 * 2 0 to 15 (0) ipra (3 to 0) high pri h'4a0 * 2 cui h'4c0 * 2 low sim eri h'4e0 * 2 0 to 15 (0) iprb (7 to 4) high rxi h'500 * 2 txi h'520 * 2 tend h'540 * 2 low wdt iti h'560 * 2 0 to 15 (0) iprb (15 to 12) ? ref rcmi h'580 * 2 0 to 15 (0) iprb (11 to 8) ? low notes: 1. intevt2 code. 2. the code set in intevt is as same as intevt2. 3. the code set in intevt indicates in terrupt level h'200 to h'3c0. for the correspondence of interrupt leve l and intevt, see table 8.5. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 272 of 1458 rej09b0033-0300 table 8.4 interrupt except ion handling sources an d priority (irl mode) interrupt source interrupt code * 1 interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h'1c0 * 2 16 ? ? high h-udi h'5e0 * 2 15 ? ? irl irl3 to rl0 =b'0000 h'200 * 3 15 ? ? irl3 to irl0 =b'0001 h'220 * 3 14 ? ? irl3 to irl0 =b'0010 h'240 * 3 13 ? ? irl3 to irl0 =b'0011 h'260 * 3 12 ? ? irl3 to i rl0 =b'0100 h'280 * 3 11 ? ? irl3 to irl0 =b'0101 h'2a0 * 3 10 ? ? irl3 to irl0 =b'0110 h'2c0 * 3 9 ? ? irl3 to irl0 =b'0111 h'2e0 * 3 8 ? ? irl3 to irl0 =b'1000 h'300 * 3 7 ? ? irl3 to irl0 =b'1001 h'320 * 3 6 ? ? irl3 to irl0 =b'1010 h'340 * 3 5 ? ? irl3 to irl0 =b'1011 h'360 * 3 4 ? ? irl3 to irl0 =b'1100 h'380 * 3 3 ? ? irl3 to irl0 =b'1101 h'3a0 * 3 2 ? ? irl3 to irl0 =b'1110 h'3c0 * 3 1 ? ? irq irq4 h'680 * 3 0 to 15 (0) iprd (3 to 0) ? irq5 h'6a0 * 3 0 to 15 (0) iprd (7 to 4) ? tmu tmu_suni h'6c0 * 3 0 to 15 (0) iprd (11 to 8) ? dei0 h'800 * 3 0 to 15 (0) ipre (15 to 12) high dei1 h'820 * 3 0 to 15 (0) dmac (1) dei2 h'840 * 3 0 to 15 (0) dei3 h'860 * 3 0 to 15 (0) low lcdc lcdci h'900 * 3 0 to 15 (0) ipre (7 to 4) ? ssl ssli h'980 * 3 0 to 15 (0) ipre (3 to 0) ? low section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 273 of 1458 rej09b0033-0300 interrupt source interrupt code * 1 interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority usbf usbfi0 h'a20 * 3 0 to 15 (0) iprf (7 to 4) high high usbfi1 h'a40 * 3 low usbh usbhi h'a60 * 3 0 to 15 (0) iprj (11 to 8) ? dei4 h'b80 * 3 0 to 15 (0) iprf (11 to 8) high dmac (2) dei5 h'ba0 * 3 low adc adci h'be0 * 3 0 to 15 (0) iprf (15 to 12) ? scif0 scifi0 h'c00 * 3 0 to 15 (0) iprg (15 to 12) ? scif1 scufi1 h'c20 * 3 0 to 15 (0) iprg (11 to 8) ? pint pinta h'c80 * 3 0 to 15 (0) iprh (15 to 12) ? pintb h'ca0 * 3 0 to 15 (0) iprh (11 to 8) ? siof0 siofi0 h'd00 * 3 0 to 15 (0) ipri (15 to 12) ? siof1 siofi1 h'd20 * 3 0 to 15 (0) ipri (11 to 8) ? tpu tpi0 h'd80 * 3 0 to 15 (0) iprh (7 to 4) high tpi1 h'da0 * 3 tpi2 h'dc0 * 3 tpi3 h'de0 * 3 low iic iici h'e00 * 3 0 to 15 (0) iprh (3 to 0) ? mmc mmci0 h'e80 * 3 0 to 15 (0) ipri (7 to 4) high mmci1 h'ea0 * 3 mmci2 h'ec0 * 3 mmci3 h'ee0 * 3 low cmt cmi h'f00 * 3 0 to 15 (0) iprf (3 to 0) ? pcc pcci h'f60 * 3 0 to 15 (0) ipri (3 to 0) ? sdhi sdi h'f80 * 3 0 to 15 (0) iprj (7 to 4) ? afeif afeci h'fe0 * 3 0 to 15 (0) iprj (3 to 0) ? low section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 274 of 1458 rej09b0033-0300 interrupt source interrupt code * 1 interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority tmu0 tuni0 h'400 * 2 0 to 15 (0) ipra (15 to 12) ? high tmu1 tuni1 h'420 * 2 0 to 15 (0) ipra (11 to 8) ? tmu2 tuni2 h'440 * 2 0 to 15 (0) ipra (7 to 4) ? rtc ati h'480 * 2 0 to 15 (0) ipra (3 to 0) high pri h'4a0 * 2 cui h'4c0 * 2 low sim eri h'4e0 * 2 0 to 15 (0) iprb (7 to 4) high rxi h'500 * 2 txi h'520 * 2 tend h'540 * 2 low wdt iti h'560 * 2 0 to 15 (0) iprb (15 to 12) ? ref rcmi h'580 * 2 0 to 15 (0) iprb (11 to 8) ? low notes: 1. intevt2 code. 2. the code set in intevt is as same as intevt2. 3. the code set in intevt indicates in terrupt level h'200 to h'3c0. for the correspondence of interrupt leve l and intevt, see table 8.5. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 275 of 1458 rej09b0033-0300 table 8.5 interrupt le vel and intevt code interrupt level intevt code 15 h'200 14 h'220 13 h'240 12 h'260 11 h'280 10 h'2a0 9 h'2c0 8 h'2e0 7 h'300 6 h'320 5 h'340 4 h'360 3 h'380 2 h'3a0 1 h'3c0 section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 276 of 1458 rej09b0033-0300 8.5 operation 8.5.1 interrupt sequence the sequence of interrupt operations is described below. figure 8.3 is a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest-prio rity interrupt from the interrupt requests sent, following the priority levels set in the interrupt priority registers a to j (ipra to iprj). lower priority interrupts are held pending. if two of thes e interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest priority is selected, according to table 8.3, interrupt exception handling sources and priority (irq mode) and table 8.4, interrupt exception handling sources and priority (irl mode). 3. the priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (i3 to i0) in the status register (sr) of the cpu. if the request priority level is higher than the level in bits i3 to i0, the interrupt controller accept s the interrupt and sends an interrupt request signal to the cpu. 4. detection timing: the intc operates, and notifies the cpu of interrupt requests, in synchronization with the peripheral clock (p ). the cpu receives an interrupt at a break in instructions. 5. the interrupt source code is set in the interrupt event registers (intevt and intevt2). 6. the status register (sr) and program counter (pc) are saved to ssr and spc, respectively. 7. the block bit (bl), mode bit (md), and register bank bit (rb) in sr are set to 1. 8. the cpu jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (vbr) and h'00000600). this jump is not a delayed branch. the interrupt handler may branch with the intevt or intevt2 value as its offset in order to identify the interrupt source. this enables it to branch to the handling routine for the individual interrupt source. notes: 1. the interrupt mask bits (i3 to i0) in the status register (sr) are not changed by acceptance of an interr upt in this lsi. 2. the interrupt source flag should be cleared in the interrupt handler. to ensure that an interrupt source that should have been cleared is not inad vertently accepted again, read the interrupt source flag after it has been cl eared, and then clear the bl bit or execute an rte instruction. section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 277 of 1458 rej09b0033-0300 i3 to i0: interrupt mask bits in status register (sr) program execution state interrupt generated? sr.bl=0, sleep mode, or standby mode? yes yes yes yes yes yes yes yes yes no no no no no no no no no nmi? level 15 interrupt? set interrupt source in intevt and intevt2 save sr to ssr; save pc to spc set bl, md, and rb bits in sr to 1 branch to exception handler i3 to i0 levels are 14 or lower? level 14 interrupt? i3 to i0 levels are 13 or lower? level 1 interrupt? i3 to i0 levels are 0? figure 8.3 interrupt operation flowchart section 8 interrupt controller (intc) rev. 3.00 jan. 18, 2008 page 278 of 1458 rej09b0033-0300 8.5.2 multiple interrupts when handling multiple interrupts, an interrupt handler should include the following procedures: 1. to determine the interrupt source, branch to a specific interrupt handler corresponding to a code set in intevt or intevt2. the code in intevt or intevt2 can be used as an offset for branching to the specific handler. 2. clear the interrupt source in each specific handler. 3. save ssr and spc to memory. 4. clear the bl bit in sr, and set the accepted inte rrupt level in the interr upt mask bits in sr. 5. handle the interrupt. 6. execute the rte instruction. when these procedures are followed in order, an interrupt of high er priority than the one being handled can be accepted after clearin g bl in step 4. figure 8.3 sh ows a sample interrupt operation flowchart. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 279 of 1458 rej09b0033-0300 section 9 bus state controller (bsc) the bus state controller (bsc) outputs control si gnals for various types of memory that is connected to the external addre ss space and external devices. the bsc functions enable this lsi to connect directly with sram, sdram, and other memory storage devices, and external devices. 9.1 features the bsc has the following features: (1) external address space ? a maximum 32 or 64 mbytes for each of the eight areas, cs0, cs2 to cs4, cs5a, cs5b, cs6a and cs6b, totally 384 mbytes (divided into eight areas). ? a maximum 64 mbytes for each of the six areas , cs0, cs2 to cs4, cs5, and cs6, totally a total of 384 mbytes (divided into six areas). ? can specify the normal space interface, byte-se lection sram, burst rom (clock synchronous or asynchronous), sdram, pcmc ia for each address space. ? can select the data bus width (8, 16, or 32 bits) for each address space. ? controls the insertion of the wait state for each address space. ? controls the insertion of the wait stat e for each read access and write access. ? can set the independent idling cycle in the c ontinuous access for five cases: read-write (in same space/different space) , read-read (in same space/different space), or the first cycle is a write access. (2) normal space interface ? supports the interface that can di rectly connect to the sram. (3) burst rom (clock asynchronous) interface ? high-speed access to the rom that has the page mode function. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 280 of 1458 rej09b0033-0300 (4) sdram interface ? can set the sdram in up to two areas. ? multiplex output for row address/column address. ? efficient access by single read/single write. ? high-speed access by bank-active mode. ? supports an auto-refresh and self-refresh. ? supports low-power function. (5) byte-selection sram interface ? can connect directly to a byte-selection sram. (6) pcmcia direct interface ? supports ic memory cards and i/o card interfaces defined in the jeida specifications ver. 4.2 (pcmcia2.1 rev 2.1). ? controls the insertion of the wait state using software. ? supports the bus sizing function of the i/o bus width (only in little endian mode). (7) burst rom (clock synchronous) interface ? can connect directly to a burst rom of the clock synchronous type. (8) bus arbitration ? shares all of the resources with other cpu and outputs the bus enable after receiving the bus request from external devices. (9) refresh function ? supports the auto-refresh and self-refresh functions. ? specifies the refresh interval using th e refresh counter an d clock selection. ? can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8). section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 281 of 1458 rej09b0033-0300 (10) interval timer using refresh counter ? generates an interrupt request by a compare match. note: the pcmcia direct interfaces supported by the bsc are only signals and bus protocols shown in table 9.1. for details on other control signals, see section 29, pc card controller (pcc) (external circuits and this lsi on-chip pc card controller). both area 5 and area 6 have the pcmcia direct interface function whic h is common to the sh3. the on-chip pc card controller supports only area 6. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 282 of 1458 rej09b0033-0300 the block diagram of the bsc is shown in figure 9.1. cmncr cs0wcr cs6bwcr rwtcnt cs0bcr cs6bbcr sdcr rtcsr rtcnt rtcor comparator bus mastership controller wait controller area controller internal master module internal slave module internal b us memory controller refresh controller interrupt controller [legend] module bus bsc cs0 , cs2 , cs3 , cs4 , cs5a , cs5b , cs6a , cs6b wait md5 to md3 iois16 a25 to a0, d31 to d0 refout back breq bs , rd/ wr , rd , we3(be3) to we0(be0) , ras , cas , cke, dqmxx, ce2a , ce2b ce1a , ce1b iciord , iciowr cmncr: csnwcr: rwtcnt: csnbcr: sdcr: rtcsr: rtcnt: rtcor: common control register csn space wait control register (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) reset wait counter csn space bus control register (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) sdram control register refresh timer control/status register refresh timer counter refresh time constant register . . . . . . . . . . . . . . . figure 9.1 block diagram of bsc section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 283 of 1458 rej09b0033-0300 9.2 input/output pins the configuration of pins in this module is shown in table 9.1. table 9.1 pin configuration name i/o function a25 to a0 o address bus d31 to d0 i/o data bus bs o bus cycle start asserted when a normal space, burst rom (clock synchronous/asynchronous), or pcmcia is accessed. asserted by the same timing as cas in sdram access. cs0 , cs2 to cs4 o chip select cs5a / ce2a o chip select active only for address map 1 corresponds to pcmcia card select signals d15 to d8 when the pcmcia is used. cs5b / ce1a o chip select corresponds to pcmcia card sele ct signals d7 to d0 when the pcmcia is used. cs6a / ce2b o chip select active only for address map 1 corresponds to pcmcia card select signals d15 to d8 when the pcmcia is used. cs6b / ce1b o chip select corresponds to pcmcia card sele ct signals d7 to d0 when the pcmcia is used. rd/ wr o read/write signal connects to we pins when sdram or byte-selection sram is connected. rd o read strobe (read data output enable signal) a strobe signal to indicate the memory read cycle when the pcmcia is used. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 284 of 1458 rej09b0033-0300 name i/o function we3(be3) /dqmuu/ iciowr o indicates that d31 to d24 are being written to. connected to the byte select signal when a byte-selection sram is connected. corresponds to signals d31 to d24 when sdram is connected. functions as the i/o write strobe signal when the pcmcia is used. we2(be2) /dqmul/ iciord o indicates that d23 to d16 are being written to. connected to the byte select signal when a byte-selection sram is connected. corresponds to signals d23 to d16 when the sdram is used. functions as the i/o read strobe sig nal when the pcmcia is used. we1(be1) /dqmlu/ we o indicates that d15 to d8 are being written to. connected to the byte select signal when a byte-selection sram is connected. corresponds to signals d15 to d8 when the sdram is used. functions as the memory write strobe signal when the pcmcia is used. we0(be0) /dqmll o indicates that d7 to d0 are being written to. connected to the byte select signal when a byte-selection sram is connected. corresponds to select signals d7 to d0 when the sdram is used. ras o connects to ras pin when sdram is connected. cas o connects to cas pin when sdram is connected. cke o connects to cke pin when sdram is connected. iois16 i pcmcia 16-bit i/o signal valid only in little endian mode. pulled low in bit endian mode. wait i external wait input (sampled at the falling edge of ckio) breq i bus request input back o bus acknowledge output md5 to md3 i md5: selects data alignment (big endian or little endian) md4 and md3: specify area 0 bus width (8/16/32 bits) refout o bus mastership request signal for refreshing section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 285 of 1458 rej09b0033-0300 9.3 area overview 9.3.1 area division in the architecture of this lsi, both virtual spaces and physical spaces have 32-bit address spaces. the upper three bits divide into the p0 to p4 areas, and specify the cache access method. for details see section 5, cache. the remaining 29 bits are used for division of the space into ten areas (address map 1) or eight areas (address map 2) according to the map bit in cmncr setting. the bsc performs control for this 29-bit space. as listed in tables 9.2 and 9.3, this lsi can be co nnected directly to eight or six areas of memory, and it outputs chip select signals ( cs0 , cs2 to cs4 , cs5a , cs5b , cs6a , and cs6b ) for each of them. cs0 is asserted during area 0 access; cs5a is asserted during area 5a access when address map 1 is selected; and cs5b is asserted when address map 2 is selected. 9.3.2 shadow area the bsc decodes a28 to a25 of the physical address and generates chip select signals that correspond to areas 0, 2 to 4, 5a, 5b, 6a, and 6b. address bits a31 to a29 are ignored. this means that the range of area 0 addresses, for example, is h'00000000 to h'03ffffff, and its corresponding shadow space is the address space in p1 to p3 areas obtained by adding to it h'20000000 n (n = 1 to 6). the address range for area 7 is h'1c000000 to h'1fffffff. the address space h'1c000000 + h'20000000 n to h'1fffffff + h'20000000 n (n = 0 to 6) corresponding to the area 7 shadow space is reserved , so do not use it. area p4 (h'e0000000 to h'efffffff) is an i/o area and is assigned for internal register addresses. therefore, area p4 does not become shadow space. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 286 of 1458 rej09b0033-0300 area 0 (cs0) h'00000000 h'20000000 h'40000000 h'60000000 h'80000000 h'a0000000 h'c0000000 h'e0000000 area 1 (internal i/o) area 2 (cs2) area 3 (cs3) area 4 (cs4) area 5a (cs5a) area 6a (cs6a) area 7 (reserved area) physical address space address space p0 p1 p2 p3 p4 area 5b (cs5b) area 6b (cs6b) figure 9.2 address space section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 287 of 1458 rej09b0033-0300 9.3.3 address map the external address space has a capacity of 384 mbytes and is used by dividing eight partial spaces (address map 1) or six partial spaces (addre ss map 2). the kind of memory to be connected and the data bus width are specified in each partia l space. the address map fo r the external address space is listed below. table 9.2 address space map 1 (cmncr.map = 0) physical address area memory to be connected capacity h'00000000 to h'03ffffff area 0 normal memory burst rom (asynchronous) burst rom (synchronous) 64 mbytes h'04000000 to h'07ffffff area 1 in ternal i/o register area * 2 64 mbytes h'08000000 to h'0bffffff area 2 normal memory byte-selection sram sdram 64 mbytes h'0c000000 to h'0fffffff area 3 normal memory byte-selection sram sdram 64 mbytes h'10000000 to h'13ffffff area 4 normal memory byte-selection sram burst rom (asynchronous) 64 mbytes h'14000000 to h'15ffffff area 5a normal memory 32 mbytes h'16000000 to h'17ffffff area 5b normal memory byte-selection sram 32 mbytes h'18000000 to h'19ffffff area 6a normal memory 32 mbytes h'1a000000 to h'1bffffff area 6b normal memory byte-selection sram 32 mbytes h'1c000000 to h'1fffffff area 7 reserved area * 1 64 mbytes notes: 1. do not access the reserved area. if t he reserved area is accessed, the correct operation cannot be guaranteed. 2. set the top three bits of the addre ss to 101 to allocate in the p2 space. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 288 of 1458 rej09b0033-0300 table 9.3 address space map 2 (cmncr.map = 1) physical address area memory to be connected capacity h'00000000 to h'03ffffff area 0 normal memory burst rom (asynchronous) burst rom (synchronous) 64 mbytes h'04000000 to h'07ffffff area 1 in ternal i/o register area * 3 64 mbytes h'08000000 to h'0bffffff area 2 normal memory byte-selection sram sdram 64 mbytes h'0c000000 to h'0fffffff area 3 normal memory byte-selection sram sdram 64 mbytes h'10000000 to h'13ffffff area 4 normal memory byte-selection sram burst rom (asynchronous) 64 mbytes h'14000000 to h'17ffffff area 5 * 2 normal memory byte-selection sram pcmcia 64 mbytes h'18000000 to h'1bffffff area 6 * 2 normal memory byte-selection sram pcmcia 64 mbytes h'1c000000 to h'1fffffff area 7 reserved area * 1 64 mbytes notes: 1. do not access the reserved area. if the reserved area is accessed, the correct operation cannot be guaranteed. 2. for area 5, cs5bbcr and cs5bwcr are valid. for area 6, cs6bbcr and cs6bwcr are valid. 3. set the top three bits of the addre ss to 101 to allocate in the p2 space. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 289 of 1458 rej09b0033-0300 9.3.4 area 0 memory type and memory bus width the memory bus width in this lsi can be set for each area. in area 0, external pins can be used to select byte (8 bits), word (16 bits), or longwo rd (32 bits) on power-on reset. the memory bus width of the other area is set by the register. the correspondence between the memory type, external pins (md3, md4), and bus width is listed in the table below. table 9.4 correspondence between external pins (md3 and md4), memory type of cs0, and memory bus width md4 md3 memory type bus width 0 reserved (setting prohibited) 0 1 8 bits * 0 16 bits 1 1 normal memory 32 bits note: * the bus width must not be specified as ei ght bits if the burst rom (clock synchronous) interface is selected. 9.3.5 data alignment this lsi supports the big endian and little endian methods of data alignment. the data alignment is specified using the external pin (md5) at power-on reset as shown in table 9.5. table 9.5 correspondence between external pin (md5) and endians md5 endian 0 big endian 1 little endian section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 290 of 1458 rej09b0033-0300 9.4 register descriptions the bsc has the following registers. refer to section 37, list of registers, for more details on the addresses and access size of these registers. do not access spaces other than cs0 until the term ination of the setting the memory interface. ? common control register (cmncr) ? bus control register for cs0 (cs0bcr) ? bus control register for cs2 (cs2bcr) ? bus control register for cs3 (cs3bcr) ? bus control register for cs4 (cs4bcr) ? bus control register for cs5a (cs5abcr) ? bus control register for cs5b (cs5bbcr) ? bus control register for cs6a (cs6abcr) ? bus control register for cs6b (cs6bbcr) ? wait control register for cs0 (cs0wcr) ? wait control register for cs2 (cs2wcr) ? wait control register for cs3 (cs3wcr) ? wait control register for cs4 (cs4wcr) ? wait control register for cs5a (cs5awcr) ? wait control register for cs5b (cs5bwcr) ? wait control register for cs6a (cs6awcr) ? wait control register for cs6b (cs6bwcr) ? sdram control register (sdcr) ? refresh timer control/st atus register (rtcsr) ? refresh timer counter (rtcnt) ? refresh time constant register (rtcor) ? sdram mode register (sdmr2) ? sdram mode register (sdmr3) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 291 of 1458 rej09b0033-0300 9.4.1 common control register (cmncr) cmncr is a 32-bit register that controls the co mmon items for each area . do not access external memory other than area 0 until the cmncr initialization is complete. bit bit name initial value r/w description 31 to 15 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 14 bsd 0 r/w bus access start timing specification after bus acknowledge specifies the bus access start timing after the external bus acknowledge signal is received. 0: starts the external access at the same timing as the address drive start after the bus acknowledge signal is received. 1: starts the external access one cycle following the address drive start after the bus acknowledge signal is received. 13 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 12 map 0 r/w space specification selects the address map for the external address space. the address maps to be selected are shown in tables 9.2 and 9.3. 0: selects address map 1 1: selects address map 2 11 block 0 r/w bus lock bit specifies whether or not the breq signal is received. 0: receives breq 1: does not receive breq section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 292 of 1458 rej09b0033-0300 bit bit name initial value r/w description 10 9 dprty1 dprty0 0 0 r/w r/w dma burst transfer priority specify the priority for a refres h request/bus mastership request during dma burst transfer. 00: accepts a refresh request and bus mastership request during dma burst transfer 01: accepts a refresh request but does not accept a bus mastership request during dma burst transfer 10: accepts neither a refresh request nor a bus mastership request during dma burst transfer 11: reserved (setting prohibited) 8 7 6 dmaiw2 dmaiw1 dmaiw0 0 0 0 r/w r/w r/w wait states between access cycles when dma single address is transferred specify the number of idle cycles to be inserted after an access to an external device with dack when dma single address transfer is performed. the method of inserting idle cycles depends on the contents of dmaiwa. 000: no idle cycle inserted 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycled inserted 100: 6 idle cycled inserted 101: 8 idle cycle inserted 110: 10 idle cycles inserted 111: 12 idle cycled inserted 5 dmaiwa 0 r/w method of inserting wa it states between access cycles when dma single address is transferred specifies the method of inserting t he idle cycles specified by the dmaiw1 and dmaiw0 bits. clearing this bit will make this lsi insert the idle cycles when another device, which includes this lsi, drives the data bus after an external device with dack drove it. setting this bit will make this lsi insert the idle cycles even when the continuous accesses to an external device with dack are performed. 0: inserts the idle cycles when another device drives the data bus after an external device with dack drove it. 1: inserts the idle cycles every time when an external device with dack is accessed. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 293 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 3 endian 0/1 * r endian flag samples the external pin for specifying endian on power-on reset (md5). all address spaces are defined by this bit. this is a read-only bit. 0: the external pin for specifying endian (md5) was low level on power-on reset. this lsi is being operated as big endian. 1: the external pin for specifying endian (md5) was high level on power-on reset. this lsi is being operated as little endian. 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 hizmem 0 r/w high-z memory control specifies the pin state in standby mode for a25 to a0, bs , csn , rd/ wr , wen ( ben )/dqmxx, and rd . when a bus is released, these pins enter the high-impedance state regardless of the setting of this bit. 0: high impedance in standby mode 1: driven in standby mode 0 hizcnt 0 r/w high-z control specifies the state in stand by mode and bus released for ckio, cke, ras , and cas . 0: high impedance in standby mode and bus released for ckio, cke, ras , and cas . 1: driven in standby mode and bus released for ckio, cke, ras , and cas . note: * the external pin (md5) for specifying endian is sampled on power-on reset. when big endian is specified, this bit is read as 0 and when little endian is specified, this bit is read as 1. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 294 of 1458 rej09b0033-0300 9.4.2 csn space bus cont rol register (csnbcr) this register specifies the type of memory connect ed to each space, data-b us width of each space, and the number of wait cycles between access cycles. do not access external memory other than area 0 until the csnbcr initializat ion is completed. (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 29 28 iww2 iww1 iww0 0 1 1 r/w r/w r/w idle cycles between write-read cycles and write-write cycles these bits specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target access cycles are t he write-read cycle and write- write cycle. 000: no idle cycle 001: 1 idle cycle inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 295 of 1458 rej09b0033-0300 bit bit name initial value r/w description 27 26 25 iwrwd2 iwrwd1 iwrwd0 0 1 1 r/w r/w r/w idle cycles for another space read-write specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target access cycle is a read-write one in which continuous accesses switch between different spaces. 000: no idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 24 23 22 iwrws2 iwrws1 iwrws0 0 1 1 r/w r/w r/w idle cycles for read-write in same space specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target cycle is a read-write cycle of which continuous accesses are for the same space. 000: no idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 296 of 1458 rej09b0033-0300 bit bit name initial value r/w description 21 20 19 iwrrd2 iwrrd1 iwrrd0 0 1 1 r/w r/w r/w idle cycles for read-read in another space specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target cycle is a read-read cycle of which continuous accesses switch between different spaces. 000: no idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted 18 17 16 iwrrs2 iwrrs1 iwrrs0 0 1 1 r/w r/w r/w idle cycles for read-read in same space specify the number of idle cycles to be inserted after the access to a memory that is connected to the space. the target cycle is a read-read cycle of which continuous accesses are for the same space. 000: no idle cycle inserted 001: 1 idle cycles inserted 010: 2 idle cycles inserted 011: 4 idle cycles inserted 100: 6 idle cycles inserted 101: 8 idle cycles inserted 110: 10 idle cycles inserted 111: 12 idle cycles inserted section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 297 of 1458 rej09b0033-0300 bit bit name initial value r/w description 15 14 13 12 type3 type2 type1 type0 0 0 0 0 r/w r/w r/w r/w memory type specify the type of memory connected to a space. 0000: normal space 0001: burst rom (clock asynchronous) 0010: reserved (setting prohibited) 0011: byte-selection sram 0100: sdram 0101: pcmcia 0110: reserved (setting prohibited) 0111: burst rom (clock synchronous) 1000: reserved (setting prohibited) 1001: reserved (setting prohibited) 1010: reserved (setting prohibited) 1011: reserved (setting prohibited) 1100: reserved (setting prohibited) 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) note: memory type for area 0 immediately after reset is normal space. the normal space, burst rom (clock asynchronous), or burst rom (clock synchronous) can be selected by these bits. for details on memory type in each area, see tables 9.2 and 9.3. 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 298 of 1458 rej09b0033-0300 bit bit name initial value r/w description 10 9 bsz1 bsz0 1 * 1 * r/w r/w data bus width specify the data bus width of spaces. 00: reserved (setting prohibited) 01: 8-bit size 10: 16-bit size 11: 32-bit size notes: 1. the data bus width fo r area 0 is specified by the external pin. the bsz1 and bsz0 bit settings in cs0bcr are ignored. 2. if area 5 or area 6 is specified as pcmcia space, the bus width can be specified as either 8 bits or 16 bits. 3. if area 2 or area 3 is specified as sdram space, the bus width can be specifi ed as either 16 bits or 32 bits. 8 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. note: * cs0bcr samples the external pins (md3 an d md4) that specify the bus width at power-on reset. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 299 of 1458 rej09b0033-0300 9.4.3 csn space wait control register (csnwcr) this register specifies various wait cycles for memory accesses. the bit configuration of this register varies as shown below according to the memory type (type3, type2, type1, or type0) specified by the csn space bus cont rol register (csnbcr). specify csnwcr before accessing the target area. specify cs nbcr first, then specify csnwcr. (n = 0, 2, 3, 4, 5a, 5b, 6a, 6b) (1) normal space, byte-selection sram ? cs0wcr, cs6bwcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 bas 0 r/w byte access select ion for byte-selection sram specifies the wen ( ben ) and rd/ wr signal timing when the byte-selection sram interface is used. 0: asserts the wen ( ben ) signal at the read/write timing and asserts the rd/ wr signal during the write access cycle. 1: asserts the wen ( ben ) signal during the read/write access cycle and asserts the rd/ wr signal at the write timing. 19 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 300 of 1458 rej09b0033-0300 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read or write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 301 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles ? cs2wcr, cs3wcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 bas 0 r/w byte access select ion for byte-selection sram specifies the wen ( ben ) and rd/ wr signal timing when the byte-selection sram interface is used. 0: asserts the wen ( ben ) signal at the read/write timing and asserts the rd/ wr signal during the write access cycle. 1: asserts the wen ( ben ) signal during the read/write access cycle and asserts the rd/ wr signal at the write timing. 19 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 302 of 1458 rej09b0033-0300 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read or write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 303 of 1458 rej09b0033-0300 ? cs4wcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 bas 0 r/w byte access select ion for byte-selection sram specifies the wen ( ben ) and rd/ wr signal timing when the byte-selection sram interface is used. 0: asserts the wen ( ben ) signal at the read/write timing and asserts the rd/ wr signal during the write access cycle. 1: asserts the wen ( ben ) signal during the read/write access cycle and asserts the rd/ wr signal at the write timing. 19 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 18 17 16 ww2 ww1 ww0 0 0 0 r/w r/w r/w number of write access wait cycles specify the number of cycles that are necessary for write access. 000: the same cycles as wr3 to wr0 setting (read or write access wait) 001: 0 cycles 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 304 of 1458 rej09b0033-0300 bit bit name initial value r/w description 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion- specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read or write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bi t is valid even when the number of access wait cycles is 0. 0: external wait is valid 1: external wait is ignored section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 305 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles ? cs5awcr bit bit name initial value r/w description 31 to 19 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 18 17 16 ww2 ww1 ww0 0 0 0 r/w r/w r/w number of write access wait cycles specify the number of cycles that are necessary for write access. 000: the same cycles as wr3 to wr0 setting (read or write access wait) 001: 0 cycles 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 306 of 1458 rej09b0033-0300 bit bit name initial value r/w description 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read or write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 307 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles ? cs5bwcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 bas 0 r/w byte access selectio n for byte-selection sram specifies the wen ( ben ) and rd/ wr signal timing when the byte-selection sram interface is used. 0: asserts the wen ( ben ) signal at the read/write timing and asserts the rd/ wr signal during the write access cycle. 1: asserts the wen ( ben ) signal during the read/write access cycle and asserts the rd/ wr signal at the write timing. 19 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 308 of 1458 rej09b0033-0300 bit bit name initial value r/w description 18 17 16 ww2 ww1 ww0 0 0 0 r/w r/w r/w number of write access wait cycles specify the number of cycles that are necessary for write access. 000: the same cycles as wr3 to wr0 setting (read or write access wait) 001: 0 cycles 010: 1 cycle 011: 2 cycles 100: 3 cycles 101: 4 cycles 110: 5 cycles 111: 6 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 309 of 1458 rej09b0033-0300 bit bit name initial value r/w description 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycl es that are necessary for read or write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycles is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd, wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 310 of 1458 rej09b0033-0300 ? cs6awcr bit bit name initial value r/w description 31 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles 10 9 8 7 wr3 wr2 wr1 wr0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cy cles that are necessary for read or write access. 0000: 0 cycle 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 311 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles (2) burst rom (clo ck asynchronous) ? cs0wcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 ben 0 r/w burst enable specification enables or disables 8-burst access for a 16-bit bus width or 16-burst access for an 8-bit bus width during 16-byte access. if this bit is set to 1, 2-burst access is performed four times when the bus width is 16 bits and 4-burst access is performed four times when the bus width is 8 bits. to use a device that does not support 8-burst access or 16- burst access, set this bit to 1. 0: enables 8-burst access for a 16-bit bus width and 16-burst access for an 8-bit bus width. 1: disables 8-burst access for a 16-bit bus width and 16-burst access for an 8-bit bus width. 19, 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 312 of 1458 rej09b0033-0300 bit bit name initial value r/w description 17 16 bw1 bw0 0 0 r/w r/w number of burst wait cycles specify the number of wait cycles to be inserted between the second or later access cycles in burst access. 00: 0 cycles 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 7 w3 w2 w1 w0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycles to be inserted in the first access cycle. 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 313 of 1458 rej09b0033-0300 bit bit name initial value r/w description 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycles is 0. 0: external wait is valid 1: external wait is ignored 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. ? cs4wcr bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 ben 0 r/w burst enable specification enables or disables 8-burst access for a 16-bit bus width or 16- burst access for an 8-bit bus width during 16-byte access. if this bit is set to 1, 2-burst access is performed four times when the bus width is 16 bits and 4-burst access is performed four times when the bus width is 8 bits. to use a device that does not support 8-burst access or 16- burst access, set this bit to 1. 0: enables 8-burst access for a 16-bit bus width and 16-burst access for an 8-bit bus width. 1: disables 8-burst access for a 16-bit bus width and 16-burst access for an 8-bit bus width. 19, 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 314 of 1458 rej09b0033-0300 bit bit name initial value r/w description 17 16 bw1 bw0 0 0 r/w r/w number of burst wait cycles specify the number of wait cy cles to be inserted between the second or later access cycles in burst access. 00: 0 cycles 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 11 sw1 sw0 0 0 r/w r/w number of delay cycles from address, csn assertion to rd , wen ( ben ) assertion specify the number of delay cycles from address and csn assertion to rd and wen ( ben ) assertion. these bits can be specified only in area 4. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 315 of 1458 rej09b0033-0300 bit bit name initial value r/w description 10 9 8 7 w3 w2 w1 w0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycles to be inserted in the first access cycle. 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) 6 wm 0 r/w external wait mask specification specifies whether or not the external wait input is valid. the specification by this bi t is valid even when the number of access wait cycles is 0. 0: external wait is valid 1: external wait is ignored 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 hw1 hw0 0 0 r/w r/w number of delay cycles from rd , wen ( ben ) negation to address, csn negation specify the number of delay cycles from rd and wen ( ben ) negation to address and csn negation. these bits can be specified only in area 4. 00: 0.5 cycle 01: 1.5 cycles 10: 2.5 cycles 11: 3.5 cycles section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 316 of 1458 rej09b0033-0300 (3) sdram ? cs2wcr bit bit name initial value r/w description 31 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 7 a2cl1 a2cl0 1 0 r/w r/w cas latency for area 2 specify the cas latency for area 2. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 6 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. ? cs3wcr bit bit name initial value r/w description 31 to 15 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 14 13 trp1 trp0 0 0 r/w r/w number of cycles from auto-precharge/pre command to actv command specify the number of minimum cycles from the start of auto- precharge or issuing of pre command to the issuing of actv command for the same bank. the setting for areas 2 and 3 is common. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 12 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 317 of 1458 rej09b0033-0300 bit bit name initial value r/w description 11 10 trcd1 trcd0 0 1 r/w r/w number of cycles from actv command to read(a)/writ(a) command specify the number of minimum cycles from issuing actv command to issuing read(a)/writ(a) command. the setting for areas 2 and 3 is common. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles 9 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 8 7 a3cl1 a3cl0 1 0 r/w r/w cas latency for area 3. specify the cas latency for area 3. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles when connecting the sdram to area 2 and area 3, set the cas latency to the bits 8 and 7 in the cs2wcr register and the sdmr2 and sdmr3 registers for sdram mode setting. (see table 9.19.) 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 trwl1 trwl0 0 0 r/w r/w number of cycles from writa/writ command to auto- precharge/pre command specifies the number of cycles from issuing writa/writ command to the start of auto-precharge or to issuing pre command. the setting for areas 2 and 3 is common. 00: 0 cycles 01: 1 cycle 10: 2 cycles 11: 3 cycles section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 318 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 0 trc1 trc0 0 0 r/w r/w number of cycles from ref command/self-refresh release to actv command specify the number of mini mum cycles from issuing the ref command or releasing self-refresh to issuing the actv command. the setting for areas 2 and 3 is common. 00: 3 cycles 01: 4 cycles 10: 6 cycles 11: 9 cycles note: * if both areas 2 and 3 are specified as sdram, trp1/0, trcd0/1, trwl1/0, and trc1/0 bit settings are common. if only one area is connected to the sdram, specify area 3. in this case, specify area 2 as normal space or byte-selection sram. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 319 of 1458 rej09b0033-0300 (4) pcmcia ? cs5bwcr, cs6bwcr bit bit name initial value r/w description 31 to 22 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 21 20 sa1 sa0 0 0 r/w r/w space attribute specification specify memory card interface or i/o card interface when the pcmcia interface is selected. sa1 0: specifies memory card interface when a25 = 1 1: specifies i/o card interface when a25 = 1 sa0 0: specifies memory card interface when a25 = 0 1: specifies i/o card interface when a25 = 0 note: when using the pc card controller, specifies the following settings. when the bit 4 (p0use) in the pcc0gcr register of pcc is 1 and the bit 5 (p0pcct) of the pcc0gcr register is 0, both sa1 and sa0 should be 0. when the bit 4 (p0use) and the bit 5 (p0pcct) in the pcc0gcr register of p cc are 1, both sa1 and sa0 should be 1. 19 to 15 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 320 of 1458 rej09b0033-0300 bit bit name initial value r/w description 14 13 12 11 ted3 ted2 ted1 ted0 0 0 0 0 r/w r/w r/w r/w delay from address to rd or we assert specify the delay time from address output to rd or we assert in pcmcia interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 321 of 1458 rej09b0033-0300 bit bit name initial value r/w description 10 9 8 7 pcw3 pcw2 pcw1 pcw0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycles to be inserted. 0000: 3 cycles 0001: 6 cycles 0010: 9 cycles 0011: 12 cycles 0100: 15 cycles 0101: 18 cycles 0110: 22 cycles 0111: 26 cycles 1000: 30 cycles 1001: 33 cycles 1010: 36 cycles 1011: 38 cycles 1100: 52 cycles 1101: 60 cycles 1110: 64 cycles 1111: 80 cycles 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycle is 0. 0: external wait is valid 1: external wait is ignored 5, 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 322 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 2 1 0 teh3 teh2 teh1 teh0 0 0 0 0 r/w r/w r/w r/w delay from rd or we negate to address specify the address hold time from rd or we negate in the pcmcia interface. 0000: 0.5 cycle 0001: 1.5 cycles 0010: 2.5 cycles 0011: 3.5 cycles 0100: 4.5 cycles 0101: 5.5 cycles 0110: 6.5 cycles 0111: 7.5 cycles 1000: 8.5 cycles 1001: 9.5 cycles 1010: 10.5 cycles 1011: 11.5 cycles 1100: 12.5 cycles 1101: 13.5 cycles 1110: 14.5 cycles 1111: 15.5 cycles section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 323 of 1458 rej09b0033-0300 (5) burst rom (clock synchronous) ? cs0wcr bit bit name initial value r/w description 31 to 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 16 bw1 bw0 0 0 r/w r/w number of burst wait cycles specify the number of wait cy cles to be inserted between the second or later access cycles in burst access. 00: 0 cycles 01: 1 cycle 10: 2 cycles 11: 3 cycles 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 7 w3 w2 w1 w0 1 0 1 0 r/w r/w r/w r/w number of access wait cycles specify the number of wait cycles to be inserted in the first access cycle. 0000: 0 cycles 0001: 1 cycle 0010: 2 cycles 0011: 3 cycles 0100: 4 cycles 0101: 5 cycles 0110: 6 cycles 0111: 8 cycles 1000: 10 cycles 1001: 12 cycles 1010: 14 cycles 1011: 18 cycles 1100: 24 cycles 1101: reserved (setting prohibited) 1110: reserved (setting prohibited) 1111: reserved (setting prohibited) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 324 of 1458 rej09b0033-0300 bit bit name initial value r/w description 6 wm 0 r/w external wait mask specification specify whether or not the exte rnal wait input is valid. the specification by this bit is valid even when the number of access wait cycles is 0. 0: external wait is valid 1: external wait is ignored 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 325 of 1458 rej09b0033-0300 9.4.4 sdram control register (sdcr) sdcr specifies the method to refresh and acce ss sdram, and the types of sdrams to be connected. bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 19 a2row1 a2row0 0 0 r/w r/w number of bits of row address for area 2 specify the number of bits of row address for area 2. 00: 11 bits 01: 12 bits 10: 13 bits 11: reserved (setting prohibited) 18 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 17 16 a2col1 a2col0 0 0 r/w r/w number of bits of column address for area 2 specify the number of bits of column address for area 2. 00: 8 bits 01: 9 bits 10: 10 bits 11: reserved (setting prohibited) 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 deep 0 r/w deep power-down mode this bit is valid for low-power sdram. if the rmode bit is set to 1 while this bit is set to 1, the deep power-down entry command is issued and the low-power sdram enters the deep power-down mode. 0: self-refresh mode 1: deep power-down mode section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 326 of 1458 rej09b0033-0300 bit bit name initial value r/w description 12 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 11 rfsh 0 r/w refresh control specifies whether or not the re fresh operation of the sdram is performed. 0: no refresh 1: refresh 10 rmode 0 r/w refresh control specifies whether to perform auto-refresh or self-refresh when the rfsh bit is 1. when the rfsh bit is 1 and this bit is 1, self-refresh starts immediately. when the rfsh bit is 1 and this bit is 0, auto-refresh starts according to the contents that are set in rtcs r, rtcnt, and rtcor. 0: auto-refresh is performed 1: self-refresh is performed 9 pdown 0 r power-down mode specifies whether the sdram is entered in power-down mode or not after the access to sdram is completed. if this bit is set to 1, the cke pin is pulled to low to place the sdram to power-down mode. 0: does not place the sdram in power-down mode after access completion. 1: places the sdram in power-down mode after access completion. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 327 of 1458 rej09b0033-0300 bit bit name initial value r/w description 8 bactv 0 r/w bank active mode specifies to access whether in auto-precharge mode (using reada and writa commands) or in bank active mode (using read and writ commands). 0: auto-precharge mode (using reada and writa commands) 1: bank active mode (using read and writ commands) note: bank active mode can be used only in area 3. in this case, the bus width can be selected as 16 or 32 bits. when both areas 2 and 3 are set to sdram, specify auto-precharge mode. 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 a3row1 a3row0 0 0 r/w r/w number of bits of row address for area 3 specify the number of bits of the row address for area 3. 00: 11 bits 01: 12 bits 10: 13 bits 11: reserved (setting prohibited) 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 0 a3col1 a3col0 0 0 r/w r/w number of bits of column address for area 3 specify the number of bits of the column address for area 3. 00: 8 bits 01: 9 bits 10: 10 bits 11: reserved (setting prohibited) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 328 of 1458 rej09b0033-0300 9.4.5 refresh timer contro l/status register (rtcsr) rtcsr specifies various items about refresh for sdram. when rtcsr is written, the upper 16 bits of the write data must be h'a55a to cancel write protection. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 cmf 0 r/w compare match flag indicates that a compare matc h occurs between the refresh timer counter (rtcnt) and refres h time constant register (rtcor). this bit is set or cleared in the following conditions. 0: clearing condition: when 0 is written in cmf after reading out rtcsr during cmf = 1. 1: setting condition: when the condition rtcnt = rtcor is satisfied. 6 cmie 0 r/w compare match interrupt enable enables or disables a cmf interrupt request when the cmf bit of rtcsr is set to 1. 0: disables the cmf interrupt request 1: enables the cmf interrupt request 5 4 3 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select select the clock input to coun t-up the refresh timer counter (rtcnt). 000: stop the counting-up 001: b /4 010: b /16 011: b /64 100: b /256 101: b /1024 110: b /2048 111: b /4096 section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 329 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 1 0 rrc2 rrc1 rrc0 0 0 0 r/w r/w r/w refresh count specify the number of contin uous refresh cycles, when the refresh request occurs after the coincidence of the values of the refresh timer counter (rtcnt) and the refresh time constant register (rtcor). t hese bits can make the period of occurrence of refresh long. 000: once 001: twice 010: 4 times 011: 6 times 100: 8 times 101: reserved (setting prohibited) 110: reserved (setting prohibited) 111: reserved (setting prohibited) 9.4.6 refresh time r counter (rtcnt) rtcnt is an 8-bit counter that increments using the clock selected by bi ts cks2 to cks0 in rtcsr. when rtcnt matches rtcor, rtcnt is cl eared to 0. the value in rtcnt returns to 0 after counting up to 255. when the rtcnt is wr itten, the upper 16 bits of the write data must be h'a55a to cancel write protection. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 ? all 0 r/w 8-bit counter section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 330 of 1458 rej09b0033-0300 9.4.7 refresh time constant register (rtcor) rtcor is an 8-bit register. when rtcor matche s rtcnt, the cmf bit in rtcsr is set to 1 and rtcnt is cleared to 0. when the rfsh bit in sdcr is 1, a memory refr esh request is issued by this matching signal. this request is maintained until the refresh opera tion is performed. if the request is not processed when the next matching occurs, the previous request is ignored. if the cmie bit of the rtcsr is set to 1, an inte rrupt is requested by this matching signal. this request is maintained until the cmf bit in rtcsr is cleared to 0. clearing the cmf bit in rtcsr affects only interrupts and does not affect refresh requests. this makes it possible to count the number of refresh requests during refresh by interrupts, and to specify the refresh and interval timer interrupts simultaneously. when the rtcor is written, the upper 16 bits of the write data must be h'a55a to can cel write protection. bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 ? all 0 r/w 8-bit counter 9.4.8 sdram mode registers 2, 3 (sdmr2 and srmr3) for the settings of sdram mode registers (sdmr2 and sdmr3), see table 9.19. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 331 of 1458 rej09b0033-0300 9.5 operation 9.5.1 endian/access size and data alignment this lsi supports big endian, in which the 0 address is the most significant byte (msbyte) in the byte data and little endian, in which the 0 address is the least significant byte (lsbyte) in the byte data. endian is specified on power-on reset by the external pin (md5). when md5 pin is low level on power-on reset, the endian will become big endian and when md5 pin is high level on power-on reset, the endian will become little endian. three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byte- selection sram. two data bus widths (16 bits and 32 bits) are available for sdram. two data bus widths (8 bits and 16 bits ) are available for pcmcia interf ace. data alignment is performed in accordance with the data bus width of the device and en dian. this also means that when longword data is read from a byte-width device, the read operation must be done four times. in this lsi, data alignment and conversion of data length is performed automatically between the respective interfaces. tables 9.6 to 9.11 show the relationship between endian, devi ce data width, and access unit. table 9.6 32-bit external device/bi g endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 data 7 to 0 ? ? ? assert ? ? ? byte access at 1 ? data 7 to 0 ? ? ? assert ? ? byte access at 2 ? ? data 7 to 0 ? ? ? assert ? byte access at 3 ? ? ? data 7 to 0 ? ? ? assert word access at 0 data 15 to 8 data 7 to 0 ? ? assert assert ? ? word access at 2 ? ? data 15 to 8 data 7 to 0 ? ? assert assert longword access at 0 data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0 assert assert assert assert section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 332 of 1458 rej09b0033-0300 table 9.7 16-bit external device/bi g endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? data 7 to 0 ? ? ? assert ? byte access at 1 ? ? ? data 7 to 0 ? ? ? assert byte access at 2 ? ? data 7 to 0 ? ? ? assert ? byte access at 3 ? ? ? data 7 to 0 ? ? ? assert word access at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert word access at 2 ? ? data 15 to 8 data 7 to 0 ? ? assert assert 1st time at 0 ? ? data 31 to 24 data 23 to 16 ? ? assert assert longword access at 0 2nd time at 2 ? ? data 15 to 8 data 7 to 0 ? ? assert assert section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 333 of 1458 rej09b0033-0300 table 9.8 8-bit external device/big endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? ? assert byte access at 1 ? ? ? data 7 to 0 ? ? ? assert byte access at 2 ? ? ? data 7 to 0 ? ? ? assert byte access at 3 ? ? ? data 7 to 0 ? ? ? assert 1st time at 0 ? ? ? data 15 to 8 ? ? ? assert word access at 0 2nd time at 1 ? ? ? data 7 to 0 ? ? ? assert 1st time at 2 ? ? ? data 15 to 8 ? ? ? assert word access at 2 2nd time at 3 ? ? ? data 7 to 0 ? ? ? assert 1st time at 0 ? ? ? data 31 to 24 ? ? ? assert 2nd time at 1 ? ? ? data 23 to 16 ? ? ? assert 3rd time at 2 ? ? ? data 15 to 8 ? ? ? assert longword access at 0 4th time at 3 ? ? ? data 7 to 0 ? ? ? assert section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 334 of 1458 rej09b0033-0300 table 9.9 32-bit external device/littl e endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? assert byte access at 1 ? ? data 7 to 0 ? ? ? assert ? byte access at 2 ? data 7 to 0 ? ? ? assert ? ? byte access at 3 data 7 to 0 ? ? ? assert ? ? ? word access at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert word access at 2 data 15 to 8 data 7 to 0 ? ? assert assert ? ? longword access at 0 data 31 to 24 data 23 to 16 data 15 to 8 data 7 to 0 assert assert assert assert section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 335 of 1458 rej09b0033-0300 table 9.10 16-bit external device/li ttle endian access and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? ? assert byte access at 1 ? ? data 7 to 0 ? ? ? assert ? byte access at 2 ? ? ? data 7 to 0 ? ? ? assert byte access at 3 ? ? data 7 to 0 ? ? ? assert ? word access at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert word access at 2 ? ? data 15 to 8 data 7 to 0 ? ? assert assert 1st time at 0 ? ? data 15 to 8 data 7 to 0 ? ? assert assert longword access at 0 2nd time at 1 ? ? data 31 to 24 data 23 to 16 ? ? assert assert section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 336 of 1458 rej09b0033-0300 table 9.11 8-bit external device/little endian a ccess and data alignment data bus strobe signals operation d31 to d24 d23 to d16 d15 to d8 d7 to d0 we3(be3) , dqmuu we2(be2) , dqmul we1(be1) , dqmlu we0(be0) , dqmll byte access at 0 ? ? ? data 7 to 0 ? ? ? assert byte access at 1 ? ? ? data 7 to 0 ? ? ? assert byte access at 2 ? ? ? data 7 to 0 ? ? ? assert byte access at 3 ? ? ? data 7 to 0 ? ? ? assert 1st time at 0 ? ? ? data 7 to 0 ? ? ? assert word access at 0 2nd time at 1 ? ? ? data 15 to 8 ? ? ? assert 1st time at 2 ? ? ? data 7 to 0 ? ? ? assert word access at 2 2nd time at 3 ? ? ? data 15 to 8 ? ? ? assert 1st time at 0 ? ? ? data 7 to 0 ? ? ? assert 2nd time at 1 ? ? ? data 15 to 8 ? ? ? assert 3rd time at 2 ? ? ? data 23 to 16 ? ? ? assert longword access at 0 4th time at 3 ? ? ? data 31 to 24 ? ? ? assert section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 337 of 1458 rej09b0033-0300 9.5.2 normal space interface (1) basic timing for access to a normal space, this lsi uses strobe signal output in consider ation of the fact that mainly static ram will be directly connected. when using sram with a byte-selection pin, see section 9.5.7, byte-selection sram interface. figure 9.3 shows the basic timings of normal space access. a no-wait normal access is completed in two cycles. the bs signal is asserted for one cycle to indicate the start of a bus cycle. ckio note: * the waveform for dackn is when active low is specified. a rd/ wr rd/ wr d dackn csn t1 t2 rd wen ( ben ) bs d read write * figure 9.3 normal space basi c access timing (access wait 0) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 338 of 1458 rej09b0033-0300 there is no access size specification when reading. the correct access start ad dress is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in case of a 32-bit device, and 16 bits in case of a 16-bit device. when writing, only the wen ( ben ) signal for the byte to be written is asserted. it is necessary to output the data that has been read using rd when a buffer is established in the data bus. the rd/ wr signal is in a read state (high output ) when no access has been carried out. therefore, care must be taken when controlling the external data buffer, to avoid collision. figures 9.4 and 9.5 show the basic timings of normal space accesses. if the wm bit of the csnwcr is cleared to 0, a tnop cycle is inserted to evaluate the external wait (figure 9.4). if the wm bit of the csnwcr is set to 1, external wa its are ignored and no t nop cycle is inserted (figure 9.5). section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 339 of 1458 rej09b0033-0300 ckio a25 to a0 rd rd/ wr d15 to d0 wen ( ben ) d15 to d0 dackn bs wait csn t1 t2 tnop t1 t2 read write * note: * the waveform for dackn is when active low is specified. figure 9.4 continuous access for normal space 1, bus width = 16 bits, longword access, csnwcr.wm bit = 0 (access wa it = 0, cycle wait = 0) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 340 of 1458 rej09b0033-0300 ckio a25 to a0 rd/ wr d15 to d0 dackn csn t1 t2 t1 t2 rd wen ( ben ) bs wait d15 to d0 read write * note: * the waveform for dackn is when active low is specified. figure 9.5 continuous access for normal space 2, bus width = 16 bits, longword access, csnwcr.wm bit = 1 (access wa it = 0, cycle wait = 0) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 341 of 1458 rej09b0033-0300 a16 a0 cs oe i/o7 i/o0 we a18 a2 csn rd d31 d24 we3 ( be3 ) d23 d16 we2 ( be2 ) d15 d8 we1 ( be1 ) d7 d0 we0 ( be0 ) this lsi 128k 8-bit sram a16 a0 cs oe i/o7 i/o0 we a16 a0 cs oe i/o7 i/o0 we a16 a0 cs oe i/o7 i/o0 we figure 9.6 example of 32-bit data-width sram connection section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 342 of 1458 rej09b0033-0300 a16 a0 cs oe i/o7 i/o0 we a17 a1 csn rd d15 d8 we1 ( be1 ) d7 d0 we0 ( be0 ) this lsi 128k 8-bit sram a16 a0 cs oe i/o7 i/o0 we figure 9.7 example of 16-bit data-width sram connection this lsi 128 k x 8 bits sram a16 a0 cs oe i/o7 i/o0 we . . . a16 a0 csn rd d7 d0 we0 ( be0 ) . . . . . . . . . figure 9.8 example of 8-bit data-width sram connection section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 343 of 1458 rej09b0033-0300 9.5.3 access wait control wait cycle insertion on a normal space access can be controlled by the settings of bits wr3 to wr0 in csnwcr. it is possible for areas 4, 5a, an d 5b to insert wait cycles independently in read access and in write access. the areas other th an 4, 5a, and 5b have common access wait for read cycle and write cycle. the specified number of tw cycles is inserted as wait cycles in a normal space access shown in figure 9.9. t1 ckio a25 to a0 csn rd/ wr rd d31 to d0 d31 to d0 wen ( ben ) bs tw read write t2 dackn * note: * the waveform for dackn is when active low is specified. figure 9.9 wait timing for normal space access (software wait only) when the wm bit in csnwcr is clear ed to 0, the external wait input wait signal is also sampled. wait pin sampling is shown in figure 9.10. a 2-cycle wait is specified as a software wait. the wait signal is sampled on the falling edge of ckio at the transition from the t1 or tw cycle to the t2 cycle. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 344 of 1458 rej09b0033-0300 t1 ckio a25 to a0 csn rd/ wr rd d31 to d0 wen ( ben ) d31 to d0 wait tw tw twx t2 read write bs wait states inserted by wait signal dackn * note: * the waveform for dackn is when active low is specified. figure 9.10 wait state timing for normal space access (wait state insertion using wait signal) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 345 of 1458 rej09b0033-0300 9.5.4 csn assert period expansion the number of cycles from csn assertion to rd and wen ( ben ) assertion can be specified by setting bits sw1 and sw0 in csnwcr. the number of cycles from rd and wen ( ben ) negation to csn negation can be specified by setting bits hw1 and hw0. therefore, a flexible interface to an external device can be obtained. figure 9.11 sh ows an example. a th cycle and a tf cycle are added before and after an ordinary cy cle, respectively. in these cycles, rd and wen ( ben ) are not asserted, while other signals are asserted. the data output is prolonged to the tf cycle, and this prolongation is useful for devices with slow writing operations. t1 ckio a25 to a0 csn rd/ wr rd d31 to d0 d31 to d0 wen ( ben ) bs th read write t2 dackn * tf note: * the waveform for dackn is when active low is specified. figure 9.11 csn assert period expansion section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 346 of 1458 rej09b0033-0300 9.5.5 sdram interface (1) sdram direct connection the sdram that can be connected to this lsi is a product that has 11/12/13 bits of row address, 8/9/10 bits of column address, 4 or less banks, and uses the a10 pin for setting precharge mode in read and write command cycles. the control signals for dir ect connection of sdram are ras , cas , rd/ wr , dqmuu, dqmul, dqmlu, dqmll, cke, cs2 , and cs3 . all the signals other than cs2 and cs3 are common to all areas, and signals other than cke are valid when cs2 or cs3 is asserted. sdram can be connected to up to 2 spaces. the data bu s width of the area that is connected to sdram can be set to 32 or 16 bits. burst read/single write (burst length 1) and burst re ad/burst write (burst length 1) are supported as the sdram operating mode. commands for sdram can be specified by ras , cas , rd/ wr , and specific address signals. these commands are shown below. ? nop ? auto-refresh (ref) ? self-refresh (self) ? all banks precharge (pall) ? specified bank precharge (pre) ? bank active (actv) ? read (read) ? read with precharge (reada) ? write (writ) ? write with precharge (writa) ? write mode register (mrs) the byte to be accessed is specified by dq muu, dqmul, dqmlu, and dqmll. reading or writing is performed for a byte whose corresponding dqmxx is low. for details on the relationship between dqmxx and the byte to be accessed, refer to sectio n 9.5.1, endian/access size and data alignment. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 347 of 1458 rej09b0033-0300 figures 9.12 and 9.13 show examples of the connection of the sdram with the lsi. a15 a2 cke ckio csn ras cas rd/ wr d31 d16 dqmuu dqmul d15 d0 dqmlu dqmll 64-mbit sdram (1m x 16 bits x 4 banks) . . . a13 a0 cke clk cs ras cas we i/o15 i/o0 dqmu dqml . . . . . . . . . . . . a13 a0 cke clk cs ras cas we i/o15 i/o0 dqmu dqml . . . . . . this lsi figure 9.12 example of 32-bit data-width sdram connection section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 348 of 1458 rej09b0033-0300 a14 a1 cke ckio csn ras cas rd/ wr d15 d0 dqmlu dqmll 64-mbit sdram (1m x 16 bits x 4 banks) . . . a13 a0 cke clk cs ras cas we i/o15 i/o0 dqmu dqml . . . . . . . . . this lsi figure 9.13 example of 16-bit data-width sdram connection (2) address multiplexing an address multiplexing is sp ecified so that sdram can be connected without external multiplexing circuitry according to the setting of bits bsz[1:0]in csnbcr, axrow[1:0] and axcol[1:0] in sdcr. tables 9.12 to 9.17 show the relationship between the settings of bits bsz[1:0], axrow[1:0], and axcol[1:0] and the bits output at the address pins. do not specify those bits in the manner other than this table, otherwise the operation of this lsi is not guaranteed. a25 to a18 are not multiplexed and the original valu es of address are always output at these pins. when the data bus width is 16 bits (bsz[1:0] =b '10), a0 of sdram speci fies a word address. therefore, connect this a0 pin of sdram to the a1 pin of the lsi; the a1 pin of sdram to the a2 pin of the lsi, and so on. when the data bus width is 32 bits (bsz[1:0] =b'11), the a0 pin of sdram specifies a longword addres s. therefore, connect this a0 pin of sdram to the a2 pin of the lsi; the a1 pin of sdram to the a3 pin of the lsi, and so on. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 349 of 1458 rej09b0033-0300 table 9.12 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (1)-1 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 00 (11 bits) 00 (8 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a25 a17 a16 a24 a16 a15 a23 a15 unused a14 a22 * 2 a22 * 2 a12 (ba1) a13 a21 * 2 a21 * 2 a11 (ba0) specifies bank a12 a20 l/h * 1 a10/ap specifies address/precharge a11 a19 a11 a9 a10 a18 a10 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 a9 a1 a0 a8 a0 unused example of connected memory 64-mbit product (512 kwords x 32 bits x 4 banks, column 8 bits product): 1 16-mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 2 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 350 of 1458 rej09b0033-0300 table 9.12 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (1)-2 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 01 (12 bits) 00 (8 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a24 a17 a16 a23 a16 unused a15 a23 * 2 a23 * 2 a13 (ba1) a14 a22 * 2 a22 * 2 a12 (ba0) specifies bank a13 a21 a13 a11 address a12 a20 l/h * 1 a10/ap specifies address/precharge a11 a19 a11 a9 a10 a18 a10 a8 a9 a17 a9 a7 a8 a16 a8 a6 a7 a15 a7 a5 a6 a14 a6 a4 a5 a13 a5 a3 a4 a12 a4 a2 a3 a11 a3 a1 a2 a10 a2 a0 address a1 a9 a1 a0 a8 a0 unused example of connected memory 128-mbit product (1 mword x 32 bits x 4 banks, column 8 bits product): 1 64-mbit product (1 mword x 16 bits x 4 banks, column 8 bits product): 2 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 351 of 1458 rej09b0033-0300 table 9.13 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (2)-1 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 01 (12 bits) 01 (9 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a26 a17 a16 a25 a16 unused a15 a24 * 2 a24 * 2 a13 (ba1) a14 a23 * 2 a23 * 2 a12 (ba0) specifies bank a13 a22 a13 a11 address a12 a21 l/h * 1 a10/ap specifies address/precharge a11 a20 a11 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 a10 a1 a0 a9 a0 unused example of connected memory 256-mbit product (2 mwords x 32 bits x 4 banks, column 9 bits product): 1 128-mbit product (2 mwords x 16 bits x 4 banks, column 9 bits product): 2 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 352 of 1458 rej09b0033-0300 table 9.13 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (2)-2 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 01 (12 bits) 10 (10 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a27 a17 a16 a26 a16 unused a15 a25 * 2 a25 * 2 a13 (ba1) a14 a24 * 2 a24 * 2 a12 (ba0) specifies bank a13 a23 a13 a11 address a12 a22 l/h * 1 a10/ap specifies address/precharge a11 a21 a11 a9 a10 a20 a10 a8 a9 a19 a9 a7 a8 a18 a8 a6 a7 a17 a7 a5 a6 a16 a6 a4 a5 a15 a5 a3 a4 a14 a4 a2 a3 a13 a3 a1 a2 a12 a2 a0 address a1 a11 a1 a0 a10 a0 unused example of connected memory 512-mbit product (4 mwords x 32 bits x 4 banks, column 10 bits product): 1 256-mbit product (4 mwords x 16 bits x 4 banks, column 10 bits product): 2 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 353 of 1458 rej09b0033-0300 table 9.14 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (3) setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 11 (32 bits) 10 (13 bits) 01 (9 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a26 a17 unused a16 a25 * 2 a25 * 2 a14 (ba1) a15 a24 * 2 a24 * 2 a13 (ba0) specifies bank a14 a23 a14 a12 a13 a22 a13 a11 address a12 a21 l/h * 1 a10/ap specifies address/precharge a11 a20 a11 a9 a10 a19 a10 a8 a9 a18 a9 a7 a8 a17 a8 a6 a7 a16 a7 a5 a6 a15 a6 a4 a5 a14 a5 a3 a4 a13 a4 a2 a3 a12 a3 a1 a2 a11 a2 a0 address a1 a10 a1 a0 a9 a0 unused example of connected memory 512-mbit product (4 mwords x 32 bits x 4 banks, column 9 bits product): 1 256-mbit product (4 mwords x 16 bits x 4 banks, column 9 bits product): 2 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 354 of 1458 rej09b0033-0300 table 9.15 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (4)-1 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 00 (11 bits) 00 (8 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a25 a17 a16 a24 a16 a15 a23 a15 a14 a22 a14 unused a13 a21 * 2 a21 * 2 a12 (ba1) a12 a20 * 2 a20 * 2 a11 (ba0) specifies bank a11 a19 l/h * 1 a10/ap specifies address/precharge a10 a18 a10 a9 address a9 a17 a9 a8 a8 a16 a8 a7 a7 a15 a7 a6 a6 a14 a6 a5 a5 a13 a5 a4 a4 a12 a4 a3 a3 a11 a3 a2 a2 a10 a2 a1 a1 a9 a1 a0 a0 a8 a0 unused example of connected memory 16-mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 355 of 1458 rej09b0033-0300 table 9.15 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (4)-2 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 01 (12 bits) 00 (8 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a25 a17 a16 a24 a16 a15 a23 a15 unused a14 a22 * 2 a22 * 2 a13 (ba1) a13 a21 * 2 a21 * 2 a12 (ba0) specifies bank a12 a20 a12 a11 address a11 a19 l/h * 1 a10/ap specifies address/precharge a10 a18 a10 a9 a9 a17 a9 a8 a8 a16 a8 a7 a7 a15 a7 a6 a6 a14 a6 a5 a5 a13 a5 a4 a4 a12 a4 a3 a3 a11 a3 a2 a2 a10 a2 a1 a1 a9 a1 a0 address a0 a8 a0 unused example of connected memory 64-mbit product (1 mword x 16 bits x 4 banks, column 8 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 356 of 1458 rej09b0033-0300 table 9.16 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (5)-1 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 01 (12 bits) 01 (9 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a26 a17 a16 a25 a16 a15 a24 a15 unused a14 a23 * 2 a23 * 2 a13 (ba1) a13 a22 * 2 a22 * 2 a12 (ba0) specifies bank a12 a21 a12 a11 address a11 a20 l/h * 1 a10/ap specifies address/precharge a10 a19 a10 a9 a9 a18 a9 a8 a8 a17 a8 a7 a7 a16 a7 a6 a6 a15 a6 a5 a5 a14 a5 a4 a4 a13 a4 a3 a3 a12 a3 a2 a2 a11 a2 a1 a1 a10 a1 a0 address a0 a9 a0 unused example of connected memory 128-mbit product (2 mwords x 16 bits x 4 banks, column 9 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 357 of 1458 rej09b0033-0300 table 9.16 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (5)-2 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 01 (12 bits) 10 (10 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a27 a17 a16 a26 a16 a15 a25 a15 unused a14 a24 * 2 a24 * 2 a13 (ba1) a13 a23 * 2 a23 * 2 a12 (ba0) specifies bank a12 a22 a12 a11 address a11 a21 l/h * 1 a10/ap specifies address/precharge a10 a20 a10 a9 a9 a19 a9 a8 a8 a18 a8 a7 a7 a17 a7 a6 a6 a16 a6 a5 a5 a15 a5 a4 a4 a14 a4 a3 a3 a13 a3 a2 a2 a12 a2 a1 a1 a11 a1 a0 address a0 a10 a0 unused example of connected memory 256-mbit product (4 mwords x 16 bits x 4 banks, column 10 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 358 of 1458 rej09b0033-0300 table 9.17 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (6)-1 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 10 (13 bits) 01 (9 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a26 a17 a16 a25 a16 unused a15 a24 * 2 a24 * 2 a14 (ba1) a14 a23 * 2 a23 * 2 a13 (ba0) specifies bank a13 a22 a13 a12 a12 a21 a12 a11 address a11 a20 l/h * 1 a10/ap specifies address/precharge a10 a19 a10 a9 a9 a18 a9 a8 a8 a17 a8 a7 a7 a16 a7 a6 a6 a15 a6 a5 a5 a14 a5 a4 a4 a13 a4 a3 a3 a12 a3 a2 a2 a11 a2 a1 a1 a10 a1 a0 address a0 a9 a0 unused example of connected memory 256-mbit product (4 mwords x 16 bits x 4 banks, column 9 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 359 of 1458 rej09b0033-0300 table 9.17 relationship between a2/3bsz[1:0], a2/3row[1:0], a2/3col[1:0], and address multiplex output (6)-2 setting a2/3 bsz [1:0] a2/3 row [1:0] a2/3 col [1:0] 10 (16 bits) 10 (13 bits) 10 (10 bits) output pin of this lsi row address output column address output synchronous dram pin function a17 a27 a17 a16 a26 a16 unused a15 a25 * 2 a25 * 2 a14 (ba1) a14 a24 * 2 a24 * 2 a13 (ba0) specifies bank a13 a23 a13 a12 a12 a22 a12 a11 address a11 a21 l/h * 1 a10/ap specifies address/precharge a10 a20 a10 a9 a9 a19 a9 a8 a8 a18 a8 a7 a7 a17 a7 a6 a6 a16 a6 a5 a5 a15 a5 a4 a4 a14 a4 a3 a3 a13 a3 a2 a2 a12 a2 a1 a1 a11 a1 a0 address a0 a10 a0 unused example of connected memory 512-mbit product (8 mwords x 16 bits x 4 banks, column 10 bits product): 1 notes: 1. l/h is a bit used in the command specificat ion; it is fixed at low or high according to the access mode. 2. bank address specification section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 360 of 1458 rej09b0033-0300 (3) burst read a burst read occurs in the fo llowing cases with this lsi. 1. access size in reading is larger than data bus width. 2. 16-byte transf er in cache miss. 3. 16-byte transfer in dmac or usdh(access to n on-cacheable area) 4. 16- to 128-byte transfer by lcdc* this lsi always accesses the sdram with burst length 1. for example, read access of burst length 1 is performed consecutively four times to read 16-byte continuous data from the sdram that is connected to a 32-bit data bus. table 9.18 shows the relationship between the access size and the number of bursts. note: * for details, see section 26, lcd controller (lcdc). table 9.18 relationship between access size and number of bursts bus width access size number of bursts 8 bits 1 16 bits 1 32 bits 2 16 bytes 8 16 bits 128 bytes 64 8 bits 1 16 bits 1 32 bits 1 16 bytes 4 32 bits 128 bytes 32 figures 9.14 and 9.15 show a timing chart in burst read. in burst read, an actv command is output in the tr cycle, the read command is issued in the tc1, tc2, and tc3 cycles, the reada command is issued in the tc4 cycle, and the read data is received at the rising edge of the external clock (ckio) in the td1 to td4 cycles. the tap cycle is used to wait fo r the completion of an auto-precharge induced by the read comman d in the sdram. in the tap cycle, a new command will not be issued to the same bank. however, access to another cs space or another bank in the same sdram space is enabled. the nu mber of tap cycles is specified by the trp1 and trp0 bits in cs3wcr. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 361 of 1458 rej09b0033-0300 in this lsi, wait cycles can be inserted by specifying each bit in csnw cr to connect the sdram in variable frequencies. figure 9.15 shows an example in which wait cycles are inserted. the number of cycles from the tr cycle where the actv command is output to the tc1 cycle where the reada command is output can be specified using the trcd1 and t rcd0 bits in cs3wcr. if the trcd1 and trcd0 bits specify two cycles or more, a trw cycle where the not command is issued is inserted between the tr cycle and tc 1 cycle. the number of cycles from the tc1 cycle where the reada command is output to the td1 cycle where the read data is latched can be specified for the cs2 and cs3 spaces independently, using the a2cl1 and a2cl0 bits in cs2wcr or the a3cl1 and a3cl0 bits in cs 3wcr and trcd0 bit in cs3wcr. the number of cycles from tc1 to td1 corresponds to the synchronous dram cas latency. the cas latency for the synchronous dram is normally defined as up to three cycles. however, the cas latency in this lsi can be specified as 1 to 4 cycles. this cas latency can be achieved by connecting a latch circuit between this lsi and the synchronous dram. tc4 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tap dackn * 2 tr tc2 tc3 tc1 td4 tde td2 td3 td1 a12/a11 * 1 cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.14 burst read ba sic timing (auto-precharge) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 362 of 1458 rej09b0033-0300 tc4 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tap dackn * 2 tr tc2 tc3 tc1 td4 tde td2 td3 td1 a12/a11 * 1 cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. trw tw notes: figure 9.15 burst read wait speci fication timing (auto-precharge) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 363 of 1458 rej09b0033-0300 (4) single read a read access ends in one cycle when data exists in non-cacheable region an d the data bus width is larger than or equal to access size. as the burst length is set to 1 in sdram burst read/single write mode, only the required data is output. consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. figure 9.16 shows the single read basic timing. ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tap dackn * 2 tr tc1 tde td1 a12/a11 * 1 cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.16 basic timing fo r single read (auto-precharge) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 364 of 1458 rej09b0033-0300 (5) burst write a burst write occurs in the fo llowing cases in this lsi. 1. access size in writing is larger than data bus width. 2. copyback of the cache 3. 16-byte transfer in dmac (a ccess to non-cacheable region) this lsi always accesses sdram with burst length 1. for example, write access of burst length 1 is performed continuously 4 times to write 16-byte continuous data to the sdram that is connected to a 32-bit data bus. the relationship between the access size and the number of bursts is shown in table 9.18. figure 9.17 shows a timing chart for burst writes. in burst write, an actv command is output in the tr cycle, the writ command is issued in the tc1, tc2, and tc3 cycles, and the writa command is issued to execute an auto-precharge in the tc4 cycle. in the write cycle, the write data is output simultaneously with the write comm and. after the write command with the auto- precharge is output, the trw1 cycle that waits for the auto-precharge initiation is followed by the tap cycle that waits for completion of the auto-p recharge induced by the writa command in the sdram. in the tap cycle, a new command will not be issued to the same bank. however, access to another cs space or an other bank in the same sdram space is enabled. the number of trw1 cycles is specified by the trwl1 and trwl0 b its in cs3wcr. the number of tap cycles is specified by the trp1 and trp0 bits in cs3wcr. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 365 of 1458 rej09b0033-0300 tc4 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tap dackn * 2 tr tc2 tc3 tc1 trwl a12/a11 * 1 cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.17 basic timing fo r burst write (auto-precharge) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 366 of 1458 rej09b0033-0300 (6) single write a write access ends in one cycle when data is wr itten in non-cacheable region and the data bus width is larger than or equal to access size. figure 9.18 shows the single write basic timing. ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tap dackn * 2 tr tc1 trwl a12/a11 * 1 cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.18 basic timing for single write (auto-precharge) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 367 of 1458 rej09b0033-0300 (7) bank active the sdram bank function is used to support high-speed accesses to the same row address. when the bactv bit in sdcr is 1, accesses are perfor med using commands without auto-precharge (read or writ). this function is called bank-active function. this function is valid only for either the upper or lower bits of area 3. when area 3 is set to bank-active mode, area 2 should be set to normal space or byte-selection sram. when areas 2 and 3 are both set to sdram, auto- precharge mode must be set. when a bank-active function is used, prechargin g is not performed when the access ends. when accessing the same row address in the same bank, it is possible to is sue the read or writ command immediately, without issuing an actv command. as sdram is internally divided into several banks, it is possible to activate one row address in each bank. if the next access is to a different row address, a pre command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an actv command followed by a read or writ command. if this is followed by an access to a different row address, the access time will be longer because of the precharging pe rformed after the access request is issued. the number of cycles between issuance of the pr e command and the actv command is determined by the trp[1:0] bits in csnwcr. in a write, when an auto-precharge is performed, a command cannot be issued to the same bank for a period of trwl + tap cycles after issuan ce of the writa command. when bank active mode is used, read or writ commands can be issued successively if the row ad dress is the same. the number of cycles can thus be reduced by trwl + tap cycles for each write. there is a limit on tras, the time for placing each bank in the active state. if there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of tras. a burst read cycle without auto-precharge is shown in figure 9.19, a burst read cycle for the same row address in figure 9.20, and a burst read cy cle for different row addresses in figure 9.21. similarly, a single write cycle without auto-prechar ge is shown in figure 9.22, a single write cycle for the same row address in figure 9.23, and a si ngle write cycle for different row addresses in figure 9.24. in figure 9.20, a tnop cycle in whic h no operation is performed is in serted before the tc cycle that issues the read command. the tnop cycle is inse rted to acquire two cycles of cas latency for the dqmxx signal that specifies the read byte in the data read from the sdram. if the cas latency is specified as two cycles or more, the tnop cycle is not inserted because the two cycles of latency can be acquired even if the dqmxx signal is asserted after the tc cycle. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 368 of 1458 rej09b0033-0300 when bank active mode is set, if only accesse s to the respective banks in the area 3 space are considered, as long as accesses to the same row address co ntinue, the operatio n starts with the cycle in figure 9.19 or 9.22, fo llowed by repetition of the cycle in figure 9.20 or 9.23. an access to a different area during this time ha s no effect. if there is an access to a different row address in the bank active state, after this is de tected the bus cycle in figure 9.21 or 9.24 is executed instead of that in figure 9.20 or 9.23. in bank active mode , too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. tc4 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs dackn * 2 tr tc2 tc3 tc1 td4 td2 td3 td1 tde a12/a11 * 1 cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.19 burst read timing (no auto-precharge) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 369 of 1458 rej09b0033-0300 tc4 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs dackn * 2 tc2 tc3 tc1 tnop td4 tde td2 td3 td1 a12/a11 * 1 cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.20 burst read timing (bank active, same row address) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 370 of 1458 rej09b0033-0300 tc4 ckio a25 to a0 csn rd/ wr d31 to d0 bs tpw dackn * 2 tp tc2 tc3 tc1 td4 td2 td3 td1 a12/a11 * 1 tde tr 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. ras dqmxx cas notes: figure 9.21 burst read timing (b ank active, differen t row addresses) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 371 of 1458 rej09b0033-0300 ckio a25 to a0 csn rd/ wr d31 to d0 bs dackn * 2 tr tc1 a12/a11 * 1 ras dqmxx cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.22 single write timing (no auto-precharge) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 372 of 1458 rej09b0033-0300 ckio a25 to a0 csn rd/ wr d31 to d0 bs dackn * 2 tnop tc1 a12/a11 * 1 ras dqmxx cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.23 single write timing (bank active, same row address) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 373 of 1458 rej09b0033-0300 ckio a25 to a0 csn rd/ wr d31 to d0 bs tpw dackn * 2 tp tc1 a12/a11 * 1 tr ras dqmxx cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.24 single write timing (b ank active, different row addresses) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 374 of 1458 rej09b0033-0300 (8) refreshing this lsi has a function for controlling sdram refreshing. auto-refreshing can be performed by clearing the rmode bit to 0 and setting the rfsh bit to 1 in sdcr. a continuous refreshing can be performed by setting the rrc[2:0] bits in rtcsr. if sdram is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the rmode bit and the rfsh bit to 1. (a) auto-refreshing refreshing is performed at intervals determined by the input clock selected by bits cks[2:0] in rtcsr, and the value set by in rtcor. the value of bits cks[2:0] in rtcor should be set so as to satisfy the refresh interval stipulation for the sdram used. first make the settings for rtcor, rtcnt, and the rmode and rfsh bits in sdcr, then make the cks[2:0] and rrc[2:0] settings. when the clock is selected by bits cks[2:0], rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the two values are the same, a refr esh request is generated and an auto-refresh is performed for the number of times specified by the rrc[2:0]. at th e same time, rtcnt is cleared to 0 and the count-up is restarted. figure 9.25 shows the auto-refresh cycle timing. after starting, the auto refreshing, pall command is issued in the tp cycle to make all the banks to precharged state from active st ate when some bank is being pr echarged. then ref command is issued in the trr cycle after inserting idle cycles of which number is specified by the trp[1:0]bits in csnwcr. a new command is not issued for the duration of the number of cycles specified by the trc[1:0] bits in csnwcr afte r the trr cycle. the trc[1:0] bits must be set so as to satisfy the sdram refreshing cycle time stipulation (trc) . a nop cycle is inse rted between the tp cycle and trr cycle when the setting value of the trp[1:0] bits in csnwcr is longer than or equal to 2 cycles. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 375 of 1458 rej09b0033-0300 ckio a25 to a0 csn rd/ wr d31 to d0 bs tpw dackn * 2 tp trr a12/a11 * 1 trc trc trc hi-z ras dqmxx cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.25 auto-refresh timing (b) self-refreshing self-refresh mode in which the refresh timing and refresh addresses are generated within the sdram. self-refreshing is activated by setting both the rmode bit and the rfsh bit in sdcr to 1. after starting the self-refreshing, pall comm and is issued in tp cycle after the completion of the pre-charging bank. a self command is then issued after inserting idle cycles of which number is specified by the trp[1:0] bits in csnwsr. sdram cannot be accessed while in the self-refresh state. self-refresh mode is cleared by clearing the rmode bit to 0. after self-refresh mode has been cleared, command i ssuance is disabled for the number of cycles specified by the trc[1:0] bits in csnwcr. self-refresh timing is shown in figure 9.26. settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-re freshing is performed at the correct intervals. when self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if the rfsh bit is set to 1 and the rmode bit is cleared to 0 when self-refresh mode is cl eared. if the transition from clearing of self-refresh mo de to the start of auto-refreshing takes time, this time should be section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 376 of 1458 rej09b0033-0300 taken into consideration when setting the initial value of rtcnt. making the rtcnt value 1 less than the rtcor value will enable refreshing to be started immediately. after self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the lsi standby function, and is maintained even after recovery from standby mode by an interrupt. the self-refresh state is not cleared by a manual reset. in case of a power-on reset, the bus state contro ller's registers are initialized, and therefore the self-refresh state is cleared. ckio a25 to a0 csn rd/ wr d31 to d0 bs tpw dackn * 2 tp trr a12/a11 * 1 trc trc trc hi-z trc trc cke ras dqmxx cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.26 self-refresh timing section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 377 of 1458 rej09b0033-0300 (9) relationship between refresh requests and bus cycles if a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle to be completed. if a refresh request occurs wh ile the bus is released by the bus arbitration function, the refresh will not be executed until the bus mastership is acquir ed. this lsi supports requests by the refout pin for the bus mastership while waiting for the refresh request. the refout pin is asserted low until the bus mastership is acquired. if a new refresh request occurs while waiting for th e previous refresh request, the previous refresh request is deleted. to refresh correctly, a bus cy cle longer than the refr esh interval or the bus mastership occupation must be prevented from occurring. if a bus mastership is requested during self-refresh, the bus will not be released until the self- refresh is completed. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 378 of 1458 rej09b0033-0300 (10) power-down mode if the pdown bit in sdcr is set to 1, the sdram is placed in the power-down mode by bringing the cke signal to the low level in the non-access cycle. this power-down mode can effectively lower the power consum ption in the non-access cycle. ho wever, please note that if an access occurs in power-down mode, a cycle of overhead occurs b ecause a cycle that asserts the cke in order to cancel power-down mode is inserted. figure 9.27 shows the access timing in power-down mode. ckio a25 to a0 csn rd/ wr d31 to d0 bs tnop dackn * 2 power-down tr a12/a11 * 1 tc1 td1 tde tap power-down cke ras dqmxx cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. notes: figure 9.27 access timi ng in power-down mode section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 379 of 1458 rej09b0033-0300 (11) power-on sequence in order to use sdram, mode setting must first be performed after powering on. to perform sdram initialization correctly, the bus state controlle r registers must first be set, followed by a write to the sdram mode register. in sdram mode register setting, the ad dress signal value at that time is latched by a combination of the csn , ras , cas , and rd/ wr signals. if the value to be set is x, the bus state controller provides for value x to be written to the sdram mode register by performing a write to address h' a4fd4000 + x for area 2 sdram, and to address h'a4fd5000 + x for area 3 sdram. in this operation the data is ignored, but the mode write is performed as a byte-size access. to set burst read/s ingle write, cas latency 2 to 3, wrap type = sequential, and burst length 1 supported by the ls i, arbitrary data is wr itten in a byte-size access to the addresses shown in table 9.19. in this time 0 is output at the external address pins of a12 or later. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 380 of 1458 rej09b0033-0300 table 9.19 access address in sdram mode register write ? setting for area 2 (sdmr2) burst read/single write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h'a4fd4440 h'0000440 3 h'a4fd4460 h'0000460 32 bits 2 h'a4fd4880 h'0000880 3 h'a4fd48c0 h'00008c0 burst read/burst write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h'a4fd4040 h'0000040 3 h'a4fd4060 h'0000060 32 bits 2 h'a4fd4080 h'0000080 3 h'a4fd40c0 h'00000c0 ? setting for area 3 (sdmr3) burst read/single write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h'a4fd5440 h'0000440 3 h'a4fd5460 h'0000460 32 bits 2 h'a4fd5880 h'0000880 3 h'a4fd58c0 h'00008c0 burst read/burst write (burst length 1): data bus width cas latency access address external address pin 16 bits 2 h'a4fd5040 h'0000040 3 h'a4fd5060 h'0000060 32 bits 2 h'a4fd5080 h'0000080 3 h'a4fd50c0 h'00000c0 section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 381 of 1458 rej09b0033-0300 mode register setting timing is shown in figure 9.28. a pall command (all bank precharge command) is firstly issued. a ref command (auto- refresh command) is then issued 8 times. an mrs command (mode register write command) is finally issued. idle cycles, of which number is specified by the trp[1:0] bits in csnwcr, are inserted between the pall and the first ref. idle cycles, of which number is specified by the t rc[1:0]bits in csnwcr, are inserted between ref and ref, and between the 8th ref and mrs. idle cycles, of which number is one or more, are inserted between the mrs and a command to be issued next. it is necessary to keep idle time of certain cy cles for sdram before issuing pall command after power-on. refer the manual of the sdram for the idle time to be needed. when the pulse width of the reset signal is longer then the idle time, mode register setting can be started immediately after the reset, but care should be taken when the pulse width of the reset signal is shorter than the idle time. ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tpw dackn * 2 tp trr a12/a11 * 1 cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. trc trc tmw hi-z tnop trc trr trc ref ref mrs pall notes: figure 9.28 write timing for sdram mode register (based on jedec) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 382 of 1458 rej09b0033-0300 (12) low-power sdram the low-power sdram can be accessed using the same protocol as the normal sdram. the differences between the low-power sdram and no rmal sdram are that partial refresh takes place that puts only a part of the sdram in the self -refresh state during the self-refresh function, and that power consumption is low during refresh under user conditions such as the operating temperature. the partial refresh is effective in syst ems in which data in a work area other than the specific area can be lost without severe repercussion s. for details, refer to the data sheet for the low-power sdram to be used. the low-power sdram supports the extension mode register (emrs) in addition to the mode registers as the normal sdram. this lsi supports issuing of the emrs command. the emrs command is issued according to the cond itions specified in table 9.20. for example, if data h'0yyyyyyy is written to address h'a4fd5xxx in long-word, the commands are issued to the cs3 space in the follo wing sequence: pall -> ref 8 -> mrs -> emrs. in this case, the mrs and emrs issue addresses are h'0000xxx and h'yyyyyyy, respectively. if data h'1yyyyyyy is written to address h'a4fd5xxx in long-word, the commands are issued to the cs3 space in the following sequence: pall -> mrs -> emrs. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 383 of 1458 rej09b0033-0300 table 9.20 output addresses when emrs command is issued command to be issued access address access data write access size mrs command issue address emrs command issue address cs2 mrs h'a4fd4xxx h' ******** 16 bits h'0000xxx ? cs3 mrs h'a4fd5xxx h' ******** 16 bits h'0000xxx ? cs2mrs +emrs (with refresh) h'a4fd4xxx h'0yyyyyyy 32 bits h'0000xxx h'yyyyyyy cs3 mrs +emrs (with refresh) h'a4fd5xxx h'0yyyyyyy 32 bits h'0000xxx h'yyyyyyy cs2 mrs +emrs (without refresh) h'a4fd4xxx h'1yyyyyyy 32 bits h'0000xxx h'yyyyyyy cs3 mrs +emrs (without refresh) h'a4fd5xxx h'1yyyyyyy 32 bits h'0000xxx h'yyyyyyy section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 384 of 1458 rej09b0033-0300 ckio a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tpw dackn * 4 tp trr a12/a11 * 3 ba1 * 1 ba0 * 2 cas 1. address pin to be connected to the ba1 pin of sdram. 2. address pin to be connected to the ba0 pin of sdram. 3. address pin to be connected to the a10 pin of sdram. 4. the waveform for dackn is when active low is specified. trc trc tmw hi-z tnop trc trr trc ref ref mrs temw tnop emrs pall notes: figure 9.29 emrs command issue timing ? deep power-down mode the low-power sdram supports the deep power-down mode as a low-power consumption mode. in the partial self-refresh function, self-r efresh is performed on a specific area. in the deep power-down mode, self-refresh will not be performed on any memory area. this mode is effective in systems where a ll of the system memory area s are used as work areas. if the rmode bit of the sdcr is set to 1 while the deep and rfsh bits of the sdcr are set to 1, the low-power sdram enters the deep power-down mode. if the rmode bit is cleared to 0, the cke signal is pulled high to cancel the deep power-down mode. before executing an access after returning from the deep power-down mode, the power-up sequence must be re-executed. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 385 of 1458 rej09b0033-0300 ckio cke a25 to a0 csn rd/ wr ras dqmxx d31 to d0 bs tpw dackn * 2 tp tdpd a12/a11 * 1 cas 1. address pin to be connected to the a10 pin of sdram. 2. the waveform for dackn is when active low is specified. trc hi-z trc trc trc trc notes: figure 9.30 transition timing in deep power-down mode 9.5.6 burst rom (clock asynchronous) interface the burst rom (clock async hronous) interface is used to access a memory with a high-speed read function using a method of address switching called the burst mode or page mode. in a burst rom (clock asynchronous) interface, basically the same access as the normal space is performed, but the 2nd and subsequent accesses are performed only by changing the addres s, without negating the rd signal at the end of the 1st cycle. in the 2n d and subsequent accesses, addresses are changed at the falling edge of the ckio. for the 1st access cycle, the numb er of wait cycles specified by the w[3:0] bits in csnwcr is inserted. for the 2nd and subsequent access cycles, the number of wait cycles specified by the bw[1:0] bits in csnwcr is inserted. in the access to the burst ro m (clock asynchronous), the bs signal is asserted only to the first access cycle. an external wait input is valid only to the first access cycle. in the single access or write access that do no t perform the burst operation in the burst rom (clock asynchronous) interface, access timing is same as a normal space. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 386 of 1458 rej09b0033-0300 table 9.21 lists a relatio nship between bus width, access size, and the number of bursts. figure 9.31 shows a timing chart. table 9.21 relationship between bus wi dth, access size, an d number of bursts bus width ben bit access size number of bursts number of accesses not affected 8 bits 1 1 not affected 16 bits 2 1 not affected 32 bits 4 1 0 16 1 8 bits 1 16 bytes 4 4 not affected 8 bits 1 1 not affected 16 bits 1 1 not affected 32 bits 2 1 0 8 1 16 bits 1 16 bytes 2 4 not affected 8 bits 1 1 not affected 16 bits 1 1 not affected 32 bits 1 1 32 bits not affected 16 bytes 4 1 section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 387 of 1458 rej09b0033-0300 ckio address rd data dack wait cs t1 tw tw tb2 twb tb2 twb tb2 twb t2 rd/ wr bs figure 9.31 burst rom (clock asynch ronous) access (bus width = 32 bits, 16-byte transfer (number of bursts = 4), access wait for first time = 2, access wait for 2nd time and after = 1) 9.5.7 byte-selection sram interface the byte-selection sram interface is for access to an sram which ha s a byte-selection pin ( wen ( ben )). this interface has 16-bit data pins and accesses srams having upper and lower byte selection pins, such as ub and lb. when the bas bit in csnwcr is cleared to 0 (initial value), the write access timing of the byte- selection sram interface is the same as that fo r the normal space interface. while in read access of a byte-selection sr am interface, the byte-selection signal is output from the wen ( ben ) pin, which is different from that for the normal sp ace interface. the basic access timing is shown in figure 9.32. in write access, data is written to the memory according to the timing of the byte- selection pin ( wen ( ben )). for details, refer to the data sheet for the corresponding memory. if the bas bit in csnwcr is set to 1, the wen ( ben ) pin and rd/ wr pin timings change. figure 9.33 shows the basic access timing. in write access, da ta is written to the memory according to the timing of the write enable pin (rd/ wr ). the data hold timing from rd/ wr negation to data write must be acquired by setting th e hw[1:0] bits in csnwcr. figu re 9.34 shows the access timing when a software wait is specified. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 388 of 1458 rej09b0033-0300 ckio a25 to a0 csn wen ( ben ) rd/ wr rd rd d31 to d0 d31 to d0 rd/ wr bs dackn * read write note: the waveform for dackn is when active low is specified. t1 t2 high figure 9.32 basic access timing fo r byte-selection sram (bas = 0) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 389 of 1458 rej09b0033-0300 ckio a25 to a0 csn wen ( ben ) rd rd d31 to d0 d31 to d0 rd/ wr rd/ wr bs dackn * read write note: the waveform for dackn is when active low is specified. t1 t2 high figure 9.33 basic access timing fo r byte-selection sram (bas = 1) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 390 of 1458 rej09b0033-0300 t2 ckio a25 to a0 csn rd/ wr wen ( ben ) d31 to d0 bs read write tf dackn * note: the waveform for dackn is when active low is specified. th t1 tw rd rd/ wr d31 to d0 rd high figure 9.34 wait timing for byte-select ion sram (bas = 1) (software wait only) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 391 of 1458 rej09b0033-0300 a15 a0 cs oe we i/o15 i/o0 ub lb . . . . . . . . . a17 a2 csn rd rd/ wr d31 d16 we3 ( be3 ) we2 ( be2 ) d15 d0 we1 ( be1 ) we0 ( be0 ) this lsi 64 k x 16 bits sram . . . a15 a0 cs oe we i/o15 i/o0 ub lb . . . . . . . . . figure 9.35 example of connection with 32-bit data-width byte-selection sram this lsi a16 a1 csn rd rd/ wr d15 d0 we1 ( be1 ) we0 ( be0 ) a15 a0 cs oe we i/o 15 i/o 0 ub lb 64kx16bit sram figure 9.36 example of connection with 16-bit data-width byte-selection sram section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 392 of 1458 rej09b0033-0300 9.5.8 pcmcia interface with this lsi, if address map (2) is select ed using the map bit in cmncr, the pcmcia interface can be specified in areas 5 and 6. areas 5 and 6 in the physical space can be used for the ic memory card and i/o card interface define d in the jeida specifi cations version 4.2 (pcmcia2.1 rev. 2.1) by specifying the type[3:0] bits of csnbcr (n = 5b, 6b) to b'0101. in addition, the sa[1:0] bits of csnwcr (n = 5b, 6b) assign the upper or lower 32 mbytes of each area to an ic memory card or i/o card interface. for example, if the sa1 and sa0 bits of the cs5bwcr are set to 1 and cleared to 0, respec tively, the upper 32 m bytes and the lower 32 mbytes of area 5b are used as an ic memory card interface and i/o card interface, respectively. when the pcmcia interface is used, the bus size must be specified as 8 bits or 16 bits using the bsz[1:0] bits in cs5bbcr or cs6bbcr. figure 9.37 shows an example of a connection be tween this lsi and the pcmcia card. to enable insertion and removal of the pcmcia card during system power-on, a three- state buffer must be connected between the lsi and the pcmcia card. in the jeida and pcmcia standards, operation in the big endian mode is not clearly defined. consequently, an original definition is provided for the pcmcia interface in big endian mode in this lsi. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 393 of 1458 rej09b0033-0300 this lsi pc card (memory i/o) a25 to a0 d7 to d0 ce1 ce2 oe we / pgm iord iowr reg a25 to a0 d7 to d0 d15 to d8 rd/ wr ce1a ce2a rd we iciord iciowr i/o port wait iois16 g g dir g g dir d15 to d8 wait iois16 cd1,cd2 card detection circuit figure 9.37 example of pcmcia interface connection section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 394 of 1458 rej09b0033-0300 (1) basic timing for memory card interface figure 9.38 shows the basic timi ng of the pcmcia ic memory card interface. if areas 5 and 6 in the physical space are specified as the pcmcia interface, accessing the common memory areas in areas 5 and 6 automatically accesses the ic memo ry card interface. if the external bus frequency (ckio) increases, the setup times and hold times for the address pi ns (a25 to a0) to rd and we, card enable signals ( ce1a , ce2a , ce1b , ce2b ), and write data (d15 to d0) become insufficient. to prevent this error, the lsi can specify the setup times and hold times for areas 5 and 6 in the physical space independently, using cs5bwcr and cs6bwcr. in the pcmcia interface, as in the normal space in terface, a software wait or hardwa re wait can be inserted using the wait pin. figure 9.39 shows the pcmcia memory bus wait timing. tpcm1w ckio a25 to a0 cexx rd/ wr rd d15 to d0 we d15 to d0 bs read write tpcm2 tpcm1 tpcm1w tpcm1w figure 9.38 basic access timing fo r pcmcia memory card interface section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 395 of 1458 rej09b0033-0300 tpcm1w ckio a25 to a0 cexx rd/ wr rd d15 to d0 we d15 to d0 bs read write tpcm2 tpcm0 tpcm1 tpcm1w tpcm0w tpcm2w tpcm1w tpcm1w wait figure 9.39 wait timing for pcmcia memory card interface (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait = 1, hardware wait = 1) if all 32 mbytes of the memory space are us ed as an ic memory card interface, the reg signal that switches between the common memory and attribute memory can be generated by an i/o port. if the memory space used for the ic memory card in terface is 16 mbytes or less, the a24 pin can be used as the reg signal by using the memory space as a 16-mbyte common memory space and a 16-mbyte attribute memory space. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 396 of 1458 rej09b0033-0300 pcmcia interface area is 32 mbytes (an i/o port is used as the reg ) area 5 : h'14000000 attribute memory/common memory i/o space attribute memory/common memory i/o space area 5 : h'16000000 area 6 : h'18000000 area 6 : h'1a000000 pcmcia interface area is 16 mbytes (a24 is used as the reg ) area 5 : h'14000000 attribute memory i/o space area 5 : h'15000000 area 5 : h'16000000 h'17000000 area 6 : h'18000000 area 6 : h'19000000 area 6 : h'1a000000 h'1b000000 common memory attribute memory i/o space common memory figure 9.40 example of pcmcia space assignment (cs5bwcr.sa[1:0] = b'10, cs6bwcr.sa[1:0] = b'10) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 397 of 1458 rej09b0033-0300 (2) basic timing for i/o card interface figures 9.41 and 9.42 show the basic timings for the pcmcia i/o card interface. the i/o card and ic memory card interfaces can be switched using an address to be accessed. if area 5 of the physical space is specified as the pcmcia, the i/o card interface can automatically be accessed by accessing the physical addresses from h'16000000 to h'17fffff f. if area 6 of the physical space is specified as the pcmcia, the i/o card interface can automatically be accessed by accessing the physical addresse s from h'1a000000 to h'1bffffff. note that areas to be accessed as the pcmcia i/ o card must be non-cached if they are virtual space (space p2 or p3) areas, or a no n-cached area specified by the mmu. if the pcmcia card is accessed as an i/o card in little endian m ode, dynamic bus sizing for the i/o bus can be achieved using the iois16 signal. if the iois16 signal is brought high in a word- size i/o bus cycle while the bus width of area 6 is specified as 16 bits, the bus width is recognized as 8 bits and data is accessed twice in 8-bit units in the i/o bus cycle to be executed. the iois16 signal is sampled at the falling edge of ckio in the tpci0, tpci0w, and tpci1 cycles when the ted[3:0] bits are specified as 1. 5 cycles or more, and is reflected in the ce2 signal 1.5 cycles after the ckio sampling point. the ted[3:0] bits must be specified appropriately to satisfy the setup time from iciord and iciowr of the pc card to cen . figure 9.43 shows the dynamic bus sizing basic timing. note that the iois16 signal is not supported in big endian mode. in the big endian mode, the iois16 signal must be fixed low. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 398 of 1458 rej09b0033-0300 tpci1w ckio a25 to a0 cexx rd/ wr iciord d15 to d0 iciowr d15 to d0 bs read write tpci2 tpci1 tpci1w tpci1w figure 9.41 basic timing fo r pcmcia i/o card interface section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 399 of 1458 rej09b0033-0300 tpci1w ckio a25 to a0 cexx rd/ wr iciord d15 to d0 iciowr iois16 d15 to d0 bs read write tpci2 tpci0 tpci1 tpci1w tpci0w tpci2w tpci1w tpci1w wait figure 9.42 wait timing fo r pcmcia i/o card interface (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait = 1, hardware wait = 1) tpci1w ckio a25 to a0 ce1x rd/ wr iciord d15 to d0 iciowr iois16 d15 to d0 bs read write tpci2 ce2x tpci0 tpci1 tpci1w tpci0w tpci2w tpci1w tpci1w wait tpci1w tpci2 tpci0 tpci1 tpci1w tpci0w tpci2w tpci1w tpci1w figure 9.43 timing for dynamic bus si zing of pcmcia i/ o card interface (ted[3:0] = b'0010, teh[3:0] = b'0001, software waits = 3) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 400 of 1458 rej09b0033-0300 9.5.9 burst rom (clock synchronous) interface the burst rom (clock synchronou s) interface is supported to access a rom with a synchronous burst function at high speed. the burst rom inte rface accesses the burst rom in the same way as a normal space. this interface is valid only for area 0. in the first access cycle, wait cycl es are inserted. in th is case, the number of wait cycles to be inserted is specified by the w[3:0] bits of the cs0wcr. in the second and subsequent cycles, the number of wait cycles to be inserted is specified by the bw[1:0 ] bits of the cs0wcr. while the burst rom is accesse d (clock synchronous), the bs signal is asserted only for the first access cycle and an external wait input is also valid for the first access cycle. if the bus width is 16 bits, the burst length must be specified as 8. if the bus width is 32 bits, the burst length must be specified as 4. the burst rom interface does not support the 8-bit bus width for the burst rom. the burst rom interface perfor ms burst operations for all read accesses. for example, in a longword acces s over a 16-bit bus, valid 16-bit data is read two times and invalid 16-bit data is read six times. these invalid data read cycles increase the memory access time and degrade the program execution speed and dma transfer sp eed. to prevent this problem, a 16-byte read by cache fill or 16-byte read by the dma should be used. the burst rom interface performs write accesses in the same way as normal space access. twb ckio address note: the waveform for dackn is when active low is specified. csn rd/ wr rd d15 to d0 dackn * bs t1 t2 tw t2b tw t2b twb twb t2b t2b twb twb t2b t2b twb t2b twb wait figure 9.44 burst rom (clock synchronous) access timing (burst length = 8, wait cycles inserted in first access = 2, wait cycles inserted in seco nd and subsequent accesses = 1) section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 401 of 1458 rej09b0033-0300 9.5.10 wait betw een access cycles as the operating frequency of lsis becomes higher, the off-operation of the data buffer often collides with the next data access when the read operation from devices with slow access speed is completed. as a result of these collisions, the reliability of the device is low and malfunctions may occur. this lsi has a function that avoids data collisions by inserting wait cycles between continuous access cycles. the number of wait cycles betw een access cycles can be set by bits iww[2:0], iwrwd[2:0], iwrws[2:0], iwrrd[2:0], and iwrrs[2:0] in csnbcr, and bits dmaiw[2:0] and dmaiwa in cmncr. the co nditions for setting the wait cycles between access cycles (idle cycles) are shown below. 1. continuous accesses are write-read or write-write 2. continuous accesses are re ad-write for different spaces 3. continuous accesses are re ad-write for the same space 4. continuous accesses are re ad-read for different spaces 5. continuous accesses are read-read for the same space 6. data output from an external device caused by dma single transfer is followed by data output from another device that includes this lsi (dmaiwa = 0) 7. data output from an external device caused by dma single transfer is followed by any type of access (dmaiwa = 1) 9.5.11 bus arbitration to prevent device malfunction while the bus master ship is transferred between master and slave, the lsi negates all of the bus control signals before bus release. when the bus mastership is received, all of the bus control signa ls are first negated and then driv en appropriately. in this case, output buffer contention can be prevented because the master and slave drive the same signals with the same values. in addition, to prevent noise while the bus control signal is in the high impedance state, pull-up resistors must be connected to these control signals. bus mastership is transf erred at the boundary of bus cycles. namely, bus mastership is released immediately after receiving a bus request when a bus cycle is not being performed. the release of bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. even when from outside the lsi it looks like a bus cycle is not being performed, a bus cycle may be performing internally, started by inserting wait cycles between acces s cycles. therefore, it cannot be immediately determined whether or not bus mastership has been released by looking at the csn section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 402 of 1458 rej09b0033-0300 signal or other bus control signals. the states th at do not allow bus mast ership release are shown below. 1. 16-byte transfer because of a cache miss 2. during copyback operation for the cache 3. between the read and write cycles of a tas instruction 4. multiple bus cycles generated when the data bus width is smaller than the access size (for example, between bus cycles when longword acces s is made to a memory with a data bus width of 8 bits) 5. 16-byte transfer by the dmac or usbh 6. setting the block bit in cmncr to 1 7. 16 to 128-byte transfer by lcdc 8. transfer by usbh bits dprty[1:0] in cmncr can select whether or not the bus request is received during dmac burst transfer. this lsi has the bus mastership until a bus request is received from another device. upon acknowledging the assertion (low level) of the external bus request signal breq , the lsi releases the bus at the completion of the current bus cycle and asserts the back signal. after the lsi acknowledges the negation (high level) of the breq signal that indicates the slave has released the bus, it negates the back signal and resumes the bus usage. the sdram issues an all bank precharge command (pall) when active banks exist and releases the bus after completion of a pall command. the bus sequence is as follows. th e address bus and data bus are pl aced in a high-impedance state synchronized with the rising edge of ckio. th e bus mastership enable signal is asserted 0.5 cycles after the above timing, sync hronized with the falling edge of ckio. the bus control signals ( bs , csn , ras , cas , dqmxx, wen ( ben ), rd , and rd/ wr ) are placed in the high-impedance state at subsequent rising edges of ckio. bus re quest signals are sampled at the falling edge of ckio. the sequence for reclaiming the bu s mastership from a slave is described below. 1.5 cycles after the negation of breq is detected at the falling edge of ck io, the bus control signals are driven high. the back is negated at the next falling edge of the clock. the fastest timing at which actual bus cycles can be resumed after bus control signal assertion is at the rising edge of the ckio where address and data signals are driven. figure 9.45 shows the bus arbitration timing. in an original slave device de signed by the user, multiple bus accesses are generated continuously to reduce the overhead caused by bus arbitration. in this case, to execute sdram refresh section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 403 of 1458 rej09b0033-0300 correctly, the slave device must be designed to release the bus mastership within the refresh interval time. to achieve this, the lsi instructs the refout pin to request the bus mastership while the sdram waits for the refresh. the lsi asserts the refout pin until the bus mastership is received. if the slave releases the bus, the lsi acquires the bus mast ership to execute the sdram refresh. the bus release by the breq and back signal handshaking requires some overhead. if the slave has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. reducing the cycles required for master to slave bus mastership transitions streamlines the system design. ckio a25 to a0 csn other bus control signals d31 to d0 breq back figure 9.45 bus arbitration timing section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 404 of 1458 rej09b0033-0300 9.6 usage notes (1) reset the bus state controller (bsc) can be initialized co mpletely only at power-on reset. at power-on reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. all control registers are initialized. in standby, sleep, and manual reset, control registers of the bus state controller are not initialized. at manual reset, the current bus cycle being executed is completed and then the access wait state is entered. if a 16-byte transfer is performed by a cache or if another lsi on-chip bus master module is executed when a manual reset occurs, the current access is cancelled in longword un its because the access request is ca ncelled by the bus master at manual reset. if a manual reset is requested duri ng cache fill operations, the contents of the cache cannot be guaranteed. since the rtcnt continues counting up during manual reset signal assertion, a refresh request occurs to initiate the re fresh cycle. in addition, a bus arbitration request by the breq signal can be accepted during manual reset signal assertion. some flash memories ma y specify a minimum time from rese t release to the first access. to ensure this minimum time, the bus state controller supports a 5-bit counter (rwtcnt). at power- on reset, the rwtcnt is cleared to 0. after power-on reset, rwtcnt is counted up synchronously together w ith ckio and an external access will not be generated until rwtcnt is counted up to h 001f. at manual reset, rwtcnt is not cleared. (2) access from the site of the lsi internal bus master there are three types of lsi inte rnal buses: a cache bus, internal bus, and peripheral bus. the cpu and cache memory are connected to the cache bus. internal bus masters other than the cpu and bus state controller are connected to the internal bus. low-speed peripheral modules are connected to the peripheral bus. internal memories other than the cache memory and debugging modules such as a ubc and aud are connected bidirecti onally to the cache bus and internal bus. access from the cache bus to the internal bus is enable d but access from the intern al bus to the cache bus is disabled. this gives rise to the following problems. internal bus masters such as dmac other than the cpu can access on-chip memory other than the cache memory but cannot access the cache memory. if an on-chip bus mast er other than the cpu writes data to an external memory other than th e cache, the contents of the external memory may differ from that of the cache me mory. to prevent this problem, if the external memory whose contents is cached is written by an on-chip bus master other than the cpu, the corresponding cache memory should be purged by software. if the cpu initiates read access for the cache, the cac he is searched. if th e cache stores data, the cpu latches the data and completes the read access. if the cache does not store data, the cpu section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 405 of 1458 rej09b0033-0300 performs four contiguous longword read cycles to perform cach e fill operations via the internal bus. if a cache miss occurs in byte or word operan d access or at a branch to an odd word boundary (4n + 2), the cpu performs four contiguous lo ngword accesses to perform a cache fill operation on the external interface. for a cache-through area, the cpu performs access according to the actual access addresses. for an instruction fetch to an even word boundary (4n), the cpu performs longword access. for an instruc tion fetch to an odd word bound ary (4n + 2), the cpu performs word access. for a read cycle of a cache-through area or an on-c hip peripheral module, the read cycle is first accepted and then read cycle is initiated. the read data is sent to the cpu via the cache bus. in a write cycle for the cache area, the write cy cle operation differs accord ing to the cache write methods. in write-back mode, the cache is first searched. if data is detected at the address corresponding to the cache, the data is then re-wr itten to the cache. in the actual me mory, data will not be re-written until data in the corresponding address is re-wr itten. if data is not detected at the address corresponding to the cache, the cache is modified. in this case, data to be modified is first saved to the internal buffer, 16-byte data including the data corresponding to the address is then read, and data in the corresponding access of the cache is finally modified. following these operations, a write-back cycle for the saved 16-byte data is executed. in write-through mode, the cache is first searched . if data is detected at the address corresponding to the cache, the data is re-writt en to the cache simultaneously with the actual write via the internal bus. if data is not detected at the address corres ponding to the cache, the cache is not modified but an actual write is performed via the internal bus. since the bus state controller (bsc ) incorporates a one-stage write buffer, the bsc can execute an access via the internal bus before the previous exte rnal bus cycle is comple ted in a write cycle. if the on-chip module is read or written after the exte rnal low-speed memory is written, the on-chip module can be accessed before the completion of th e external low-speed me mory write cycle. in read cycles, the cpu is placed in the wait st ate until read operation has been completed. to continue the process after the data write to the device has been completed, perform a dummy read to the same address to check for completion of the write before the next process to be executed. the write buffer of the bsc functions in the same way for an access by a bu s master other than the cpu such as the dmac. accordingly, to perform dual address dma transfers, the next read cycle is initiated before the previous write cycle is completed. note, however, that if both the dma source and destination addresses exist in external memory space, the next wr ite cycle will not be initiated until the previous write cycle is completed. section 9 bus state controller (bsc) rev. 3.00 jan. 18, 2008 page 406 of 1458 rej09b0033-0300 (3) on-chip peripheral module access to access an on-chip module register, two or more periphe ral module clock (p ) cycles are required. care must be taken in system design. (4) external bus priority order access via an external bus is perfor med in the priority order below: breq > refresh > lcdc > usbh > dmac > cpu note that next transfer is not performed until cu rrent transfer (e.g. burst transfer) has completed. section 10 direct memory access controller (dmac) dmas301a_010020030200 rev. 3.00 jan. 18, 2008 page 407 of 1458 rej09b0033-0300 section 10 direct memory access controller (dmac) this lsi includes the direct memory access controller (dmac). the dmac can be used in place of the cpu to perform high-speed transfers between external devices that have dack (transfer request acknowledge signal), external memory, on-chip memory, memory-mapped external devi ces, and on-chip peripheral modules. 10.1 features ? six channels (two channels can receive an external request) ? 4-gbyte physical address space ? data transfer unit is selectable: byte, word (2 bytes), longword (4 bytes), and 16 bytes (longword 4) ? maximum transfer count: 16,777,216 transfers ? address mode: dual address mode or si ngle address mode can be selected. ? transfer requests: external request, on-chip peripheral module re quest, or auto request can be selected. the following modules can issue an on-chip peripheral module request. ? scif0, siof1, mmc, cmt (channels 0 to 4), sim, usbf, siof0, siof1, adc, and sdhi ? selectable bus modes: cycle steal mode (normal mode and intermittent mode) or burst mode can be selected. ? selectable channel priority levels: the channel priority levels are selectable between fixed mode and round-robin mode. ? interrupt request: an interrupt request can be generated to the cpu after transfers end by the specified counts. ? external request detection: there are following four types of dreq input detection. ? low level detection ? high level detection ? rising edge detection ? falling edge detection ? transfer request acknowledge signal: active levels for dack and tend can be set independently. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 408 of 1458 rej09b0033-0300 figure 10.1 shows the block diagram of the dmac. sarn dmac module iteration control register control start-up control request priority control bus interface darn dmatcrn chcrn dmaor dmars0 to dmars2 dein peripheral bus internal bus dack0 , dack1 tend0, tend1 dreq0 , dreq1 external rom external ram external i/o (memory mapped) external i/o (with acknowledge- ment) bus state controller on-chip memory on-chip peripheral module sarn: darn: dmatcrn: chcrn: dmaor: dmars0 to dmars2: dein: n: dma source address register dma destination address register dma transfer count register dma channel control register dma operation register dma extended resource selector 0 to 2 dma transfer-end interrupt request to the cpu 0, 1, 2, 3, 4, 5 [legend] dma transfer request signal dma transfer acknowledge signal interrupt controller figure 10.1 block diagram of dmac section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 409 of 1458 rej09b0033-0300 10.2 input/output pins the external pins for the dmac are described below. table 10.1 lists the configuration of the pins that are connected to external bus. the dmac has pins for 2 channels (channels 0 and 1) for external bus use. table 10.1 pin configuration channel name pin name i/o function dma transfer request dreq0 input dma transfer request input from external device to channel 0 dma transfer request reception dack0 output dma transfer request acknowledge output from channel 0 to external device 0 dma transfer end tend0 output dma transfer end of dmac channel 0 output of dma transfer request dreq1 input dma transfer request input from external device to channel 1 dma transfer request reception dack1 output dma transfer request acknowledge output from channel 1 to external device 1 dma transfer end tend1 output dma transfer end of dmac channel 1 output section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 410 of 1458 rej09b0033-0300 10.3 register descriptions the dmac has the following registers. refer to sect ion 37, list of registers, for more details on the addresses and states of these registers in each operating mode. the sar for channel 0 is expressed such as sar_0. (1) channel 0 ? dma source address register_0 (sar_0) ? dma destination address register_0 (dar_0) ? dma transfer count re gister_0 (dmatcr_0) ? dma channel control register_0 (chcr_0) (2) channel 1 ? dma source address register_1 (sar_1) ? dma destination address register_1 (dar_1) ? dma transfer count regi ster_1 (dmatcr_1) ? dma channel control register _1 (chcr_1) (3) channel 2 ? dma source address register_2 (sar_2) ? dma destination address register_2 (dar_2) ? dma transfer count regi ster_2 (dmatcr_2) ? dma channel control register_2 (chcr_2) (4) channel 3 ? dma source address register_3 (sar_3) ? dma destination address register_3 (dar_3) ? dma transfer count regi ster_3 (dmatcr_3) ? dma channel control register_3 (chcr_3) (5) channel 4 ? dma source address register_4 (sar_4) ? dma destination address register_4 (dar_4) ? dma transfer count re gister_4 (dmatcr_4) ? dma channel control register_4 (chcr_4) section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 411 of 1458 rej09b0033-0300 (6) channel 5 ? dma source address register_5 (sar_5) ? dma destination address register_5 (dar_5) ? dma transfer count re gister_5 (dmatcr_5) ? dma channel control register_5 (chcr_5) (7) common ? dma operation register (dmaor) ? dma extended resource selector 0 (dmars0) ? dma extended resource selector 1 (dmars1) ? dma extended resource selector 2 (dmars2) 10.3.1 dma source address re gisters (sar_0 to sar_5) sar are 32-bit readable/writable registers that specify the source addr ess of a dma transfer. during a dma transfer, these registers indicate the next source address. when the data is transferred from an external de vice with the dack in single address mode, the sar is ignored. to transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. when transferring data in 16-byte units, a 16-byte boundary must be set for the source address value. the initial value is undefined. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 412 of 1458 rej09b0033-0300 10.3.2 dma destination address registers (dar_0 to dar_5) dar are 32-bit readable/writable registers that sp ecify the destination address of a dma transfer. during a dma transfer, these regi sters indicate the next destination address. when the data is transferred from an external de vice with the dack in single ad dress mode, the dar is ignored. to transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. when transferring data in 16-byte units, a 16-byte boundary must be set for the destination address value. the initial value is undefined. 10.3.3 dma transfer count registers (dmatcr_0 to dmatcr_5) dmatcr are 32-bit readable/writable registers that specify the dma transf er count. the number of transfers is 1 when the setting is h'000000 01, 16,777,215 when h'00ffffff is set, and 16,777,216 (the maximum) when h'00000000 is set. during a dma transfer, these registers indicate the remaining transfer count. the upper eight bits of dmatcr are always read as 0, and the write value should always be 0. to transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. the initial value is undefined. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 413 of 1458 rej09b0033-0300 10.3.4 dma channel control registers (chcr_0 to chcr_5) chcr are 32-bit readable/writable register s that control the dma transfer mode. bit bit name initial value r/w descriptions 31 to 24 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 23 do 0 r/w dma overrun selects whether dreq is detected by overrun 0 or by overrun 1. this bit is valid only in chcr_0 and chcr_1. this bit is always reserved and read as 0 in chcr_2 to chcr_5. the write value should always be 0. 0: detects dreq by overrun 0 1: detects dreq by overrun 1 22 tl 0 r/w transfer end level specifies whether the tend signal output is high active or low active. this bit is valid only in chcr_0 and chcr_1. this bit is always reserved and read as 0 in chcr2 to chcr_5. the write value should always be 0. 0: low-active output of tend 1: high-active output of tend 21 to 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 am 0 r/w acknowledge mode selects whether dack is outpu t in data read cycle or in data write cycle in dual address mode. in single address mode, dack is always output regardless of the specification by this bit. this bit is valid only in chcr_0 and chcr_1. this bit is always reserved and read as 0 in chcr_2 to chcr_5. the write value should always be 0. 0: dack output in read cycle (dual address mode) 1: dack output in write cycle (dual address mode) section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 414 of 1458 rej09b0033-0300 bit bit name initial value r/w descriptions 16 al 0 r/w acknowledge level specifies whether the dack signal output is high active or low active. this bit is valid only in chcr_0 and chcr_1. this bit is always reserved and read as 0 in chcr_2 to chcr_5. the write value should always be 0. 0: low-active output of dack 1: high-active output of dack 15 14 dm1 dm0 0 0 r/w r/w destination address mode 1, 0 specify whether the dma destination address is incremented, decremented, or left fixed. (in single address mode, the dm1 and dm0 bits are ignored when data is transferred to an external device with dack.) 00: fixed destination address (setting prohibited in 16- byte transfer) 01: destination address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longword- unit transfer, +16 in 16-byte transfer) 10: destination address is decremented (?1 in byte-unit transfer, ?2 in word-unit transfer, ?4 in longword- unit transfer; setting prohibited in 16-byte transfer) 11: setting prohibited 13 12 sm1 sm0 0 0 r/w r/w source address mode 1, 0 specify whether the dma source address is incremented, decremented, or left fixed. (in single address mode, sm1 and sm0 bits are ignored when data is transferred from an external device with dack.) 00: fixed source address (setting prohibited in 16-byte transfer) 01: source address is incremented (+1 in byte-unit transfer, +2 in word-unit transfer, +4 in longword- unit transfer, +16 in 16-byte transfer) 10: source address is decremented (?1 in byte-unit transfer, ?2 in word-unit transfer, ?4 in longword- unit transfer; setting prohibited in 16-byte transfer) 11: setting prohibited section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 415 of 1458 rej09b0033-0300 bit bit name initial value r/w descriptions resource select 3 to 0 specify which transfer requests will be sent to the dmac. the changing of transfer request source should be done in the state that the dma enable bit (de) is set to 0. 0 0 0 0 external request, dual address mode 0 0 0 1 setting prohibited 0 0 1 0 external request, single address mode external address space external device with dack 0 0 1 1 external request, single address mode external device with dack external address space 0 1 0 0 auto request 0 1 0 1 setting prohibited 0 1 1 0 setting prohibited 0 1 1 1 setting prohibited 1 0 0 0 selected by dma extended resource selector 1 0 0 1 setting prohibited 1 0 1 0 setting prohibited 1 0 1 1 setting prohibited 1 1 0 0 setting prohibited 1 1 0 1 setting prohibited 1 1 1 0 adc 1 1 1 1 setting prohibited 11 10 9 8 rs3 rs2 rs1 rs0 0 0 0 0 r/w r/w r/w r/w note: external request specification is valid only in chcr_0 and chcr_1. none of the external request can be selected in chcr_2 to chcr_5. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 416 of 1458 rej09b0033-0300 bit bit name initial value r/w descriptions 7 6 dl ds 0 0 r/w r/w dreq level and dreq edge select specify the detecting method of the dreq pin input and the detecting level. these bits are valid only in chcr_0 and chcr_1. these bits are always reserved and read as 0 in chcr_2 to chcr_5. the write value should always be 0. in channels 0 and 1, also, if the transfer request source is specified as an on-chip peripheral module or if an auto- request is specified, these bits are invalid. 00: dreq detected in low level 01: dreq detected at falling edge 10: dreq detected in high level 11: dreq detected at rising edge 5 tb 0 r/w transfer bus mode specifies the bus mode when dma transfers data. 0: cycle steal mode 1: burst mode 4 3 ts1 ts0 0 0 r/w r/w transfer size 1, 0 specify the size of data to be transferred. select the size of data to be transferred when the source or destination is an on-chip peripheral module register of which transfer size is specified. 00: byte size 01: word size (2 bytes) 10: longword size (4 bytes) 11: 16-byte unit (four longword transfers) 2 ie 0 r/w interrupt enable specifies whether or not an in terrupt request is generated to the cpu at the end of the dma transfer. setting this bit to 1 generates an interrupt request (dei) to the cpu when the te bit is set to 1. 0: interrupt request is disabled. 1: interrupt request is enabled. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 417 of 1458 rej09b0033-0300 bit bit name initial value r/w descriptions 1 te 0 r/(w) * transfer end flag shows that dma transfer ends. the te bit is set to 1 when data transfer ends when dmatcr becomes to 0. the te bit is not set to 1 in the following cases. ? dma transfer ends due to an nmi interrupt or dma address error before dmatcr is cleared to 0. ? dma transfer is ended by clearing the de bit and dme bit in the dma operation register (dmaor). to clear the te bit, the te bit should be written to 0 after reading 1. even if the de bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: during the dma transfer or dma transfer has been interrupted [clearing condition] writing 0 after te = 1 read 1: dma transfer ends by the specified count (dmatcr = 0) 0 de 0 r/w dma enable enables or disables the dma transfer. in auto request mode, dma transfer starts by setting the de bit and dme bit in dmaor to 1. in this ti me, all of the bits te, nmif, and ae in dmaor must be 0. in an external request or peripheral module request, dma transfer starts if dma transfer request is generated by the devices or peripheral modules after setting the bits de and dme to 1. in this case, however, all of the bits te, nmif, and ae must be 0, which is the same as in the case of auto request mode. clearing the de bit to 0 can terminate the dma transfer. 0: dma transfer disabled 1: dma transfer enabled note: * writing 0 is possible to clear the flag. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 418 of 1458 rej09b0033-0300 10.3.5 dma operation register (dmaor) dmaor is a 16-bit readable/writable register that specifies the priority level of channels at the dma transfer. this register sh ows the dma transfer status. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 cms1 cms0 0 0 r/w r/w cycle steal mode select 1, 0 select either normal mode or intermittent mode in cycle steal mode. it is necessary that all channel's bus modes are set to cycle steal mode to make valid intermittent mode. 00: normal mode 01: setting prohibited 10: intermittent mode 16 executes one dma transfer in each of 16 clocks of an external bus clock. 11: intermittent mode 64 executes one dma transfer in each of 64 clocks of an external bus clock. 11, 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 pr1 pr0 0 0 r/w r/w priority mode 1, 0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: ch0 > ch1 > ch2 > ch3 > ch4 > ch5 01: ch0 > ch2 > ch3 > ch1 > ch4 > ch5 10: setting prohibited 11: round-robin mode 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 419 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 ae 0 r/(w) * address error flag indicates that an address error occurred during dma transfer. if this bit is set, dma transfer is disabled even if the de bit in chcr and the dme bit in dmaor are set to 1. this bit can only be cleared by writing 0 after reading 1. 0: no dmac address error [clearing condition] writing ae = 0 after ae = 1 read 1: dmac address error occurs 1 nmif 0 r/(w) * nmi flag indicates that an nmi interrupt occurred. if this bit is set, dma transfer is disabled even if the de bit in chcr and the dme bit in dmaor are set to 1. this bit can only be cleared by writing 0 after reading 1. when the nmi is input, the dma transfer in progress can be done in one transfer unit. when the dmac is not in operational, the nmif bit is set to 1 even if the nmi interrupt was input. 0: no nmi interrupt [clearing condition] writing nmif = 0 after nmif = 1 read 1: nmi interrupt occurs 0 dme 0 r/w dma master enable enables or disables dma transfers on all channels. if the dme bit and the de bit in chcr are set to 1, transfer is enabled. in this time, all of the bits te in chcr, nmif, and ae in dmaor must be 0. if this bit is cleared during transfer, transfers in all channels are terminated. 0: disables dma transfers on all channels 1: enables dma transfers on all channels note: * writing 0 is possible to clear the flag. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 420 of 1458 rej09b0033-0300 10.3.6 dma extended resource select ors 0 to 2 (dmars0 to dmars2) dmars are 16-bit readable/writable registers th at specify the dma tr ansfer sources from peripheral modules in each channel. dmars0 speci fies for channels 0 an d 1, dmars1 specifies for channels 2 and 3, and dmars2 specifies for channels 4 and 5. this register can set the transfer request of scif0, siof1, mmc, cmt (channels 0 to 4), sim, usbf, siof0, siof1, and sdhi. when mid/rid other than the values listed in table 10.2 is set, the operation of this lsi is not guaranteed. the transfer request fr om dmars is valid only when th e resource select bits (rs3 to rs0) have been set to b'1000 for chcr_0 to chcr_5 registers. otherwise, even if dmars has been set, transfer requ est source is not accepted. ? dmars0 bit bit name initial value r/w description 15 14 13 12 11 10 c1mid5 c1mid4 c1mid3 c1mid2 c1mid1 c1mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id5 to id0 for dma channel 1 (mid) see table 10.2. 9 8 c1rid1 c1rid0 0 0 r/w r/w transfer request register id1 and id0 for dma channel 1 (rid) see table 10.2. 7 6 5 4 3 2 c0mid5 c0mid4 c0mid3 c0mid2 c0mid1 c0mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id5 to id0 for dma channel 0 (mid) see table 10.2. 1 0 c0rid1 c0rid0 0 0 r/w r/w transfer request register id1 and id0 for dma channel 0 (rid) see table 10.2. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 421 of 1458 rej09b0033-0300 ? dmars1 bit bit name initial value r/w description 15 14 13 12 11 10 c3mid5 c3mid4 c3mid3 c3mid2 c3mid1 c3mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id5 to id0 for dma channel 3 (mid) see table 10.2. 9 8 c3rid1 c3rid0 0 0 r/w r/w transfer request register id1 and id0 for dma channel 3 (rid) see table 10.2. 7 6 5 4 3 2 c2mid5 c2mid4 c2mid3 c2mid2 c2mid1 c2mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id5 to id0 for dma channel 2 (mid) see table 10.2. 1 0 c2rid1 c2rid0 0 0 r/w r/w transfer request register id1 and id0 for dma channel 2 (rid) see table 10.2. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 422 of 1458 rej09b0033-0300 ? dmars2 bit bit name initial value r/w description 15 14 13 12 11 10 c5mid5 c5mid4 c5mid3 c5mid2 c5mid1 c5mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id5 to id0 for dma channel 5 (mid) see table 10.2. 9 8 c5rid1 c5rid0 0 0 r/w r/w transfer request register id1 and id0 for dma channel 5 (rid) see table 10.2. 7 6 5 4 3 2 c4mid5 c4mid4 c4mid3 c4mid2 c4mid1 c4mid0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w transfer request module id5 to id0 for dma channel 4 (mid) see table 10.2. 1 0 c4rid1 c4rid0 0 0 r/w r/w transfer request register id1 and id0 for dma channel 4 (rid) see table 10.2. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 423 of 1458 rej09b0033-0300 table 10.2 transfer request sources peripheral module setting value for one channel (mid + rid) mid rid function h'21 b'01 transmit scif0 h'22 b'001000 b'10 receive h'29 b'01 transmit scif1 h'2a b'001010 b'10 receive cmt (channel 0) h'03 b'000000 b'11 ? cmt (channel 1) h'07 b'000001 b'11 ? cmt (channel 2) h'0b b'000010 b'11 ? cmt (channel 3) h'0f b'000011 b'11 ? cmt (channel 4) h'13 b'000100 b'11 ? h'83 b'11 transmit usbf h'80 b'100000 b'00 receive h'a1 b'01 transmit sim h'a2 b'101000 b'10 receive mmc h'a8 b'101010 b'00 transmit/receive h'b1 b'01 transmit siof0 h'b2 b'101100 b'10 receive h'b5 b'01 transmit siof1 h'b6 b'101101 b'10 receive sdhi h'c1 b'01 transmit h'c2 b'110000 b'10 receive section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 424 of 1458 rej09b0033-0300 10.4 operation when there is a dma transfer request, the dmac starts the transfer according to the predetermined channel priority; when the transfer end conditions are satisfie d, it ends the transfer. transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. in bus mode, burst mode or cycle steal mode can be selected. 10.4.1 dma transfer flow after the dma source address registers (sar), dma destination address registers (dar), dma transfer count registers (dmatcr), dma channel control registers (chcr), dma operation register (dmaor), and dma exte nded resource selector s (dmars) are set, the dmac transfers data according to the following procedure: 1. checks to see if transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0) 2. when a transfer request occurs while transfer is enabled, the dmac tr ansfers one transfer unit of data (depending on the ts0 and ts1 settings). in auto request mode, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value will be decremented for each transfer. th e actual transfer flows vary by address mode and bus mode. 3. when the specified number of transfer ha ve been completed (when dmatcr reaches 0), the transfer ends normally. if the ie bit in chcr is se t to 1 at this time, a dei interrupt is sent to the cpu. 4. when an address error or an nmi interrupt is generated, the transfer is aborted. transfers are also aborted when the de bit in chcr or the dme bit in dmaor is changed to 0. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 425 of 1458 rej09b0033-0300 figure 10.2 shows a flowchart of this procedure. normal end nmif = 1 or ae = 1 or de = 0 or dme = 0? bus mode, transfer request mode, dreq detection selection system initial settings (sar, dar, dmatcr, chcr, dmaor, dmars) transfer (1 transfer unit); dmatcr ? 1 dmatcr, sar and dar updated dei interrupt request (when ie = 1) te = 1 no yes no yes no yes yes no yes no * 3 * 2 start transfer aborted dmatcr = 0? transfer request occurs? * 1 de, dme = 1 and nmif, ae, te = 0? nmif = 1 or ae = 1 or de = 0 or dme = 0? transfer end notes: 1. in auto-request mode, transfer begins when the nmif, ae, and te bits are all 0 and the de and dme bits are set to 1. 2. dreq = level detection in burst mode (external request) or cycle-steal mode. 3. dreq = edge detection in burst mode (external request), or auto-request mode in burst mode. figure 10.2 dma transfer flowchart section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 426 of 1458 rej09b0033-0300 10.4.2 dma transfer requests dma transfer requests are basically generated in e ither the data transfer source or destination, but they can also be generated by external devices or on-chip peripheral modules that are neither the source nor the destination. transfers can be requ ested in three modes: au to request, external request, and on-chip peripheral module request. the request mode is selected in the rs3 to rs0 bits in chcr0 to chcr3, and dmars0 to dmars2. (1) auto-request mode when there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the de bits in chcr and the dme bit in dmaor are set to 1, the transfer begins so long as the ae and nmif bits in dmaor are all 0. (2) external request mode in this mode, a transfer is perfo rmed at the request signals (dre q0 and dreq1) of an external device. this mode is valid only in channel 0 and channel 1. choose one of the modes shown in table 10.3 according to the application system. when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon a request at the dreq input. table 10.3 selecting external request modes with rs bits rs3 rs2 rs1 rs0 address mode source destination 0 0 dual address mode any any 0 external memory, memory-mapped external device external device with dack 0 0 1 1 single address mode external device with dack external memory, memory-mapped external device section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 427 of 1458 rej09b0033-0300 choose to detect dreq by either the edge or level of the signal input with the dl bit and ds bit in chcr_0 and chcr_1 as shown in table 10.4. the source of the transfer request does not have to be the data transfer source or destination. table 10.4 selecting external request detection with dl, ds bits chcr_0 or chcr_1 dl ds detection of external request 0 low level detection 0 1 falling edge detection 0 high level detection 1 1 rising edge detection when dreq is accepted, the dreq pin becomes request accept disabled state. after issuing acknowledge signal dack for the accepted dreq, the dreq pin again becomes request accept enabled state. when dreq is used by level detection, there ar e following two cases by the timing to detect the next dreq after outputting dack. ? overrun 0: transfer is aborted after the same number of transfer has been performed as requests. ? overrun 1: transfer is aborted after transfers have been performed for (the number of requests plus 1) times. the do bit in chcr selects this overrun 0 or overrun 1. table 10.5 selecting external request detection with do bit chcr_0 or chcr_1 do external request 0 overrun 0 1 overrun 1 section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 428 of 1458 rej09b0033-0300 (3) on-chip peripheral module request mode in this mode, a transfer is perform ed at the transfer request signal of an on-chip peripheral module. transfer request signals comprise the transmit da ta empty transfer request and receive data full transfer request from the adc set by chcr0 to chcr5 and the scif0, scif1, mmc, usbf, sim, siof0, siof1, and sdhi set by dmars0 /1/2, and the compare- match timer transfer request from the cmt (channels 0 to 4). when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, ae = 0, nmif = 0), a transfer is performed upon the input of a transfer request signal. when a transmit data empty transfer request of the scif0 is set as the transf er request, the transfer destination must be the scif0's transmit data register. likewise, when receive data full transfer request of the scif0 is set as the transfer request , the transfer source must be the scif0's receive data register. these conditions also apply to the siof1, mmc, usbf, sim, siof0, siof1, and sdhi. when the adc is set as the transfer reques t, the transfer source must be the a/d data register. any address can be specifi ed for data source and destinat ion, when transfer request is generated by the cmt (channels 0 to 4). the number of the r eceive fifo triggers can be set as a tr ansfer request depending on an on-chip peripheral module. data needs to be read after th e dma transfer is ended, because data may be remained in the receive fifo when the recei ve fifo trigger condition is not satisfied. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 429 of 1458 rej09b0033-0300 table 10.6 selecting on-chip peripheral modu le request modes with rs3 to rs0 bits chcr dmars rs[3:0] mid rid dma transfer request source dma transfer request signal source destination bus mode 01 scif0 transmitter txi0 (transmit fifo data empty interrupt) any scftdr0 cycle steal 001000 10 scif0 receiver rxi0 (receive fifo data full interrupt) scfrdr0 any cycle steal 01 scif1transmitt er txi1 (transmit fifo data empty interrupt) any sitdr cycle steal 001010 10 scif1 receiver rxi1 (receive fifo data full interrupt) scfrdr1 any cycle steal 000000 11 cmt (channel 0) compare-match transfer request any any cycle steal/ burst 000001 11 cmt (channel 1) compare-match transfer request any any cycle steal/ burst 000010 11 cmt (channel 2) compare-match transfer request any any cycle steal/ burst 000011 11 cmt (channel 3) compare-match transfer request any any cycle steal/ burst 1000 000100 11 cmt (channel 4) compare-match transfer request any any cycle steal/ burst section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 430 of 1458 rej09b0033-0300 chcr dmars rs[3:0] mid rid dma transfer request source dma transfer request signal source destination bus mode 11 usbf transmitter transmit data empty request any epdr2 cycle steal 100000 00 usbf receiver transmit data full request epdr1 any cycle steal 01 sim transmitter txi (transmit data empty) any sctdr cycle steal 101000 10 sim receiver rxi (receive data full) scrdr any cycle steal mmc transmitter receive data empty request any data register cycle steal 101010 00 mmc receiver receive data full request data register any cycle steal 01 siof0 transmitter txi0 (transmit fifo data empty) any sitdr0 cycle steal 101100 10 siof0 receiver rxi0 (receive fifo data full) sirdr0 any cycle steal 01 siof1 transmitter txi1 (transmit fifo data empty) any sitdr1 cycle steal 101101 10 siof1 receiver rxi1 (receive fifo data full) sirdr0 any cycle steal 01 sd transmitter transmit data empty request any data register cycle steal 1000 110000 10 sd receiver receive data full request data register any cycle steal 1110 ? ? adc adi (a/d conversion end) addr any cycle steal section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 431 of 1458 rej09b0033-0300 10.4.3 channel priority when the dmac receives simultaneous transfer re quests on two or more channels, it transfers data according to a predetermined priority. two modes (fixed mode and round-robin mode) are selected by the pr1 and pr0 bits in dmaor. (1) fixed mode in this mode, the priority levels among the channels remain fixed. there are two kinds of fixed modes as follows: ? ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ? ch0 > ch2 > ch3 > ch1 > ch4 > ch5 these are selected by the pr1 and the pr0 bits in dmaor. (2) round-robin mode in round-robin mode each time data of one transfer unit (word, byte, longword, or 16-byte unit) is transferred on one channel, the pr iority is rotated. the channel on which the tran sfer was just finished rotates to the bottom of the priority. the round-robin mode operation is shown in figure 10.3. the priority of round-robin mode is ch0 > ch1 > ch2 > ch3 > ch4 > ch5 immediately after a reset. when round-robin mode is specified, the same bus mode, either cycle steal mode or burst mode, must be specified for all of the channels. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 432 of 1458 rej09b0033-0300 ch1 > ch2 > ch3 > ch4 > ch5 > ch0 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch2 > ch3 > ch4 > ch5 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 ch3 > ch4 > ch5 > ch0 > ch1 > ch2 ch0 > ch1 > ch2 > ch3 > ch4 > ch5 (1) when channel 0 transfers initial priority order initial priority order initial priority order initial priority order priority order after transfer priority order does not change. channel 2 becomes bottom priority. the priority of channels 0 and 1, which were higher than channel 2, are also shifted. if immediately after there is a request to transfer channel 5 only, channel 5 becomes bottom priority and the priority of channels 3 and 4, which were higher than channel 5, are also shifted. channel 1 becomes bottom priority. the priority of channel 0, which was higher than channel 1, is also shifted. channel 0 becomes bottom priority priority order after transfer priority order after transfer priority order after transfer post-transfer priority order when there is an immediate transfer request to channel 5 only (2) when channel 1 transfers (3) when channel 2 transfers (4) when channel 5 transfers figure 10.3 round-robin mode section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 433 of 1458 rej09b0033-0300 figure 10.4 shows how the priority changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. the dmac operates as follows: 1. transfer requests are generated simultaneously to channels 0 and 3. 2. channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. a channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. when the channel 0 transfer ends, channel 0 becomes lowest priority. 5. at this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. when the channel 1 transfer ends, channel 1 becomes lowest priority. 7. the channel 3 transfer begins. 8. when the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority. transfer request waiting channel(s) dmac operation channel priority (1) channels 0 and 3 (3) channel 1 0 > 1 > 2 > 3 > 4 > 5 (2) channel 0 transfer starts (4) channel 0 transfer ends (5) channel 1 transfer starts (6) channel 1 transfer ends (7) channel 3 transfer starts (8) channel 3 transfer ends 1 > 2 > 3 > 4 > 5 > 0 2 > 3 > 4 > 5 > 0 > 1 4 > 5 > 0 > 1 > 2 > 3 priority order changes priority order changes priority order changes none 3 3 1,3 figure 10.4 changes in channe l priority in round-robin mode section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 434 of 1458 rej09b0033-0300 10.4.4 dma transfer types dma transfer has two types; single address mode transfer and dual address mode transfer. they depend on the number of bus cycl es of access to source and dest ination. a data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. the dmac supports the transfers shown in table 10.7. table 10.7 supported dma transfers destination source external device with dack external memory memory- mapped external device on-chip peripheral module x/y memory u memory external device with dack not available dual, single dual, single not available not available external memory dual, single dual dual dual dual memory-mapped external device dual, single dual dual dual dual on-chip periphera l module not available dual dual dual dual x/y memory not available dual dual dual dual notes: 1. dual: dual address mode 2. single: single address mode 3. for on-chip peripheral modules, 16-byte transfer is available only by registers which can be accessed in longword units. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 435 of 1458 rej09b0033-0300 (1) address modes (a) dual address mode in dual address mode, both the transfer source and destination are accessed by an address. the source and destination can be located externally or internally. dma transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a da ta write cycle. at this time, transfer data is temporarily stored in the dmac. in the transfer between external memories as shown in figure 10.5, data is read to the dmac from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar the sar value is an address, data is read from the transfer source module, and the data is temporarily stored in the dmac. first bus cycle second bus cycle the dar value is an address and the value stored in the data buffer in the dmac is written to the transfer destination module. dmac dmac figure 10.5 data flow of dual address mode auto request, external request, and on-chip peripher al module request are av ailable for the transfer request. dack can be output in read cycle or write cycle in dual address mode. the channel control register (chcr) can specify whether the dack is output in read cycle or write cycle. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 436 of 1458 rej09b0033-0300 figure 10.6 shows an example of dma transfer timing in dual address mode. ckio a25 to a0 note: in transfer between external memories, with dack output in the read cycle, dack output timing is the same as that of csn . d31 to d0 wen rd dackn (active-low) csn transfer source address transfer destination address data read cycle data write cycle (1st cycle) (2nd cycle) figure 10.6 example of dma tr ansfer timing in dual mode (source: ordinary memory, dest ination: ordinary memory) section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 437 of 1458 rej09b0033-0300 (b) single address mode in single address mode, either the transfer source or transfer destination peripheral device is accessed (selected) by means of the dack signal, and the other device is accessed by an address. in this mode, the dmac performs one dma tran sfer in one bus cycle, accessing one of the external devices by outputting the dack transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. for example, in the case of transfer between external memory and an external device with dack shown in figure 10.7, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. dmac this lsi dack dreq external address bus external data bus external memory external device with dack data flow figure 10.7 data flow in single address mode two kinds of transfer are possible in single address mode: (1) tran sfer between an external device with dack and a memory-mapped external device, and (2) transfer between an external device with dack and external memory. in both cases, onl y the external request signal (dreq) is used for transfer requests. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 438 of 1458 rej09b0033-0300 figure 10.8 shows an example of dma transfer timing in single address mode. address output to external memory space select signal to external memory space select signal to external memory space data output from external device with dack dack signal (active-low) to external device with dack write strobe signal to external memory space address output to external memory space data output from external memory space dack signal (active-low) to external device with dack read strobe signal to external memory space (a) external device with dack external memory space (ordinary memory) (b) external memory space (ordinary memory) external device with dack ckio a25 to a0 d31 to d0 dackn csn we ckio a25 to a0 d31 to d0 dackn csn rd figure 10.8 example of dma transf er timing in single address mode section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 439 of 1458 rej09b0033-0300 (2) bus modes there are two bus modes: cycle steal mode and burst mode. select th e mode in the tb bits in the channel control register (chcr). (a) cycle-steal mode ? normal mode in cycle-steal normal mode, th e bus mastership is given to another bus master after a one- transfer-unit (byte, word, longword, or 16-byte unit) dma transfer. when another transfer request occurs, the bus mastership is obtained from the other bus mast er and a transfer is performed for one transfer unit. when that transfer ends, the bus mastership is passed to the other bus master. this is repeated until th e transfer end conditions are satisfied. in cycle-steal normal mode , transfer areas are not affected rega rdless of settings of the transfer request source, transf er source, and transfer destination. figure 10.9 shows an example of dma transfer timing in cycl e-steal normal mode. transfer conditions shown in the figure are: ? dual address mode ? dreq low level detection cpu cpu cpu dmac dmac cpu dmac dmac cpu dreq bus cycle bus mastership returned to cpu once read/write read/write figure 10.9 dma transfer exampl e in cycle-steal normal mode (dual address, dreq low level detection) ? intermittent mode 16 and intermittent mode 64 in intermittent mode of cycle steal, the dmac returns the bus mastership to other bus master whenever a unit of transfer (byte, word, longword, or 16-byte unit) is complete. if the next transfer request occurs after that, the dmac ge ts the bus mastership from other bus master after waiting for 16 or 64 clocks in b count. the dmac then transfers data of one unit and returns the bus mastership to ot her bus master. these operations ar e repeated until the transfer end condition is satisfied. it is thus possible to make lower the ratio of bus occupation by dma transfer than cycle-steal normal mode. when the dmac gets again the bus mastership , dma transfer can be postponed in case of entry updating due to cache miss. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 440 of 1458 rej09b0033-0300 this intermittent mode can be used for all transf er section; transfer re quest source, transfer source, and transfer destination. the bus mode s, however, must be cycle steal mode in all channels. figure 10.10 shows an example of dma transf er timing in cycle steal intermittent mode. transfer conditions shown in the figure are: ? dual address mode ? dreq low level detection dreq cpu cpu bus cycle cpu more than 16 or 64 b (change by the cpu, lcdc, and usbh states of using bus) dmac dmac cpu cpu dmac dmac cpu read/write read/write figure 10.10 example of dma transfer in cycle steal intermittent mode (dual address, dreq low level detection) (b) burst mode in burst mode, once the dmac obtains the bus mast ership, the transfer is performed continuously without releasing the bus mastership until the tr ansfer end condition is satisfied. in external request mode with level detection of the dreq pin, however, when the dreq pin is not active, the bus mastership passes to the other bus master after the dmac tr ansfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. burst mode cannot be used for other than cmt (channels 0 to 4) when the on-chip peripheral module is the transfer request source. figure 10.11 shows dma tran sfer timing in burst mode. cpu cpu cpu dmac dmac dmac dmac dmac dmac cpu dreq bus cycle read read read write write write figure 10.11 dma transf er example in burst mode (dual address, dreq low level detection) section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 441 of 1458 rej09b0033-0300 (3) relationship between request modes and bus modes by dma transfer category table 10.8 shows the relationship between request modes and bus modes by dma transfer category. table 10.8 relationship between request modes and bus modes by dma transfer category address mode transfer category request mode bus mode transfer size (bits) usable channels external device with dack and external memory external b/c 8/16/32/128 0,1 external device with dack and memory- mapped external device external b/c 8/16/32/128 0, 1 external memory and external memory all * 1 b/c 8/16/32/128 0 to 5 * 5 external memory and memory-mapped external device all * 1 b/c 8/16/32/128 0 to 5 * 5 memory-mapped external device and memory-mapped external device all * 1 b/c 8/16/32/128 0 to 5 * 5 external memory and on-chip peripheral module all * 2 b/c * 3 8/16/32/128 * 4 0 to 5 * 5 memory-mapped external device and on-chip peripheral module all * 2 b/c * 3 8/16/32/128 * 4 0 to 5 * 5 on-chip peripheral module and on-chip peripheral module all * 2 b/c * 3 8/16/32/128 * 4 0 to 5 * 5 x/y memory and x/y memory all * 1 b/c 8/16/32/128 0 to 5 * 5 x/y memory and memory-mapped external device all * 1 b/c 8/16/32/128 0 to 5 * 5 x/y memory and on-chip peripheral module all * 2 b/c * 3 8/16/32/128 * 4 0 to 5 * 5 dual x/y memory and external memory all * 1 b/c 8/16/32/128 0 to 5 * 5 external device with dack and external memory external b/c 8/16/32 0, 1 single external device with dack and memory- mapped external device external b/c 8/16/32 0, 1 b: burst mode, c: cycle steal mode section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 442 of 1458 rej09b0033-0300 notes: 1. external requests, auto requests, and on-chip peripheral module requests are all available. in the case of on-chip peri pheral module requests, however, the cmt (channels 0 to 4) are only available. 2. external requests, auto requests, and on-chip peripheral module requests are all available. however, with the exception of the cmt (channels 0 to 4) as the transfer request source, the request source register must be designated as the transfer source or the transfer destination. 3. only cycle steal except for the cmt (channel s 0 to 4) as the transfer request source. 4. access size permitted for the on-chip perip heral module register functioning as the transfer source or transfer destination. 5. if the transfer request is an external request, channels 0 and 1 are only available. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 443 of 1458 rej09b0033-0300 (4) bus mode and channel priority when the priority is set in fixed mode (ch0 > ch 1), even though channel 1 is transferring in burst mode, if there is a transfer request to channel 0 wh ich has a higher priority, the transfer of channel 0 will begin immediately. at this time, if channel 0 is also operating in burs t mode, the channel 1 transfer will continue when the channel 0 transfer with a higher priority has completely finished. if channel 0 is operating in cycle steal mode, immediately after channel 0 with a higher priority completes the transfer of one transfer unit, the channel 1 transfer will begin again without releasing the bus mastership . transfer will then sw itch between the two in the order of channel 0, channel 1, channel 0, and channel 1. for the bu s state, the cpu cycle after cycle steal mode transfer finishes is replaced with a burst mode transfer cycle (hereafter referred to as burst mode high-priority execution). this example is illustrated in figure 10.12. if th ere are channels with conf licting burst transfers, transfer for the channel with the hi ghest priority is performed first. in dma transfer for more than one channel, the dmac does not give the bus mastership to the bus master until all conflicting burst transfers have finished. cpu dma ch1 dma ch1 dma ch0 dma ch1 dma ch0 dma ch1 dma ch1 cpu ch0 ch1 ch0 dmac ch0 and ch1 cycle-steal mode dmac ch1 burst mode cpu cpu priority: ch0 > ch1 ch0: cycle-steal mode ch1: burst mode dmac ch1 burst mode figure 10.12 bus state when multiple channels are operating in round-robin mode, the priority changes according to the specifications shown in figure 10.3. note that a channel operating in cycle steal mo de cannot be handled together with a channel operating in burst mode. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 444 of 1458 rej09b0033-0300 10.4.5 number of bus cycle states and dreq pin sampling timing (1) number of bus cycle states when the dmac is the bus master, the number of bus cycle states is cont rolled by the bus state controller (bsc) in the same way as when the cp u is the bus master. for details, see section 9, bus state controller (bsc). (2) dreq pin sampling timing figures 10.13, 10.14, 10.15, and 10.16 show the sample timing of the dreq input in each bus mode, respectively. ckio bus cycle dreq (rising edge) dack (high-active) cpu non-sensitive period 1st acceptance 2nd acceptance acceptance started cpu cpu dmac figure 10.13 example of dreq input detect ion in cycle steal mode edge detection section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 445 of 1458 rej09b0033-0300 ckio bus cycle dreq (overrun 0, high-level) bus cycle dreq (overrun 1, high-level) dack (high-active) cpu cpu cpu dmac ckio dackn (high-active) cpu cpu cpu dmac non-sensitive period non-sensitive period non-sensitive period 1st acceptance 2nd acceptance 1st acceptance 2nd acceptance acceptance started acceptance started figure 10.14 example of dreq input detect ion in cycle steal mode level detection ckio dreq (rising edge) dack (high-active) cpu cpu dmac dmac bus cycle non-sensitive period burst acceptance figure 10.15 example of dreq input detection in burst mode edge detection section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 446 of 1458 rej09b0033-0300 ckio dack (high-active) cpu cpu dmac ckio dack (high-active) cpu cpu dmac dmac bus cycle dreq (overrun 0, high-level) bus cycle dreq (overrun 1, high-level) non-sensitive period non-sensitive period 1st acceptance 1st acceptance 3rd acceptance 2nd acceptance acceptance started acceptance started acceptance started 2nd acceptance figure 10.16 example of dreq input detection in burst mode level detection dmac cpu cpu cpu dmac ckio dreq dack tend bus cycle last dma transfer figure 10.17 example of dma transfer end in cycle steal mode level detection section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 447 of 1458 rej09b0033-0300 when an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external device is accessed in word units, th e dack output is divided because of the data alignment. this example is illustrated in figure 10.18. ckio csn wen wait rd address data t1 t2 taw t1 t2 note: the dack is asserted for the last transfer unit of the dma transfer. when the transfer unit is divided into several bus cycles and the csn is negated between bus cycles, the dack is also divided. dackn (active-low) figure 10.18 example of bsc ordinary memory access (no wait, idle cycle 1, longwo rd access to 16-bit device) section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 448 of 1458 rej09b0033-0300 10.5 usage notes pay attentions to the following notes when the dmac is used. 10.5.1 notes on dack pin output when burst mode and cycle steal mode are simultaneously set in two or more channels, an additional dack may be asserted at the end of bu rst transfer. this phenomenon will occur when all of the conditions described below are satisfied. 1. when the dma transfer is simultaneously performed in two or more channels support both burst mode and cycle steal mode 2. when the channel to be used in burst mode is set to dual address mode, and dack is output in data write cycle 3. when the dmac cannot obtain the bus master ship consecutively even though a transfer demand of cycle steal has been received after the completion of burst transfer this phenomenon is avoided by taking either of three measures shown below. ? measure 1 after confirming the completion of burst transfer ( te bit = 1), perform the dma transfer of other cycle steal mode ? measure 2 the channel to be used in burst mode should not be set to output dack in data write cycle ? measure 3 when the dma transfer is simultaneously performed in two or more channels, set all of the channels to burst mode or cycle steal mode 10.5.2 notes on the cases when dack is divided (1) overview when dack is divided for output while the dmac is accessing an external device, sampling of dreq may be accepted once more during the access. (2) conditions and phenomena conditions: in the cases wh en dack is divided for output duri ng external access, specifically, the following cases: section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 449 of 1458 rej09b0033-0300 ? 16-byte access ? 32-bit access in an 8-bit space ? 16-bit access in an 8-bit space ? 32-bit access in a 16-bit space, any one of the following inter- access idle cycle specifications ha s been made for that space: ? idle between write cycles (iww = 001 or more) ? idle between read cycles in the same space (iwrrs = 001 or more) ? external wait masking (wm = 0) phenomena: for the access pa tterns above, the dreq pin signal is detected with the timing shown in figures 10.19 and 10.21. for other access patte rns, dreq is detected normally as shown in figures 10.20 and 10.22. (3) how to avoid the problem for the external accesses under th e conditions of 2 above, the pr oblems can be avoided in the following way: 1. detection of dreq edges: during the bus cycle, input a dreq edge (rising edge) only once at most. 2. when overrun-0 in dreq level detection is sp ecified: during the bus cycle, negate the dreq input after detection of the first dack output negation but before the second dack output negation takes place. 3. when overrun-1 in dreq level detection is specified: during the bus cycle, negate the dreq input after detection of the first dack output assertion but before the second dack output assertion takes place. section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 450 of 1458 rej09b0033-0300 (4) dreq pin detection timing charts ckio bus cycle dreq (rising edge) dack (active-high) cpu dmac write or read first acceptance second acceptance third acceptance (possible) dead zone dead zone acceptance started acceptance started dead zone figure 10.19 timing of dreq input detection by edge detection in cycle stealing mode (dack is divided into four due to idle cy cle insertion between access cycles and so dreq sampling is accepted one extra time) ckio bus cycle dreq (rising edge) dack (active-high) cpu dmac write or read first acceptance second acceptance dead zone dead zone acceptance started acceptance started third acceptance dead zone figure 10.20 timing of dreq input detection by edge detection in cycle stealing mode (dack is not divided by idle cycle inse rtion between access cy cles and so dreq sampling is accepted normally) section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 451 of 1458 rej09b0033-0300 ckio bus cycle dreq (overrun 0, high level) dack (active-high) cpu first acceptance second acceptance third acceptance (possible) dead zone dead zone ckio bus cycle dreq (overrun 1, high level) dack (active-high) cpu first acceptance second acceptance third acceptance (possible) dead zone dead zone acceptance started dmac write or read dmac write or read acceptance started figure 10.21 timing of dreq input detection by level detection in cycle stealing mode (dack is divided into four due to idle cy cle insertion between access cycles and so dreq sampling is accepted one extra time) section 10 direct memory access controller (dmac) rev. 3.00 jan. 18, 2008 page 452 of 1458 rej09b0033-0300 ckio bus cycle dreq (overrun 0, high level) dack (high active) ckio bus cycle dreq (overrun 1, high level) dack (active-high) cpu first acceptance second acceptance third acceptance dead zone dead zone dead zone first acceptance second acceptance third acceptance dead zone dead zone dead zone acceptance started acceptance started dmac write or read acceptance started acceptance started cpu dmac write or read figure 10.22 timing of dreq input detection by edge dete ction in cycle stealing mode (dack is not divided by idle cycle inse rtion between access cy cles and so dreq sampling is accepted normally) 10.5.3 other notes 1. before making a transition to standby mode, either wait until dma transfer finishes or suspend dma transfer. 2. if an on-chip peripheral module whose clock supply is to be stopped by the module standby function is performing dma transfer, either wait until dma transfer finishes or suspend dma transfer before making a transition to module standby mode. 3. do not write to sar, dar, dmatcr, or dmars during dma transfer. concerning above notes 1 and 2: dma transfer end can be confirmed by checking whether the te bit in chcr is set to 1. to suspend dma transfer, clear the de bit in chcr to 0. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 453 of 1458 rej09b0033-0300 section 11 clock pulse generator (cpg) this lsi has a clock pulse generator which generates an internal clock (i ), a peripheral clock (p ), and a bus clock (b ). the clock pulse generator consists of oscillators, pll circuits, and a divider. 11.1 features the cpg has the following features: ? four clock modes: selection of four clock modes according to the frequency range to be used and direct connection of crystal re sonator or external clock input. ? three clocks generated independently: an internal clock for the cpu and cache (i ); a peripheral clock (p ) for the on-chip supporting modules; and a bus clock (b =ckio) for the external bus interface. ? frequency change function: internal and peripheral clock frequencies can be changed independently using the pll circuit and divider circuit within the cpg. frequencies are changed by software using frequency control register (frqcr) settings. ? power-down mode control: the clock can be stopped for sleep mode and standby mode and specific modules can be stopped using the module standby function. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 454 of 1458 rej09b0033-0300 a block diagram of the cpg is shown in figure 11.1. ckio extal_usb xtal crystal oscillator pll circuit 1 ( 1, 2, 3, 4) pll circuit 2 ( 1, 4) oscillator circuit clock frequency control unit standby control unit frqcr stbcr bus interface internal bus frqcr : frequency control register uckcr : usbh/usbf clock control register stbcr : standby control register 1 stbcr2 : standby control register 2 stbcr3 : standby control register 3 stbcr4 : standby control register 4 stbcr5 : standby control register 5 peripheral clock (p ) extal md2 to md0 cpg control unit xtal_usb 1 1/2 1/3 1/4 1/6 internal clock (i ) usbh/usbf clock divider 1 bus clock (b frequency is the same as ckio frequency.) stbcr3 stbcr2 uclkcr stbcr4 stbcr5 crystal oscillator figure 11.1 block diagram of cpg section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 455 of 1458 rej09b0033-0300 the individual clock pulse generator blocks function as follows: (1) pll circuit 1 pll circuit 1 doubles, triples, quadruples, or leaves unchanged the input clock frequency from the ckio terminal. the multiplication rate is set by th e frequency control register. when this is done, the phase of the leading edge of the internal clock is controlled so that it will agree with the phase of the leading edge of the ckio pin. (2) pll circuit 2 pll circuit 2 quadruples or leaves unchanged the input clock frequency from the crystal oscillator or extal pin. the multiplication rate is set in the clock operating modes. the clock operating modes are set by pins md0, md1, and md2. see table 11.2 for more information on clock operating modes. (3) crystal oscillator this oscillator is used when a crystal resonator is connected to the xtal or extal pin. it operates according to the clock operating mode setting. (4) divider 1 divider 1 generates a clock at the operating frequency used by the internal or peripheral clock. the operating frequency of the internal clock (i ) can be 1, 1/2, 1/3, or 1/4 times the output frequency of pll circuit 1, as long as it stays at or above the clock frequency of the ckio pin. the operating frequency of the peripheral clock (p ) can be 1, 1/2, 1/3, 1/4, or 1/6 times the output frequency of pll circuit 1 within 8.34 mhz p 33.34 mhz. the division ratio is set in the frequency control register. (5) clock frequency control circuit the clock frequency control circuit controls the clock frequency using the md0, md1, and md2 pins and the frequency control register. (6) standby control circuit the standby control circuit controls the state of the clock pulse generator and other modules during clock switching or in sleep or standby mode. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 456 of 1458 rej09b0033-0300 (7) frequency control register the frequency control register has control bits assigned for the following functions: clock output/non-output from the ckio pin, the frequency multiplication ratio of pll circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. (8) standby control register the standby control register has bits for controlling the power-down modes. see section 13, power-down modes, for more information. (9) usbh/usbf clock control register the usbh/usbf clock control register specifies a signal source for generation of the usbh/usbf clock. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 457 of 1458 rej09b0033-0300 11.2 input/output pins table 11.1 lists the cpg pins and their functions. table 11.1 pin configuration pin name abbreviation i/o description mode control pins md0 input set the clock operating mode md1 input set the clock operating mode md2 input set the clock operating mode xtal output connects a crystal resonator crystal i/o pins (clock input pins) extal input connects a crystal resonator. also used to input an external clock. clock i/o pin ckio i/o inputs or outputs an external clock extal_usb input external clock pin for usbh/usbf xtal_usb output inputs an external clock to usbh/usbf (48 mhz) note: to prevent device malfunction, the value of the mode control pin is sampled only upon a power-on reset. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 458 of 1458 rej09b0033-0300 11.3 clock operating modes table 11.2 shows the relationship between the mode control pins (md2 to md0) combinations and the clock modes. table 11.3 shows the available combinations of the values of the clock modes and frequency control register (frqcr). table 11.2 clock operating modes pin values clock i/o mode md2 md1 md0 source output pll2 on/off pll1 on/off ckio frequency 0 0 0 0 extal ckio on (x 1) on (x 1, 2, 3, 4) (extal) 1 0 0 1 extal ckio on (x 4) on (x 1, 2, 3, 4) (extal) x 4 2 0 1 0 crystal resonator ckio on (x 4) on (x 1, 2, 3, 4) (crystal) x 4 7 1 1 1 ckio ? off on (x 1, 2, 3, 4) (ckio) mode 0: the lsi is supplied with a clock that is wave-formed by pll circuit 2 after receiving an external clock from the extal pin. the fr equency of ckio ranges from 24.00 to 66.67 mhz, because the input clock frequen cy ranges from 24.00 to 66.67 mhz. mode 1: the clock supplied to the internal circ uitry in the lsi is generated by pll circuit 2 quadrupling the frequency after receiving an external clock from the extal pin. therefore, the frequency of a clock gener ated outside the lsi can be lower. the frequency of ckio ranges from 40.00 to 66.67 mhz, because an input clock with a frequency range of 10.00 to 16.67 mhz is used. mode 2: the clock is generated by an on-chip cr ystal oscillator, and its frequency is quadrupled by pll circuit 2. therefore, t he frequency of a clock generated outside the lsi can be lower. the frequency of ckio ranges from 40.00 to 66. 67 mhz, because a crystal oscillator with a frequency range of 10.00 to 16.67 mhz is used. mode 7: the ckio pin works as an input pin in th is mode. the frequency of the external clock supplied to the lsi is multiplied by the setting ratio after the external clock is input via the ckio pin and wave-formed by pll circuit 1. this mode is suitable for connecting a synchronous dram, because the change in the lo ad in the ckio pin is controlled by pll circuit 1. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 459 of 1458 rej09b0033-0300 table 11.3 possible combination of clock mode and frqcr values mode frqcr value pll circuit 1 pll circuit 2 clock ratio * (i:b:p) frequency range of input clock and crystal resonator frequency range of ckio pin 0 1000 on ( 1) on ( 1) 1:1:1 33.34 mhz 33.34 mhz 1001 on ( 1) on ( 1) 1:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1003 on ( 1) on ( 1) 1:1:1/4 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1101 on ( 2) on ( 1) 2:1:1 33.34 mhz 33.34 mhz 1103 on ( 2) on ( 1) 2:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1111 on ( 2) on ( 1) 1:1:1 33.34 mhz 33.34 mhz 1113 on ( 2) on ( 1) 1:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1202 on ( 3) on ( 1) 3:1:1 33.34 mhz 33.34 mhz 1204 on ( 3) on ( 1) 3:1:1/2 33.34 mhz to 44.45 mhz 33.34 mhz to 44.45 mhz 1222 on ( 3) on ( 1) 1:1:1 33.34 mhz 33.34 mhz 1224 on ( 3) on ( 1) 1:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1303 on ( 4) on ( 1) 4:1:1 33.34 mhz 33.34 mhz 1313 on ( 4) on ( 1) 2:1:1 33.34 mhz 33.34 mhz 1333 on ( 4) on ( 1) 1:1:1 33.34 mhz 33.34 mhz 1, 2 1001 on ( 1) on ( 4) 4:4:2 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1003 on ( 1) on ( 4) 4:4:1 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1103 on ( 2) on ( 4) 8:4:2 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1113 on ( 2) on ( 4) 4:4:2 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1204 on ( 3) on ( 4) 12:4:2 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz 1224 on ( 3) on ( 4) 4:4:2 10.00 mhz to 16.67 mhz 40.00 mhz to 66.67 mhz section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 460 of 1458 rej09b0033-0300 mode frqcr value pll circuit 1 pll circuit 2 clock ratio * (i:b:p) frequency range of input clock and crystal resonator frequency range of ckio pin 7 1000 on ( 1) off 1:1:1 33.34 mhz 33.34 mhz 1001 on ( 1) off 1:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1003 on ( 1) off 1:1:1/4 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1101 on ( 2) off 2:1:1 33.34 mhz 33.34 mhz 1103 on ( 2) off 2:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1111 on ( 2) off 1:1:1 33.34 mhz 33.34 mhz 1113 on ( 2) off 1:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1202 on ( 3) off 3:1:1 33.34 mhz to 44.45 mhz 33.34 mhz to 44.45 mhz 1204 on ( 3) off 3:1:1/2 33.34 mhz to 44.45 mhz 33.34 mhz to 44.45 mhz 1222 on ( 3) off 1:1:1 33.34 mhz 33.34 mhz 1224 on ( 3) off 1:1:1/2 33.34 mhz to 66.67 mhz 33.34 mhz to 66.67 mhz 1303 on ( 4) off 4:1:1 33.34 mhz 33.34 mhz 1313 on ( 4) off 2:1:1 33.34 mhz 33.34 mhz 1333 on ( 4) off 1:1:1 33.34 mhz 33.34 mhz notes: * the input clock is 1. maximum frequency: i = 133.34 mhz, b (ckio) = 66.67 mhz, p = 33.34 mhz 1. use the ckio frequency within 33.34 mhz ckio 66.67 mhz. 2. the input to divider 1 is the output of pll circuit 1. 3. use the internal clock frequency within 33.34 mhz i 133.34 mhz. the internal clock frequency is the produc t of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1 selected by the stc bit in frqcr, and the division ratio selected by the ifc bit in frqcr. do not set the internal clock frequency lower than the ckio pin frequency. 4. use the peripheral clock frequency within 8.34 mhz p 33.34 mhz. the peripheral clock frequency is the produc t of the frequency of the ckio pin, the frequency multiplication ratio of pll circuit 1 selected by the stc bit in frqcr, and the division ratio selected by the pfc bit in frqcr. do not set the peripheral clock frequency hi gher than the frequency of the ckio pin. 5. 1, 2, 3, or 4 can be used as the multiplication ratio of pll circuit 1. 1, 1/2, 1/3, or 1/4can be selected as the division ratio of an internal clock. 1, 1/2, 1/3, 1/4, or 1/6 can be selected as the division ratio of a peripheral clock. set the rate in frqcr. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 461 of 1458 rej09b0033-0300 11.4 register descriptions the cpg has the following registers. refer to section 37, list of registers, for more details on the addresses and access size of these registers. ? frequency control register (frqcr) ? usbh/usbf clock control register (uclkcr) 11.4.1 frequency cont rol register (frqcr) the frequency control register (frqcr) is a 16-b it readable/writable register used to specify whether a clock is output from the ckio pin, the frequency multiplication ratio of pll circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. only word access can be used on the frqcr regist er. frqcr is initialized by a power-on reset, but not initialized by a power-on reset at the wdt overflow. frqcr retains its value in a manual reset and in standby mode. the write values to bits 14, 13, 11, 10, 7, 6, and 3 should always be 0. bit bit name initial value r/w description 15 pll2en 0 r/w pll2 enable pll2en specifies whether make the pll circuit 2 on in clock operating mode 7. pll circuit 2 is on in clock operating modes other than mode 7 regardless of the pll2en setting. 0: pll circuit 2 is off 1: pll circuit 2 is on 14, 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 462 of 1458 rej09b0033-0300 bit bit name initial value r/w description 12 ckoen 1 r/w clock output enable ckoen specifies whether a clock is output from the ckio pin or the ckio pin is placed in the level-fixed state in the standby mode, ckio pin is fixed at low during status 1 = l, and status0 = h, when ckoen is set to 0. therefore, the malfunction of an external circuit because of an unstable ckio clock in releasing the standby mode can be prevented. the ckio pin becomes to input pin regardless of the value of the ckoen bit in clock operating mode 7. 0: ckio pin goes to low level state in standby mode 1: clock is output from ckio pin 11, 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 stc1 stc0 0 0 r/w r/w frequency multiplication ratio of pll circuit 1 00: 1 time 01: 2 times 10: 3 times 11: 4 times 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 4 ifc1 ifc0 0 0 r/w r/w internal clock frequency division ratio these bits specify the frequency division ratio of the internal clock (i ) with respect to the output frequency of pll circuit 1. 00: 1 time 01: 1/2 time 10: 1/3 time 11: 1/4 time 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 463 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 1 0 pfc2 pfc1 pfc0 0 1 1 r/w r/w r/w peripheral clock frequency division ratio these bits specify the division ratio of the peripheral clock (p ) frequency with respect to the output frequency of pll circuit 1. 000: 1 time 001: 1/2 time 010: 1/3 time 011: 1/4 time 100: 1/6 time other than above: reserved (setting prohibited) section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 464 of 1458 rej09b0033-0300 11.4.2 usbh/usbf clock control register (uclkcr) the usbh/usbf clock control register is an 8-bit readable/writable register. uclkcr is initialized to h'60 by a power-on reset. word-size access is used to write to this register. this writing should be performed with h'a5 in the upper byte and the write data in the lower byte. bit bit name initial value r/w description 7 6 5 usscs2 usscs1 usscs0 0 1 1 r/w r/w r/w source clock select these bits select the source clock. 000: clock stopped 001: setting prohibited 010: setting prohibited 011: initial value (to run the usbh/usb, however, change the setting to "110: extal_usb" or "111: usb crystal resonator".) 100: setting prohibited 101: setting prohibited 110: extal_usb 111: usb crystal resonator 4 usstb 0 r/w standby usb crystal specifies stop or operation of the usb crystal oscillator in standby mode. 0: usb crystal oscillator stops in standby mode when the stbxtl bit (bit 4) in t he stbcr register is 0. 1: usb crystal oscillator c ontinues operating in standby mode 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 465 of 1458 rej09b0033-0300 11.5 changing frequency the frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of pll circuit 1 or by changing the division rates of divider 1. all of these are controlled by software through frqcr. the methods are described below. 11.5.1 changing multiplication rate a pll settling time is required when the multiplicati on rate of pll circuit 1 is changed. the on- chip wdt counts the settling time. 1. in the initial state, the multiplication rate of pll circuit 1 is 1. 2. set a value that will become the specified os cillation settling time in the wdt and stop the wdt. the following must be set: tme bit in wtcsr = 0: wdt stops cks2 to cks0 bits in wtcsr: division ratio of wdt count clock wtcnt: initial counter value 3. set the desired value in the stc1 and stc0 bits. the division ratio can also be set in the ifc1 and ifc0 bits and pfc2 to pfc0 bits. 4. the processor pauses internally and the wdt st arts incrementing. the in ternal and peripheral clocks both stop and the wdt is supplied with the clock. the clock will continue to be output at the ckio pin. 5. supply of the clock that has been set begins at wdt count overflow, and the processor begins operating again. the wdt stops after it overflows. 11.5.2 changing division ratio the wdt will not count unless the multiplication rate is changed simultaneously. 1. in the initial state, ifc1 and ifc0 = 00 and pfc2 to pfc0 = 011. 2. set the ifc1, ifc0, and pfc2 to pfc0 bits to the new division ratio. the values that can be set are limited by the clock mode and the multiplication rate of pll circuit 1. note that if the wrong value is set, the processor will malfunction. 3. the clock is immediately supplied at the new division ratio. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 466 of 1458 rej09b0033-0300 11.6 usage notes note the following when using the usbh and usbf. 1. when the usbh and usbf are not used, it is recommended that uclkcr should be cleared to h'00 to halt the clock. 2. halt the usbh and usbf modules before changing the value of uclkcr. this is done by selecting the "clock stopped" setting with the module stop bit 31 (usbh module stop) and module stop bit 30 (usbf module stop) in stbcr3. 3. uclkcr is initialized only by a power-on reset. in a manual reset, it retains its current set values. 4. when using the usbh/usbf, be sure to set the peripheral clock (p ) to a frequency higher than 13 mhz. 5. when using the usbh, be sure to set the bus clock (b ) to a frequency higher than 32 mhz. 11.7 notes on board design (1) when using an ext ernal crystal resonator place the crystal resonator, capacitors cl1 and cl 2, and damping resistor r close to the extal and xtal pins. to prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to th e resonator, and do not locate a wiring pattern near these components. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 467 of 1458 rej09b0033-0300 note: the values for cl1, cl2, and the damping resistance should be determined after consultation with the crystal manufacturer. xtal extal this lsi r cl2 cl1 avoid crossing signal lines figure 11.2 points for attention when using crystal resonator (2) bypass capacitors insert a laminated ceramic capacitor as a bypass capacitor for each v ss /v cc pair. mount the bypass capacitors to the power supply pins, and use compon ents with a frequency characteristic suitable for the operating frequency of the lsi, as well as a suitable capacitance value. (3) when using a pll oscillator circuit keep the wiring from the pll v cc and v ss connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. connect the extal pin to v cc or v ss q and make the xtal pin open in clock mode 7. the analog power supply system of the pll is sensitive to a noise. therefore the system malfunction may occur by the intervention with other power supply. do not supply the analog power supply with the same resource as the digital power supply of v cc and v cc q. section 11 clock pulse generator (cpg) rev. 3.00 jan. 18, 2008 page 468 of 1458 rej09b0033-0300 vcc(pll2) vss(pll2) vcc(pll1) vss(pll1) avoid crossing signal lines power supply vcc vss figure 11.3 points for attention when using pll oscillator circuit section 12 watchdog timer (wdt) wdts300b_000020030200 rev. 3.00 jan. 18, 2008 page 469 of 1458 rej09b0033-0300 section 12 watchdog timer (wdt) this lsi includes the watchdog timer (wdt). this lsi can be reset by the overflow of the co unter when the value of the counter has not been updated because of a system runaway. the wdt is a single-channel timer that uses a peri pheral clock as an input and counts the clock settling time when clearing softwa re standby mode and temporary standbys, such as frequency changes. it can also be used as an interval timer. 12.1 features the wdt has the following features: ? can be used to ensure the clock settling time: use the wdt to cancel software standby mode and the temporary standbys which occur when the clock frequency is changed. ? can switch between watchdog timer mode and interval timer mode. ? generates internal resets in watchdog timer mode: internal resets occur after counter overflow. ? an interrupt is generated in interval timer mode an interval timer interrupt is generated when the counter overflows. ? choice of eight counter input clocks eight clocks ( 1 to 1/4096) that are obtained by dividing the peripheral clock can be chosen. ? choice of two resets power-on reset and manual reset are available. section 12 watchdog timer (wdt) rev. 3.00 jan. 18, 2008 page 470 of 1458 rej09b0033-0300 figures 12.1 shows a block diagram of the wdt. wtcsr standby control bus interface wtcnt divider clock selector clock standby mode peripheral clock standby cancellation reset control clock selection wdt overflow internal reset request interrupt control interrupt request [legend] wtcsr: wtcnt: watchdog timer control/status register watchdog timer counter figure 12.1 block diagram of wdt section 12 watchdog timer (wdt) rev. 3.00 jan. 18, 2008 page 471 of 1458 rej09b0033-0300 12.2 register descriptions for wdt the wdt has the following two registers. refer to section 37, list of regi sters, for more details on the addresses and states of these registers in each operating mode. ? watchdog timer counter (wtcnt) ? watchdog timer control/status register (wtcsr) 12.2.1 watchdog timer counter (wtcnt) wtcnt is an 8-bit readable/writable register that increments on the selected clock. when an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. the wtcnt counter is not initialized by an internal reset due to the wdt overflow. the wtcnt counter is initialized to h' 00 only by a power-on reset. use a word access to write to the wtcnt counter, with h'5a in the upper byte. use a byte access to read wtcnt. note: wtcnt differs from other registers in that it is more difficult to write to. see section 12.2.3, notes on regist er access, for details. 12.2.2 watchdog timer contro l/status register (wtcsr) wtcsr is an 8-bit readable/writable register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. wtcsr holds its value in an internal reset due to the wdt overflow. wtcsr is initialized to h'00 only by a power-on reset. when used to count the clock settling time for canceling a software standby, it retains its value after counter overflow. use a word access to write to wtcsr, with h'a5 in the upper byte. use a byte access to read wtcsr. note: wtcsr differs from other registers in that it is more difficult to write to. see section 12.2.3, notes on regist er access, for details. section 12 watchdog timer (wdt) rev. 3.00 jan. 18, 2008 page 472 of 1458 rej09b0033-0300 bit bit name initial value r/w description 7 tme 0 r/w timer enable starts and stops timer operation. clear this bit to 0 when using the wdt in software standby mode or when changing the clock frequency. 0: timer disabled: count-up stops and wtcnt value is retained 1: timer enabled 6 wt/it 0 r/w timer mode select selects whether to use the wdt as a watchdog timer or an interval timer. 0: interval timer mode 1: watchdog timer mode note: if wt/it is modified when the wdt is operating, the up-count may not be performed correctly. 5 rsts 0 r/w reset select selects the type of reset when the wtcnt overflows in watchdog timer mode. in interval timer mode, this setting is ignored. 0: power-on reset 1: manual reset 4 wovf 0 r/w watchdog timer overflow indicates that the wtcnt has overflowed in watchdog timer mode. this bit is not set in interval timer mode. 0: no overflow 1: wtcnt has overflowed in watchdog timer mode 3 iovf 0 r/w interval timer overflow indicates that the wtcnt has overflowed in interval timer mode. this bit is not set in watchdog timer mode. 0: no overflow 1: wtcnt has overflowed in interval timer mode section 12 watchdog timer (wdt) rev. 3.00 jan. 18, 2008 page 473 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select the clock to be used for the wtcnt count from the eight types obtainable by dividing the peripheral clock (p ). the overflow period that is shown inside the parenthesis in the table is the value when the peripheral clock (p ) is 15 mhz. 000: p (17 s) 001: p /4 (68 s) 010: p /16 (273 s) 011: p /32 (546 s) 100: p /64 (1.09 ms) 101: p /256 (4.36 ms) 110: p /1024 (17.48 ms) 111: p /4096 (69.91 ms) note: if bits cks2 to cks0 are modified when the wdt is operating, the up-count may not be performed correctly. ensure that these bits are modified only when the wdt is not operating. 12.2.3 notes on register access the watchdog timer counter (wtcnt) and watchdog timer control/status register (wtcsr) are more difficult to write to than other registers. the procedure for writing to these registers is given below. ? writing to wtcnt and wtcsr these registers must be written by a word transf er instruction. they cannot be written by a byte or longword transfer instruction. when writing to wtcnt, set the upper byte to h'5a and transfer the lower byte as the write data, as shown in figure 12.3. when writing to wtcsr, set the upper byte to h'a5 and transfer the lower byte as the write data. this transfer procedure writes the lower byte data to wtcnt or wtcsr. section 12 watchdog timer (wdt) rev. 3.00 jan. 18, 2008 page 474 of 1458 rej09b0033-0300 15 8 7 0 h'5a write data address: h'a415ff84 wtcnt write 15 8 7 0 h'a5 write data address: h'a415ff86 wtcsr write figure 12.2 writing to wtcnt and wtcsr 12.3 wdt operation 12.3.1 canceling software standbys the wdt can be used to cancel software standby mode with an nmi interrupt or external interrupt (irq). the procedure is described below. (the wdt does not run when resets are used for canceling, so keep the resetp pin low until the clock stabilizes.) 1. before transition to software standby mode, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interv al timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2 to cks0 bits in wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. move to software standby mode by executing a sleep instruction to stop the clock. 4. the wdt starts counting by detecti ng the edge change of the nmi signal. 5. when the wdt count overflows, the cpg st arts supplying the clock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 6. since the wdt continues counting from h'00, set the stby bit in stbcr to 0 in the interrupt processing program and this will stop the wdt. when the stby bit remains 1, the lsi again enters software standby mode when the wdt has counted up to h'80. this software standby mode can be canceled by a power-on reset. section 12 watchdog timer (wdt) rev. 3.00 jan. 18, 2008 page 475 of 1458 rej09b0033-0300 12.3.2 changing frequency to change the frequency used by the pll, use the wdt. when changing the frequency only by switching the divider, do not use the wdt. 1. before changing the frequenc y, always clear the tme bit in wtcsr to 0. when the tme bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. set the type of count clock used in the cks2 to cks0 bits in wtcsr and the initial values for the counter in the wtcnt counter. these values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. when the frequency control register (frqcr) is written, the processor stops temporarily. the wdt starts counting. 4. when the wdt count overflows, the cpg re sumes supplying the cl ock and the processor resumes operation. the wovf flag in wtcsr is not set when this happens. 5. the counter stops at the values h'00. 6. before changing wtcnt after the execution of the frequency change instruction, always confirm that the value of wtcn t is h'00 by reading wtcnt. 12.3.3 using watchdog timer mode 1. set the wt/it bit in wtcsr to 1, set the rese t type in the rsts bit, set the type of count clock in the cks2 to cks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in watchdog timer mode. 3. while operating in watchdog timer mode, rewrite the counter periodically to h'00 to prevent the counter from overflowing. 4. when the counter overflows, the wdt sets th e wovf flag in wtcsr to 1 and generates the type of reset specified by the rsts b it. the counter then resumes counting. section 12 watchdog timer (wdt) rev. 3.00 jan. 18, 2008 page 476 of 1458 rej09b0033-0300 12.3.4 using interval timer mode when operating in interval timer mode, interval tim er interrupts are generated at every overflow of the counter. this enables interrupts to be generated at set periods. 1. clear the wt/it bit in wtcsr to 0, set the type of count clock in the cks2 to cks0 bits, and set the initial value of the counter in the wtcnt counter. 2. set the tme bit in wtcsr to 1 to start the count in interval timer mode. 3. when the counter overflows, the wdt sets th e iovf flag in wtcsr to 1 and an interval timer interrupt request is sent to the intc. the counter then resumes counting. section 13 power-down modes lpws300a_000020011000 rev. 3.00 jan. 18, 2008 page 477 of 1458 rej09b0033-0300 section 13 power-down modes this lsi has four types of power-down modes: sleep mode, software standby mode, module standby function, and hardware standby mode. 13.1 features ? supports sleep/software standby/module standby/hardware standby. 13.1.1 power-down modes this lsi has the following power-down modes and function: ? sleep mode ? software standby mode ? module standby function (dsp, cache, tlb, x/y memory, ubc, dmac, h-udi, and on-chip peripheral module) ? hardware standby mode section 13 power-down modes rev. 3.00 jan. 18, 2008 page 478 of 1458 rej09b0033-0300 table 13.1 shows the transition conditions for entering the modes from the program execution state, as well as the cpu and peripheral module states in each mode and the procedures for canceling each mode. table 13.1 states of power-down modes state mode transition conditions cpg cpu cpu reg- ister on-chip memory on-chip periphera l modules external memory canceling procedure sleep mode execute sleep instruction with stby bit in stbcr cleared to 0 runs halts held halts (contents remained) run auto- refreshing ? interrupt ? reset software standby mode execute sleep instruction with stby bit in stbcr set to 1 halts halts held halts (contents remained) halt * self- refreshing ? interrupt (nmi, irq (edge detection), rtc, tmu, pint ? reset module standby function set mstp bit in stbcr to 1 runs runs/ halts held specified module halts (contents remained) specified module halts auto- refreshing ? clear mstp bit to 0 ? power-on reset hardware standby mode set ca pin to low halts halts held held halt * self- refreshing ? power-on reset note: * the rtc operates when the start bit in rcr2 is set to 1. for details, see section 17, realtime clock (rtc). 13.1.2 reset resetting occurs when power is supplied, and when execution is started again from an initialized state. there are two types of reset: a power-on rese t and a manual reset. in a power-on reset, all processing in execution is suspended, all unpro cessed events are canceled, and reset processing starts immediately. on the other hand, processing to retain the contents of external memory is continued in a manual reset. the conditions for generating power-on and manual resets are as follows. section 13 power-down modes rev. 3.00 jan. 18, 2008 page 479 of 1458 rej09b0033-0300 (1) power-on reset 1. driving the resetp pin low. 2. while the wt/it bit in wtcsr is set to 1 and the rsts bit is cleared to 0, the wdt starts counting and continues until it overflows. 3. generation of the h-udi reset (for details on the h-udi reset, refer to section 36, user debugging interface (h-udi)). (2) manual reset 1. driving the resetm pin low. 2. while the wt/it bit in wtcsr and the rsts bit are set to 1, the wdt starts counting and continues until it overflows. 13.2 input/output pins table 13.2 lists the pin configuration related to power-down modes. table 13.2 pin configuration pin name abbreviation i/o description status 1 output status1 status 0 output status0 output operating stat e of the processor. hh: reset hl: sleep mode lh: standby mode ll: normal operation power-on reset input resetp input power-on reset occurs at low-level. manual-reset input resetm input manual reset occurs at low-level. chip active ca input hardware standby mode entered at low-level. section 13 power-down modes rev. 3.00 jan. 18, 2008 page 480 of 1458 rej09b0033-0300 13.3 register descriptions there are following five registers related to power-down modes. refer to section 37, list of registers, for more details on the addresses and states of these register s in each operating mode. ? standby control register (stbcr) ? standby control register 2 (stbcr2) ? standby control register 3 (stbcr3) ? standby control register 4 (stbcr4) ? standby control register 5 (stbcr5) 13.3.1 standby control register (stbcr) stbcr is an 8-bit readable/writable register th at specifies the state of power-down modes. bit bit name initial value r/w description 7 stby 0 r/w standby specifies transition to software standby mode. 0: executing sleep instructi on enters chip into sleep mode 1: executing sleep instructi on enters chip into software standby mode 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 stbxtl 0 r/w standby crystal specifies halt/operation of a cr ystal oscillator in standby mode. 0: crystal oscillator is halted in standby mode 1: crystal oscillator is oper ated continuously in standby mode section 13 power-down modes rev. 3.00 jan. 18, 2008 page 481 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 2 mstp2 0 r/w module stop bit 2 when the mstp2 bit is set to 1, the supply of the clock to the tmu is halted. 0: tmu operates 1: clock supply to tmu halted 1 mstp1 0 r/w module stop bit 1 when the mstp1 bit is set to 1, the supply of the clock to the rtc is halted. 0: rtc operates 1: clock supply to rtc halted 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 13.3.2 standby control register 2 (stbcr2) stbcr2 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. bit bit name initial value r/w description 7 mstp10 0 r/w module stop bit 10 when the mstp10 bit is set to 1, the supply of the clock to the h-udi is halted. 0: h-udi operates 1: clock supply to h-udi halted 6 mstp9 0 r/w module stop bit 9 when the mstp9 bit is set to 1, the supply of the clock to the ubc is halted. 0: ubc operates 1: clock supply to ubc halted section 13 power-down modes rev. 3.00 jan. 18, 2008 page 482 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 mstp8 0 r/w module stop bit 8 when the mstp8 bit is set to 1, the supply of the clock to the dmac is halted. 0: dmac operates 1: clock supply to dmac halted 4 mstp7 0 r/w module stop bit 7 when the mstp7 bit is set to 1, the supply of the clock to the dsp is halted. 0: dsp operates 1: clock supply to dsp halted 3 mstp6 0 r/w module stop bit 6 when the mstp6 bit is set to 1, the supply of the clock to the tlb is halted. 0: tlb operates 1: clock supply to tlb halted 2 mstp5 0 r/w module stop bit 5 when the mstp5 bit is set to 1, the supply of the clock to the cache memory is halted. 0: cache memory operates 1: clock supply to cache memory halted 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 mstp3 0 r/w module stop bit 3 when the mstp3 bit is set to 1, the supply of the clock to the x/y memory is halted. 0: x/y memory operates 1: clock supply to x/y memory halted section 13 power-down modes rev. 3.00 jan. 18, 2008 page 483 of 1458 rej09b0033-0300 13.3.3 standby control register 3 (stbcr3) stbcr3 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. bit bit name initial value r/w description 7 mstp37 0 r/w module stop bit 37 when the mstp37 bit is set to 1, the supply of the clock to the siof1 is halted. 0: siof1 operates 1: clock supply to siof1 halted 6 mstp36 0 r/w module stop bit 36 when the mstp36 bit is set to 1, the supply of the clock to the siof0 is halted. 0: siof0 operates 1: clock supply to siof0 halted 5 mstp35 0 r/w module stop bit 35 when the mstp35 bit is set to 1, the supply of the clock to the cmt is halted. howe ver, count-up operation is continued when the channel 5 is in the operation. 0: cmt operates 1: clock supply to cmt halted 4 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 3 mstp33 0 r/w module stop bit 33 when the mstp33 bit is set to 1, the supply of the clock to the adc is halted. 0: adc operates 1: clock supply to adc halted 2 mstp32 0 r/w module stop bit 32 when the mstp32 bit is set to 1, the supply of the clock to the dac is halted. 0: dac operates 1: clock supply to dac halted section 13 power-down modes rev. 3.00 jan. 18, 2008 page 484 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 mstp31 0 r/w module stop bit 31 when the mstp31 bit is set to 1, the supply of the clock to the usbh is halted. 0: usbh operates 1: clock supply to usbh halted 0 mstp30 0 r/w module stop bit 30 when the mstp30 bit is set to 1, the supply of the clock to the usbf is halted. 0: usbf operates 1: clock supply to usbf halted 13.3.4 standby control register 4 (stbcr4) stbcr4 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 mstp45 0 r/w module stop bit 45 when the mstp45 bit is set to 1, the supply of the clock to the pcc is halted. 0: pcc operates 1: clock supply to pcc halted 4 mstp44 0 r/w module stop bit 44 when the mstp44 bit is set to 1, the supply of the clock to the i 2 c is halted. 0: i 2 c operates 1: clock supply to i 2 c halted section 13 power-down modes rev. 3.00 jan. 18, 2008 page 485 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 mstp43 0 r/w module stop bit 43 when the mstp43 bit is set to 1, the supply of the clock to the mmc is halted. 0: mmc operates 1: clock supply to mmc halted 2 mstp42 0 r/w module stop bit 42 when the mstp42 bit is set to 1, the supply of the clock to the sim is halted. 0: sim operates 1: clock supply to sim halted 1 mstp41 0 r/w module stop bit 41 when the mstp41 bit is set to 1, the supply of the clock to the scif1 is halted. 0: scif1 operates 1: clock supply to scif1 halted 0 mstp40 0 r/w module stop bit 40 when the mstp40 bit is set to 1, the supply of the clock to the scif0 is halted. 0: scif0 operates 1: clock supply to scif0 halted section 13 power-down modes rev. 3.00 jan. 18, 2008 page 486 of 1458 rej09b0033-0300 13.3.5 standby control register 5 (stbcr5) stbcr5 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 mstp56 0 r/w module stop bit 56 when the mstp56 bit is set to 1, the supply of the clock to the sdhi is halted. 0: clock supply to sdhi halted 1: sdhi operates note: on the models not having the sdhi, this bit is reserved and is always read as 0. the write value should always be 0. 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 mstp54 0 r/w module stop bit 54 when the mstp54 bit is set to 1, the supply of the clock to the tpu is halted. 0: tpu operates 1: clock supply to tpu halted 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 13 power-down modes rev. 3.00 jan. 18, 2008 page 487 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 mstp52 0 r/w module stop bit 52 when the mstp52 bit is set to 1, the supply of the clock to the ssl is halted. 0: ssl operates 1: clock supply to ssl halted note: on the models not having the ssl, this bit is reserved. the write value should always be 1. 1 mstp51 0 r/w module stop bit 51 when the mstp51 bit is set to 1, the supply of the clock to the afeif is halted. 0: afeif operates 1: clock supply to afeif halted 0 mstp50 0 r/w module stop bit 50 when the mstp50 bit is set to 1, the supply of the clock to the lcdc is halted. 0: lcdc operates 1: clock supply to lcdc halted section 13 power-down modes rev. 3.00 jan. 18, 2008 page 488 of 1458 rej09b0033-0300 13.4 sleep mode 13.4.1 transition to sleep mode executing the sleep inst ruction when the stby bit in stbcr is 0 causes a transition from the program execution state to sleep mode. although the cpu halts immediat ely after executing the sleep instruction, the contents of the cpu regi sters remain unchanged. the on-chip peripheral modules continue to operate in sleep mode and the clock continues to be output to the ckio pin. in sleep mode the output of the status0 pin and status1 pin go high and low, respectively. 13.4.2 canceling sleep mode sleep mode is canceled by an in terrupt (nmi, irq, irl, pint, and on-chip peripheral module) or reset. interrupts are accepted in sleep mode even wh en the bl bit in sr is 1. if necessary, save spc and ssr to the stack before executing the sleep instruction. (1) canceling with interrupt when an nmi, irq, irl, pint, or on-chip peri pheral module interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. a code indicating the interrupt source is set in intevt and intevt2. (2) canceling with reset sleep mode is canceled by a powe r-on reset or a manual reset. section 13 power-down modes rev. 3.00 jan. 18, 2008 page 489 of 1458 rej09b0033-0300 13.5 software standby mode 13.5.1 transition to software standby mode executing the sleep instruction wh en the stby bit in stbcr is 1 causes a transition from the program execution state to software standby mode. in software standby mode, not only the cpu but also the clock and on-chip peripheral modules halt. the clock output from the ckio pin also halts. the contents of the cpu and cach e registers remain unchanged. so me registers of the on-chip peripheral modules are, however, initialized. refer to section 37, list of registers, for the register states of the on-chip peripheral modules in software standby mo de. the procedure for a transition to software standby mode is as follows. 1. clear the tme bit in the wdt's timer contro l register (wtcsr) to 0 to stop the wdt. 2. clear the wdt's timer counter (wtcnt) to 0 and set the cks2 to cks0 bits in wtcsr to appropriate values to secure the sp ecified oscillation settling time. 3. after the stby bit in stbcr is set to 1, the sleep instruction is executed. 4. software standby mode is entered and the clocks within the chip are halted. the output of the status0 pin and status1 pin go high and low, respectively. 13.5.2 canceling so ftware standby mode software standby mode is can celed by interrupts (nmi, irq (e dge detection), rtc, tmu, and pint) or a reset. (1) canceling with interrupt the on-chip wdt can be used for hot starts. when the chip detects an nmi, irq (edge detection)* 1 , rtc* 1 , tmu* 1 , or pint* 1 interrupt, the clock will be supplied to the entire chip and software standby mode will be canceled after the time set in the wdt's timer control/status register has elapsed. both status1 and status0 pins go low. interrupt exception handling then begins and a code indicating the interrupt source is set in intevt and intevt2. after the branch to the interrupt handling routine, clear the stby bit in stbcr. wdt stops automatically. if the stby bit is not cleared, wdt continues operation and a transition is made to software standby mode* 2 when wtcnt reaches h'80. note that a manual reset is not accepted until the stby bit is cleared. inte rrupts are accepted in software standby mode even when the bl bit in sr is 1. if necessary, save spc and ssr to the stack before executing th e sleep instruction. section 13 power-down modes rev. 3.00 jan. 18, 2008 page 490 of 1458 rej09b0033-0300 immediately after an interrupt is detected, the phase of the clock output of the ckio pin may be unstable, until software st andby mode is canceled. notes: 1. only when the rtc is used, softwa re standby mode can be canceled by irq (edge detection), rtc, tmu, or pint interrupt. 2. cancel this software standby mode by a power-on reset. wtcnt value h'ff h'80 time interrupt request wdt overflow and branch to interrupt handling routine crystal oscillator settling time and pll synchronization time clear the stby bit in stbcr before wtcnt reaches h'80. when he stby bit in stbcr is cleared, wtcnt halts automatically. figure 13.1 canceling standby mode with stby bit in stbcr (2) canceling with reset software standby mode is ca nceled by a reset with the resetp pin and resetm pin. keep the resetp pin and resetm pin low until the clock oscillation settles in clock operating mode to use pll. the internal clock will continue to be output to the ckio pin. section 13 power-down modes rev. 3.00 jan. 18, 2008 page 491 of 1458 rej09b0033-0300 13.6 module standby function 13.6.1 transition to module standby function setting the mstp bits in the standby control register to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. this function can be used to reduce power consumption in normal mode. when changing the setting of an mstp bit to use the module standby function, be sure to halt operation of the module whose clock supply is to be stopped before setting the corresponding mstp bit to 1. in the module standby state, the st ates of the external pins of the on-chip peripheral modules differ depending on the on-chip peripheral module and i/o port settings. register state is as same as in standby mode. when changing the setting of an mstp bit to use the module standby function, be sure to halt operation of the module whose clock supply is to be stopped before setting the corresponding mstp bit to 1. 13.6.2 canceling modul e standby function the module standby function can be canceled by clearing the mstp bits to 0, or by a power-on reset. when canceling the module standby function by cl earing the corresponding mstp bit, be sure to read the relevant mstp bit to confir m that it has been cleared to 0. section 13 power-down modes rev. 3.00 jan. 18, 2008 page 492 of 1458 rej09b0033-0300 13.7 status pin change timing the status1 and status0 pin change timings are shown below. 13.7.1 reset (1) power-on reset ckio status pll setting time 1. reset : hh (status1 = high, status0 = high) 2. normal : ll (status1 = low, status0 = low) 3. bcyc : bus clock cycle notes: * 2 * 2 * 1 0 to 30 bcyc * 3 0 to 5 bcyc normal reset normal * 3 resetp figure 13.2 status output at power-on reset (2) manual reset ckio status 1. : in manual reset, status = hh (reset) after the current bus cycle is completed and then internal reset is initiated. 2. : reset: hh (status1 = high, status0 = high) 3. : normal: ll (status1 = low, status0 = low) 4. : bcyc: bus clock cycle notes * 3 * 3 * 2 0 to 30 bcyc * 4 0bcyc~ normal reset normal * 1, * 4 resetm figure 13.3 status output at manual reset section 13 power-down modes rev. 3.00 jan. 18, 2008 page 493 of 1458 rej09b0033-0300 13.7.2 software standby mode (1) canceling software stan dby mode by an interrupt ckio status wdt count interrupt request oscillation stops wtd overflow 1. standby : lh (status1 = low, status0 = high) 2. normal : ll (status1 = low, status0 = low) notes: * 2 * 2 * 1 normal standby normal figure 13.4 status output when software standby mode is canceled by an interrupt (2) canceling software standb y mode by a power-on reset ckio status 1. if a standby mode is canceled by a power on reset, the wdt stops counting. resetp must be kept low for the pll oscillation stabilization time. 2. reset : hh (status1 = high, status0 = high) 3. standby : lh (status1 = low, status0 = high) 4. normal : ll (status1 = low, status0 = low) 5. bcyc : bus clock cycle notes: undefined * 4 * 4 * 1 * 2 0 to 30 bcyc * 5 0 to 10 bcyc normal * 3 standby reset normal * 5 resetp reset oscillation stops figure 13.5 status output when software standby mode is can celed by a power-on reset section 13 power-down modes rev. 3.00 jan. 18, 2008 page 494 of 1458 rej09b0033-0300 (3) canceling software standby mode by a manual reset ckio status 1. 2. 3. 4. 5. if a standby mode is canceled by a manual reset, the wdt stops counting. resetm must be kept low for the pll oscillation stabilization time. reset : hh (status1 = high, status0 = high) standby : lh (status1 = low, status0 = high) normal : ll (status1 = low, status0 = low) bcyc : bus clock cycle oscillation stops reset notes: * 2 * 4 * 3 normal standby reset * 1 0 to 20 bcyc * 5 * 4 normal resetm figure 13.6 status output when softwa re standby mode is canceled by a manual reset 13.7.3 sleep mode (1) canceling sleep mode by an interrupt ckio status 1. sleep : hl (status1 = high, status0 = low) 2. normal : ll (status1 = low, status0 = low) notes: * 2 * 2 * 1 normal sleep normal interrupt request figure 13.7 status output when slee p mode is canceled by an interrupt section 13 power-down modes rev. 3.00 jan. 18, 2008 page 495 of 1458 rej09b0033-0300 (2) canceling sleep mode by a power-on reset ckio resetp status 1. if pll1 multiplication rate changed by a power-on reset, resetp must be kept low for the oscillation stabilization time. 2. reset : hh (status1 = high, status0 = high) 3. sleep : hl (ststus1= high, status0= low) 4. normal : ll (status1 = low, status0 = low) 5. bcyc : bus clock cycle notes: undefined * 4 * 4 * 1 * 2 0 to 30 bcyc * 5 0 to 10 bcyc normal * 3 sleep reset normal * 5 reset figure 13.8 status output when sleep mode is canceled by a power-on reset (3) canceling sleep mode by a manual reset ckio status 1. resetm must be kept low until statau = reset. 2. reset:hh (status1 = high, status0 = high) 3. sleep:hl(ststus1= high, status0= low) 4. normal:ll (status1 = low, status0 = low) 5. bcyc:bus clock cycle notes: * 4 * 4 * 1 * 2 0 to 30 bcyc * 5 0 to 80 bcyc normal * 3 sleep reset normal * 5 reset resetm figure 13.9 status output when sleep mode is canceled by a manual reset section 13 power-down modes rev. 3.00 jan. 18, 2008 page 496 of 1458 rej09b0033-0300 13.8 hardware standby mode 13.8.1 transition to hardware standby mode this lsi enters hardware standby mode by driving the ca pin low. in hardware standby mode as well as a standby mode entered by the sleep instruction, all modules stop other than the modules that operate using the rtc clock. hardware standby mode differs from standby mode as follows: 1. interrupts and manual reset cannot be accepted. 2. tmu does not operate. 3. rtc operates without power supply to the power supply pins other than that of rtc. if the ca pin goes low, the operation differs according to the cpg status. ? during standby mode hardware standby mode is entered with the clock stopped. interrupts and manual reset cann ot be accepted and tmu halts. ? during wdt operation while the standby mode is canceled by an interrupt after standby mode is canceled and the cpu restarts operating, a transition to hardware standby mode occurs. ? sleep mode after sleep mode is canceled and the cpu restar ts operating, a transition to hardware standby mode occurs. note that the ca pin must be brought low during hardware standby mode. 13.8.2 canceling the hardware standby mode hardware standby mode is canceled by power-on or reset. if the ca pin is pulled high while the resetp signal is low, clock oscillation starts. in this case, resetp must be kept low until clock oscillation has settled. if resetp is then pulled high, the cpu initiates the power-on reset processing. if an interrupt or manual reset is input, correct operation cannot be guaranteed. section 13 power-down modes rev. 3.00 jan. 18, 2008 page 497 of 1458 rej09b0033-0300 13.8.3 hardware standby mode timing figures 13.10 and 13.11 show signal timings in hardware standby mode. since the signal on the ca pin is sampled at the timing of extal_rtc, clock should be input to the extal_rtc pin when hardware standby mode is entered. in hardware standby mode, the ca pin must be kept low. the clock oscillation starts if the ca pin is pulled high after the resetp pin is brought low. ckio ca status normal * 3 reset * 1 0 to 10 bcyc standby * 2 resetp undefined notes: 1. reset : hh (status1 = high, status0 = high) 2. standby : lhlh (status1 = low, status0 = high) 3. normal : ll (status1 = low, status0 = low) 4. bcyc : bus clock cycle figure 13.10 hardware stan dby mode timing (ca is pulled low in normal operation) section 13 power-down modes rev. 3.00 jan. 18, 2008 page 498 of 1458 rej09b0033-0300 ckio ca status reset * 1 0 to 10 bcyc standby * 2 resetp undefined notes: 1. reset : hh (status1 = high, status0 = high) 2. standby : lh(status1 = low, status0 = high) 3. normal : ll (status1 = low, status0 = low) 4. bcyc : bus clock cycle standby normal * 3 wdt opeeration figure 13.11 hardware standby mode timing (ca is pulled low while wdt operates after the standby mode is canceled) ca status power supply other than vcc_rtc and vccq_rtc resetp rtc protection normal * 3 standby* 2 undefined reset * 1 normal * 3 specification: checking the standby state of the status pin 0 to 10 bcyc * 4 0 to 30 bcyc notes: * 1 reset: hh (status1 = high, status0 = high) * 2 standby: lh (status1 = low, status0 = high) * 3 normal operation: ll (status1 = low, status0 = low) * 4 bcyc: bus clock cycle figure 13.12 timing when power of pins other than v cc _rtc and v cc q_rtc is off section 14 timer unit (tmu) timtmu0a_000020011000 rev. 3.00 jan. 18, 2008 page 499 of 1458 rej09b0033-0300 section 14 timer unit (tmu) this lsi includes a three-ch annel 32-bit timer unit (tmu). 14.1 features ? each channel is provided with an auto-reload 32-bit down counter ? all channels are provided with 32-bit constant registers and 32-bit down counters that can be read or written to at any time ? all channels generate interrupt requests when the 32-bit down counter underflows (h'00000000 h'ffffffff) ? allows selection among five counter input clocks: p /4, p /16, p /64, p /256, and rtc output clock (16 khz) ? allows channels operate when this lsi is in standby mode even when this lsi is in standby mode, channe ls can operate when the rtc output clock is used as a counter input clock. section 14 timer unit (tmu) rev. 3.00 jan. 18, 2008 page 500 of 1458 rej09b0033-0300 figure 14.1 shows a block diagram of the tmu. tstr: tcr: [legend] timer start register timer control register tcnt: tcor: timer counter timer constant register tmu_suni, tuni0, tuni1, and tuni2: interrupt requests prescaler tstr tcr_0 tcnt_0 peripheral bus internal bus tcor_0 tcr_1 tcnt_1 tcor_1 counter controller p tuni0 tmu_suni rtc output clock bus interface ch. 0 interrupt controller interrupt controller interrupt controller counter controller counter controller tuni1 tuni2 tcr_2 tcnt_2 tcor_2 tmu ch. 1 ch. 2 clock controller figure 14.1 block diagram of tmu section 14 timer unit (tmu) rev. 3.00 jan. 18, 2008 page 501 of 1458 rej09b0033-0300 14.2 register descriptions the tmu has the following registers. refer to section 37, list of registers, for more details on the addresses and states of these registers in each operating mode. notation for the cmt registers takes the form xxx_n, where xxx including the register name and n indicating the channel number. for example, tcor_0 deno tes the tcor for channel 0. (1) common ? timer start register (tstr) (2) channel 0 ? timer constant register_0 (tcor_0) ? timer counter_0 (tcnt_0) ? timer control register_0 (tcr_0) (3) channel 1 ? timer constant register_1 (tcor_1) ? timer counter_1 (tcnt_1) ? timer control register_1 (tcr_1) (4) channel 2 ? timer constant register_2 (tcor_2) ? timer counter_2 (tcnt_2) ? timer control register_2 (tcr_2) section 14 timer unit (tmu) rev. 3.00 jan. 18, 2008 page 502 of 1458 rej09b0033-0300 14.2.1 timer start register (tstr) tstr is an 8-bit readable/writable register th at selects whether to operate or halt the timer counters (tcnt). tstr is initialized to h'00 at a power-on reset, manual reset, or in module stop mode. it is retained in sleep mode and standby mode. bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 str2 0 r/w counter start 2 selects whether to operate or halt timer counter 2 (tcnt_2). 0: tcnt_2 count halted 1: tcnt_2 counts 1 str1 0 r/w counter start 1 selects whether to operate or halt timer counter 1 (tcnt_1). 0: tcnt_1 count halted 1: tcnt_1 counts 0 str0 0 r/w counter start 0 selects whether to operate or halt timer counter 0 (tcnt_0). 0: tcnt_0 count halted 1: tcnt_0 counts section 14 timer unit (tmu) rev. 3.00 jan. 18, 2008 page 503 of 1458 rej09b0033-0300 14.2.2 timer control registers (tcr) tcr are 16-bit readable/writable registers that c ontrol the timer counters (tcnt) and interrupts. tcr control the issuance of interrupts when the flag indicating timer counter (tcnt) underflow has been set to 1, and also carry out counter clock selection. tcr are initialized to h'0000 at a power-on reset or manual reset. they are retained in standby or sleep mode. bit bit name initial value r/w description 15 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 unf 0 r/(w) * underflow flag status flag that indicates occurrence of a tcnt underflow. 0: tcnt has not underflowed [clearing condition] 0 is written to unf 1: tcnt has underflowed [setting condition] tcnt underflows 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 unie 0 r/w underflow interrupt control controls enabling of interrupt generation when the status flag (unf) indicating tcnt underflow has been set to 1. 0: interrupt due to unf (tuni) is disabled 1: interrupt due to unf (tuni) is enabled section 14 timer unit (tmu) rev. 3.00 jan. 18, 2008 page 504 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4, 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w timer prescaler 2 to 0 select the tcnt count clock. 000: count on p /4 001: count on p /16 010: count on p /64 011: count on p /256 101: count on rtc output clock (16 khz) others are setting prohibited. note: * only 0 can be written to clear the flag. 14.2.3 timer constant registers (tcor) tcor set the value to be set in tcnt when tcnt underflows. tcor are 32-bit readable/writable registers. tcor are initialized to h'ffffffff at a power-on reset or manual reset. they are retained in standby or sleep mode. 14.2.4 timer counters (tcnt) tcnt count down upon input of a clock. the clock input is selected using the tpsc2 to tpsc0 bits in the timer control register (tcr). when a tcnt count-down results in an underflow (h'00000000 h'ffffffff), the underflow flag (unf) in the timer control register (tcr) of the relevant channel is set. the tcor value is simultaneously set in tcnt itself and the count-down continues from that value. tcnt are initialized to h'ffffffff at a power-on reset or manual reset. they are retained in standby or sleep mode. section 14 timer unit (tmu) rev. 3.00 jan. 18, 2008 page 505 of 1458 rej09b0033-0300 14.3 operation each of the three channels has a 32-bit timer counter (tcnt) and a 32-bit timer constant register (tcor). tcnt counts down. the auto-reload function enables synchronized counting. 14.3.1 counter operation when the str0 to str2 bits in the timer start register (tstr) are set to 1, the corresponding timer counter (tcnt) starts counting. when tcnt underflows, the unf flag in the corresponding timer co ntrol register (tcr) is set. at this time, if the unie bit in tcr is 1, an interrupt request is sent to the cpu. also at this time, the value is copied from tcor to tcnt and the down-count operation is continued. (1) count operation setting procedure an example of the procedure for setting the count operation is shown in figure 14.2. select operation select counter clock set interrupt generation set timer constant register initialize timer counter start counting (1) (2) (3) (4) (5) note: when an interrupt has been generated, clear the flag in the interrupt handler that caused it. if interrupts are enabled without clearing the flag, another interrupt will be generated. (1) select the counter clock with the bits tpsc2 to tpsc0 in the timer control register (tcr). (2) use the unie bit in tcr to set whether to generate an interrupt when tcnt underflows. (3) set a value in the timer constant register (tcor) (the cycle is the set value plus 1). (4) set the initial value in the timer counter (tcnt). (5) set the str bit in the timer start register (tstr) to 1 to start counting. figure 14.2 setting count operation section 14 timer unit (tmu) rev. 3.00 jan. 18, 2008 page 506 of 1458 rej09b0033-0300 (2) auto-reload count operation figure 14.3 shows the tcnt auto-reload operation. tcnt value tcor h'00000000 str0 to str2 unf tcor value set to tcnt during underflow time figure 14.3 auto-r eload count operation section 14 timer unit (tmu) rev. 3.00 jan. 18, 2008 page 507 of 1458 rej09b0033-0300 (3) tcnt count timing 1. internal clock set the bits tpsc2 to tpsc0 in tcr to select one of the four internal clocks created by dividing a peripheral module clock (p /4, p /16, p /64, p /256). figure 14.4 shows the timing. p divided clock tcnt input clock tcnt n + 1 n n ? 1 figure 14.4 count timing when internal clock is operating 2. internal rtc clock set the bits tpsc2 to tpsc0 in tcr to select the rtc output clock as a clock for timer. figure 14.5 shows the timing. tcnt input clock n n+1 n-1 rtc output clock tcnt figure 14.5 count timing when rtc clock is operating section 14 timer unit (tmu) rev. 3.00 jan. 18, 2008 page 508 of 1458 rej09b0033-0300 14.4 interrupts there is one source of tmu interrupts: underflow interrupts (tuni). 14.4.1 status fl ag set timing the unf bit is set to 1 when tcnt underflows. figure 14.6 shows the timing. p tcnt underflow signal unf tuni (tcor value) h'00000000 figure 14.6 unf set timing 14.4.2 status flag clear timing the status flag can be cleared by writing 0 from the cpu. figure 14.7 shows the timing. p peripheral address bus unf, icpf tcr address t1 t2 tcr write cycle t3 figure 14.7 status flag clear timing section 14 timer unit (tmu) rev. 3.00 jan. 18, 2008 page 509 of 1458 rej09b0033-0300 14.4.3 interrupt sou rces and priorities the tmu generates underflow interrupts for each channel. when the interrupt request flag and interrupt enable bit are both set to 1, the interrupt is requested. codes are set in the interrupt event register (intevt, intevt2) for these interrupts and interrupt processing must be executed according to the codes. the relative priorities between channels can be ch anged using the interrupt controller. for details, refer to section 7, exception handling, and section 8, interrupt controller (intc). table 14.1 lists tmu interrupt sources. table 14.1 tmu interrupt sources channel interrupt source description priority 0 tuni0 underflow interrupt 0 high 1 tuni1 underflow interrupt 1 2 tuni2 underflow interrupt 2 low software standby mode can be cancelled by tsu_su ni which is or of an underflow interrupt for each tmu channel. (it is available when the rtc output clock is selected as a counter input clock.) tmu_suni is processed as an interrupt which differs from an underflow interrupt for each channel by the interrupt controller (intc). therefore, an underflow interrupt for each channel and tmu_suni should be used differently. when canceling software standby mode, set the bits 11 to 8 in interrupt priority register d (iprd) of intc to any value and bits 15 to 4 in interrupt priority register a (ipra) of intc to h'000 so that only the tmu_suni is accepted. in the tm u_suni interrupt routin e, clear both the under flow flag (unf) in the timer control register (tcr) and the tmu_suni interrupt request bit (tmu_sunir) in the interrupt request register 0 of intc. in the normal operating state, set the bits 11 to 8 in iprd to h'0 and bits 15 to 4 in ipra to any value so that an underflow interrupt can be accepte d for each channel. for details, see section 8, interrupt controller (intc). section 14 timer unit (tmu) rev. 3.00 jan. 18, 2008 page 510 of 1458 rej09b0033-0300 14.5 usage notes 14.5.1 writing to registers synchronization processing is not performed for timer counting during register writes. when writing to registers, always clear the appropriate start bits for th e channel (str2 to str0) in the timer start register (tstr) to halt timer counting. 14.5.2 reading registers synchronization processing is performed for timer counting during register reads. when timer counting and register read proce ssing are performed simultaneous ly, the register value before tcnt counting down with synchronization processing is read. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 511 of 1458 rej09b0033-0300 section 15 16-bit timer pulse unit (tpu) this lsi has an on-chip 16-bit timer pulse unit (t pu) that comprises four 16-bit timer channels. 15.1 features ? maximum 4-pulse output ? a total of 16 timer general registers (tgra to tgrd 4 ch.) are provided (four each for channels). tgra can be set as an output compare register. ? tgrb, tgrc, and tgrd for each channel can also be used as timer counter clearing registers. tgrc and tgrd can also be used as buffer registers. ? selection of four counter input clocks for channels 0 and 1, and of six counter input clocks for channels 2 and 3. ? the following operations can be set for each channel: ? waveform output at compare match: selection of 0, 1, or toggle output ? counter clear operation: counter cl earing possible by compare match ? pwm mode: any pwm output duty can be set maximum of 4-phase pwm output possible ? buffer operation settable for each channel ? automatic rewriting of output compare register possible ? phase counting mode settable independently for each of channels 2, and 3 ? two-phase encoder pulse up/down-count possible ? an interrupt request for each channel ? for channels 0 and 1, compare match interrupts and overflow interrupts can be requested independently ? for channels 2, and 3, compare match interrupts, overflow interrupts, and underflow interrupts can be requested independently table 15.1 lists the functions of the tpu. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 512 of 1458 rej09b0033-0300 table 15.1 tpu functions item channel 0 channel 1 channel 2 channel 3 count clock p /1 p /4 p /16 p /64 ? ? p /1 p /4 p /16 p /64 ? ? p /1 p /4 p /16 p /64 tpu_ti2a tpu_ti2b p /1 p /4 p /16 p /64 tpu_ti3a tpu_ti3b general registers tgr0a tgr0b tgr1a tgr1b tgr2a tgr2b tgr3a tgr3b general registers/ buffer registers tgr0c tgr0d tgr1c tgr1d tgr2c tgr2d tgr3c tgr3d output pins tpu_to0 tpu_to1 tpu_to2 tpu_to3 counter clear function tgr compare match tgr compare match tgr compare match tgr compare match compare 0 output match 1 output output toggle output pwm mode phase counting mode ? ? buffer operation interrupt sources 5 sources ? compare match ? overflow 5 sources ? compare match ? overflow 6 sources ? compare match ? overflow ? underflow 6 sources ? compare match ? overflow ? underflow [legend] : possible ? : not possible note: tpu_ti2b and tpu_ti3b are used as count clocks only in phase counting mode. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 513 of 1458 rej09b0033-0300 figure 15.1 shows a block diagram of the tpu. divider clock selection edge selection comparator buffer counter up output control channel 0 channel 2 channel 1 same as channel 0 channel 3 same as channel 2 note 1 clear tgra p tpu_ti2a tpu_ti2b tpu_ti3a tpu_ti3b tpu_to0 tpu_to2 tpu_to1 tpu_to3 p /1 p /4 p /16 p /64 tgrb tgrc tgrd selecter clock selection edge selection comparator buffer phase comparison counter up output control note 1 note 1: output disabled initial value 0, 1 compare match 0, 1, toggle clear down tgra tgrb tgrc tgrd selector selector figure 15.1 block diagram of tpu section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 514 of 1458 rej09b0033-0300 15.2 input/output pins table 15.2 summarizes the tpu related external pins. table 15.2 tpu pin configurations channel name pin name i/o function 0 tpu compare match output 0 tpu_to0 output tgr0a output compare output/pwm output pin 1 tpu compare match output 1 tpu_to1 output tgr1a output compare output/pwm output pin 2 tpu compare match output 2a tpu_to2 output tgr2a output compare output/pwm output pin tpu clock input 2a tpu_ti2a input external clock channel 2a input pin /channel 2 counting mode a phase input tpu clock input 2b tpu_ti2b input channel 2 counting mode b phase input 3 tpu compare match output 3a tpu_to3 output tgr3a output compare output/pwm output pin tpu clock input 3a tpu_ti3a input external clock channel 3a input pin /channel 3 counting mode a phase input tpu clock input 3b tpu_ti3b input channel 3 counting mode b phase input section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 515 of 1458 rej09b0033-0300 15.3 register descriptions the tpu has the following registers. refer to section 37, list of registers, for more details on the addresses and states of these re gisters in each operating mode. channel 0: ? timer control register_0 (tcr_0) ? timer mode register_0 (tmdr_0) ? timer i/o control register_0 (tior_0) ? timer interrupt enable register_0 (tier_0) ? timer status register_0 (tsr_0) ? timer counter_0 (tcnt_0) ? timer general register a_0 (tgra_0) ? timer general register b_0 (tgrb_0) ? timer general register c_0 (tgrc_0) ? timer general register d_0 (tgrd_0) channel 1: ? timer control register_1 (tcr_1) ? timer mode register_1 (tmdr_1) ? timer i/o control register_1 (tior_1) ? timer interrupt enable register_1 (tier_1) ? timer status register_1 (tsr_1) ? timer counter_1 (tcnt_1) ? timer general register a_1 (tgra_1) ? timer general register b_1 (tgrb_1) ? timer general register c_1 (tgrc_1) ? timer general register d_1 (tgrd_1) channel 2: ? timer control register_2 (tcr_2) ? timer mode register_2 (tmdr_2) ? timer i/o control register_2 (tior_2) ? timer interrupt enable register_2 (tier_2) ? timer status register_2 (tsr_2) section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 516 of 1458 rej09b0033-0300 ? timer counter_2 (tcnt_2) ? timer general register a_2 (tgra_2) ? timer general register b_2 (tgrb_2) ? timer general register c_2 (tgrc_2) ? timer general register d_2 (tgrd_2) channel 3: ? timer control register_3 (tcr_3) ? timer mode register_3 (tmdr_3) ? timer i/o control register_3 (tior_3) ? timer interrupt enable register_3 (tier_3) ? timer status register_3 (tsr_3) ? timer counter_3 (tcnt_3) ? timer general register a_3 (tgra_3) ? timer general register b_3 (tgrb_3) ? timer general register c_3 (tgrc_3) ? timer general register d_3 (tgrd_3) ? timer start register (tstr) 15.3.1 timer control registers (tcr) the tcr registers are 16-bit registers that cont rol the tcnt channels. the tpu has four tcr registers, one for each of channels 0 to 3. the t cr registers are initialized to h'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby. tcr register settings should be made only when tcnt operation is stopped. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 517 of 1458 rej09b0033-0300 bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear 2, 1, and 0 these bits select the tcnt counter clearing source. 000: tcnt clearing disabled 001: tcnt cleared by tgra compare match 010: tcnt cleared by tgrb compare match 011: reserved (setting prohibited) 100: tcnt clearing disabled 101: tcnt cleared by tgrc compare match 110: tcnt cleared by tgrd compare match 111: reserved (setting prohibited) 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 1 and 0 these bits select the input cl ock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. /4 both edges = /2 rising edge). if phase counting mode is used this setting is ignored. 00: count at rising edge 01: count at falling edge 1x: count at both edges * [legend] x: don't care note: * if p /1 is selected for the input clock, operation is disabled. 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w time prescaler 2, 1, and 0 these bits select the tcnt c ounter clock. the clock source can be selected independently for each channel. table 15.3 shows the clock sources that can be set for each channel. for more in formati on on count clock selection, see table 15.4. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 518 of 1458 rej09b0033-0300 table 15.3 tpu clock sources internal clock external clock channel p /1 p /4 p /16 p /64 tpu_ti2a tpu_ti3a 0 1 2 3 [legend] : setting blank : no setting table 15.4 tpsc2 to tpsc0 (1) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 0 internal clock: counts on p /1 (initial value) 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 * * reserved (setting prohibited) table 15.4 tpsc2 to tpsc0 (2) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 1 0 0 0 internal clock: counts on p /1 (initial value) 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 * * reserved (setting prohibited) section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 519 of 1458 rej09b0033-0300 table 15.4 tpsc2 to tpsc0 (3) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 2 0 0 0 internal clock: counts on p /1 (initial value) 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 0 0 external clock: counts on tpu_ti2a pin input 1 reserved (setting prohibited) 1 * table 15.4 tpsc2 to tpsc0 (4) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 3 0 0 0 internal clock: counts on p /1 (initial value) 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 0 0 external clock: counts on tpu_ti3a pin input 1 reserved (setting prohibited) 1 * note: * don't care section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 520 of 1458 rej09b0033-0300 15.3.2 timer mode registers (tmdr) the tmdr registers are 16-bit readable/writable regi sters that are used to set the operating mode for each channel. the tpu has four tmdr regist ers, one for each channe l. the tmdr registers are initialized to h'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby. tmdr register settings should be made only when tcnt operation is stopped. bit bit name initial value r/w description 15 to 7 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 6 bfwt 0 r/w buffer write timing specifies tgra and tgrb update timing when tgrc and tgrd are used as a compare match buffer. when tgrc and tgrd are not used as a com pare match buffer register, this bit does not function. 0: tgra and tgrb are rewritt en at compare match of each register. 1: tgra and tgrb are rewritten in counter clearing. 5 bfb 0 r/w buffer operation b specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. 0: tgrb operates normally 1: tgrb and tgrd used together for buffer operation * 4 bfa 0 r/w buffer operation a specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. 0: tgra operates normally 1: tgra and tgrc used together for buffer operation 3 ? 0 r reserved this bit is always read as 0 and cannot be modified. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 521 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 1 0 md2 md1 md0 0 0 0 r/w r/w r/w modes 2 to 0 these bits are used to set the timer operating mode. 000: normal operation 001: reserved (setting prohibited) 010: pwm mode 011: reserved (setting prohibited) 100: phase counting mode 1 101: phase counting mode 2 110: phase counting mode 3 111: phase counting mode 4 note: * operation when setting (bfwt, bfb, bfa) = (1, 1, 0) is the same as when setting (bfwt, bfb, bfa) = (1, 0, 1). however, when the bfb bit is set to 1 (tgrb and tgrd used together for buffer operation), the setting of (bfwt, bfb, bfa) = (1, 1, 1) should be made. in this case, the value set in tgra should also be set in tgrc because tgra and tgrc are also used together for buffer operation. 15.3.3 timer i/o control registers (tior) the tior registers are 16-bit registers that control the tpu_to pin. the tpu has four tior registers, one for each channel. the tior registers are initialized to h'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby. tior register settings should be made only when tcnt operation is halted. care is required since tior is affected by the tmdr setting. if the counting operation is halted, the initial value set by this register is output from the tpu_to pin. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 522 of 1458 rej09b0033-0300 bit bit name initial value r/w description 15 to 3 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 2 1 0 ioa2 ioa1 ioa0 0 0 0 r/w r/w r/w i/o control a2 to a0 bits ioa3 to ioa0 specify t he functions of tgra and the tpu_to pin. for details, see table 15.5. table 15.5 ioa2 to ioa0 bit 2 bit 1 bit 0 channels ioa2 ioa1 ioa0 description 0 always 0 output (initial value) 0 1 0 output at tgra compare match * 0 1 output at tgra compare match 0 1 1 initial output is 0 output for tpu_to pin toggle output tgra at compare match * 0 always 1 output 0 1 0 output at tgra compare match 0 1 output at tgra compare match * 0 to 3 1 1 1 initial output is 1 output for tpu_to pin toggle output at tgra compare match * note: * this setting is invalid in pwm mode. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 523 of 1458 rej09b0033-0300 15.3.4 timer interrupt en able registers (tier) the tier registers are 16-bit registers that control enabling or disabling of interrupt requests for each channel. the tpu has four ti er registers, one for each channel. the tier registers are initialized to h'0000 by a reset, but not initialized in standby mode, sleep mode or module standby. bit bit name initial value r/w description 15 to 6 ? 0 r reserved these bits are always read as 0 and cannot be modified. 5 tc1eu 0 r/w underflow interrupt enable enables or disables interrupt requests by the tcfu bit when the tcfu bit in tsr is set to 1 in phase counting mode of channels 2, and 3 (tcnt underflow). in channels 0 and 1, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: interrupt requests by tcfu disabled 1: interrupt requests by tcfu enabled 4 tc1ev 0 r/w overflow interrupt enable enables or disables interrupt requests by the tcfv bit when the tcfv bit in tsr is set to 1 (tcnt overflow). 0: interrupt requests by tcfv disabled 1: interrupt requests by tcfv enabled 3 tg1ed 0 r/w tgr interrupt enable d enables or disables interrupt requests by the tgfd bit when the tgfd bit in tsr is set to (tcnt and tgrd compare match). 0: interrupt requests by tgfd disabled 1: interrupt requests by tgfd enabled 2 tg1ec 0 r/w tgr interrupt enable c enables or disables interrupt requests by the tgfc bit when the tgfc bit in tsr is set to 1 (tcnt and tgrc compare match). 0: interrupt requests by tgfc disabled 1: interrupt requests by tgfc enabled section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 524 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 tg1eb 0 r/w tgr interrupt enable b enables or disables interrupt requests by the tgfb bit when the tgfb bit in tsr is set to 1 (tcnt and tgrb compare match). 0: interrupt requests by tgfb disabled 1: interrupt requests by tgfb enabled 0 tg1ea 0 r/w tgr interrupt enable a enables or disables interrupt requests by the tgfa bit when the tgfa bit in tsr is set to 1 (tcnt and tgra compare match). 0: interrupt requests by tgfa disabled 1: interrupt requests by tgfa enabled 15.3.5 timer status registers (tsr) the tsr registers are 16-bit registers that indicat e the status of each channel. the tpu has four tsr registers, one for each channel. the tsr registers are initialized to h'0000 by a reset, but not initialized in standby mode, sleep mode or module standby mode. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 7 tcfd 0 r count direction flag status flag that shows the dire ction in which tcnt counts in phase counting mode of channels 2, and 3. in channels 0 and 1, bit 7 is reserved. it is always read as 0 and cannot be modified. 0: tcnt counts down 1: tcnt counts up 6 ? 0 r reserved this bit is always read as 0 and cannot be modified. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 525 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 tcfu 0 r/(w) * underflow flag status flag that indicates that tcnt underflow has occurred when channels 2, and 3 are set to phase counting mode. in channels 0 and 1, bit 5 is reserved. it is always read as 0 and cannot be modified. [clearing condition] (initial value) when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) 4 tcfv 0 r/(w) * overflow flag status flag that indicates that tcnt overflow has occurred. [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000) 3 tgfd 0 r/(w) * compare flag d status flag that indicates t he occurrence of tgrd compare match. [clearing conditions] when 0 is written to tgfd after reading tgfd = 1 [setting conditions] when tcnt = tgrd 2 tgfc 0 r/(w) * compare flag c status flag that indicates t he occurrence of tgrc compare match. [clearing conditions] when 0 is written to tgfc after reading tgfc = 1 [setting conditions] when tcnt = tgrc section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 526 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 tgfb 0 r/(w) * compare flag b status flag that indicates t he occurrence of tgrb compare match. [clearing conditions] when 0 is written to tgfb after reading tgfb = 1 [setting conditions] when tcnt = tgrb 0 tgfa 0 r/(w) * output compare flag a status flag that indicates t he occurrence of tgra compare match. [clearing conditions] when 0 is written to tgfa after reading tgfa = 1 [setting conditions] when tcnt = tgra note: * only 0 can be written, to clear the flag. 15.3.6 timer counters (tcnt) the tcnt registers are 16-bit r eadable/writable counters. the tpu has four tcnt counters, one for each channel. the tcnt counters are initialized to h'0000 by a reset. the tcnt counters are not initialized in standby mode, sleep mode, or module standby. 15.3.7 timer general registers (tgr) the tgr registers are 16-bit regist ers. the tpu has 16 tgr registers, four each for channels 0 and 3. tgrc and tgrd can also be designated for operation as buffer registers*. the tgr registers are initialized to h'ffff by a reset. th ese registers are not initia lized in standby mode, sleep mode, or module standby. note: * tgr buffer register combina tions are tgra?tg rc and tgrb?tgrd. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 527 of 1458 rej09b0033-0300 15.3.8 timer start register (tstr) tstr is a 16-bit readable/writable register that se lects tcnt operation/stoppage for channels 0 to 3. tstr is initialized to h'0000 by a reset, but not initialized in standby mode, sleep mode, or module standby. bit bit name initial value r/w description 15 to 4 ? all 0 r reserved these bits are always read as 0 and cannot be modified. 3 2 1 0 cst3 cst2 cst1 cst0 0 0 0 0 r/w r/w r/w r/w counter start 3 to 0 these bits select operat ion or stoppage for tcnt. 0: tcntn count oper ation is stopped) 1: tcntn performs count operation n=3 to 0 section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 528 of 1458 rej09b0033-0300 15.4 operation 15.4.1 overview operation in each mode is outlined below. (1) normal operation each channel has a tcnt and tgr register. tcnt performs up-counting, an d is also capable of free-running operation, synchronous counting, and external event counting. (2) buffer operation when a compare match occurs, the value in the buffer register for the relevant channel is transferred to tgr. for update timing from a buffer register, rewri ting on compare match occurrence or on counter clearing can be selected. (3) pwm mode in this mode, a pwm waveform is output. the output level can be set by means of tior. a pwm waveform with a duty of between 0% and 100% can be output, according to the setting of each tgr register. (4) phase counting mode in this mode, tcnt is incremen ted or decremented by detecting the phases of two clocks input from the external clock input pins (tpu_ti2a and tpu_ti2b, or tpu_ti3a and tpu_ti3b) in channels 2, and 3. when phase counting mode is set, the corresponding ti pin functions as the clock pin, and tcnt performs up/down-counting. this can be used for two-phase encoder pulse input. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 529 of 1458 rej09b0033-0300 15.4.2 basic functions (1) counter operation when one of bits cst0 to cst3 is set to 1 in tstr, the tcnt counter for the corresponding channel starts counting. tcnt can operate as a free-running counte r, periodic counter, and so on. (a) example of count opera tion setting procedure figure 15.2 shows an example of the count operation setting procedure. select counter clock operation selection select counter clearing source periodic counter set period start count section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 530 of 1458 rej09b0033-0300 (b) free-running count operation and periodic count operation immediately after a reset, the tpu's tcnt counte rs are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up-count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. after overflow, tcnt starts counting up again from h'0000. figure 15.3 illustrates fre e-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 15.3 free-running counter operation when compare match is selected as the tcnt cl earing source, the tcnt co unter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr2 to cclr0 in tcr. after the settings have been made, tcnt starts up-count operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. after a compare match, tcnt starts counting up again from h'0000. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 531 of 1458 rej09b0033-0300 figure 15.4 illustrates periodic counter operation. tcnt value tgr h'0000 cst bit tgfa time counter cleared by tgra compare match flag cleared by software figure 15.4 periodic counter operation section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 532 of 1458 rej09b0033-0300 (2) waveform output by compare match the tpu can perform 0, 1, or toggle output from the corresponding output pin (tpu_to pin) using tgra compare match. (a) example of setting procedure for waveform output by compare match figure 15.5 shows an example of the setting procedure for waveform output by compare match. select waveform output mode output selection set output timing start count section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 533 of 1458 rej09b0033-0300 (b) examples of waveform output operation figure 15.6 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, and settings have been made so that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. tcnt value h'ffff h'0000 tpu_to pin (1 output) tpu_to pin (0 output) time tgra no change no change no change no change figure 15.6 example of 0 output/1 output operation figure 15.7 shows an example of toggle output. in this example tcnt has been designated as a periodic counter (with counter clearing performed by compare match b), and settings have been made so that output is toggled by compare match a. tcnt value h'ffff h'0000 tpu_to pin time tgrb tgra toggle output counter cleared by tgrb compare match figure 15.7 example of toggle output operation section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 534 of 1458 rej09b0033-0300 15.4.3 buffer operation buffer operation, enables tgrc and tgrd to be used as buffer registers. table 15.6 shows the register combin ations used in buffer operation. table 15.6 register combinations in buffer operation timer general register buffer register tgra tgrc tgrb tgrd when a compare match occurs, the value in the bu ffer register for the corresponding channel is transferred to the timer general register. for update timing from a buffer register, rewriting on compare match occurrence or on c ounter cleaning can be selected. this operation is illustrated in figure 15.8. buffer register timer general register tcnt comparator compare match signal counter cleaning signal bfwt bit figure 15.8 compare match buffer operation section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 535 of 1458 rej09b0033-0300 (1) example of buffer operation setting procedure figure 15.9 shows an example of the buffer operation setting procedure. set buffer operation buffer operation set rewriting timing start count section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 536 of 1458 rej09b0033-0300 tcnt value tgrb h'0000 tgrc time tgra n (a) n (tgrb+1) tpu_to pin n (a) n (b) n (tgrb+1) n (tgrb+1) n (b) tgra n (b) n (a) figure 15.10 example of buffer operation 15.4.4 pwm modes in pwm mode, pwm waveforms are output from the output pins. 0, or 1, output can be selected as the output level in response to compare match of each tgra. designating tgrb compare match as the counter clear ing source enables the period to be set in that register. all channels can be designated for pwm mode independently. pwm output is generated from the tpu_to pin using tgrb as the period register and tgra as duty registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a period register compare matc h, the output value of each pin is the initial value set in tior. set tior so that the initial output and an output value by compare match are different. if the same levels or toggle outputs are selected, operation is disabled. conditions of duty 0% and 100% are shown below. ? duty 0%: the set value of the duty register (tgra) is tgrb + 1 for the period register(tgrb). ? duty 100%: the set value of the duty register (tgra) is 0. in pwm mode 1, a maximum 4-phase pwm output is possible. section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 537 of 1458 rej09b0033-0300 (1) example of pwm mode setting procedure figure 15.11 shows an example of the pwm mode setting procedure. select counter clock pwm mode select counter clearing source select waveform output level section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 538 of 1458 rej09b0033-0300 (2) examples of pwm mode operation figure 15.12 shows an example of pwm mode operation. in this example, tgrb compare match is set as the tcnt clearing source, 0 is set for the tgra initial output value and output value, and 1 is set as the tgra output value. in this case, the value set in tgrb is used as the period, and the value set in tgra as the duty. tcnt value tgrb h'0000 tpu_to pin time tgra counter cleared by tgrb compare match figure 15.12 example of pwm mode operation (1) figure 15.13 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt tgra=1 tgra=2 tgra=3 rewrite timing for tgra period: tgrb=2 0 2 1 20 tgra=0 figure 15.13 examples of pwm mode operation (2) section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 539 of 1458 rej09b0033-0300 15.4.5 phase counting mode in phase counting mode, the phase difference betw een two external clock inputs is detected and tcnt is incremented/decremented accordingly. th is mode can be set for channels 2, and 3. when phase counting mode is set, an external cl ock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc2 to tpsc0 and bits ckeg1 and ckeg0 in tcr. however, the functions of bits cclr1 and cclr0 in tcr, and of tior, tier, and tgr are valid, and compare match and interrupt functions can be used. the previous set value (initial output value set before the timer was started in phase counting mode) is output from the tpu_to pin in tior. when overflow occurs while tcnt is counting up, the tcfv flag in tsr is set; when underflow occurs while tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag pr ovides an indication of whether tcnt is counting up or down. table 15.7 shows the correspondence between external clock pins and channels. table 15.7 phase counting mode clock input pins external clock pins channels a-phase b-phase when channel 2 is set to phase counting mode tpu_ti2a tpu_ti2b when channel 3 is set to phase counting mode tpu_ti3a tpu_ti3b section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 540 of 1458 rej09b0033-0300 (1) example of phase counting mode setting procedure figure 15.14 shows an example of the phase counting mode setting procedure. select phase counting mode phase counting mode start count section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 541 of 1458 rej09b0033-0300 (2) examples of phase counting mode operation in phase counting mode, tcnt counts up or down according to the phase difference between two external clocks. there are four mode s, according to the count conditions. (a) phase counting mode 1 figure 15.15 shows an example of phase counting mode 1 operation, and table 15.8 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tpu_ ti2a (channel 2) tpu_ ti3a (channel 3) tpu_ ti2b (channels 2) tpu_ ti3b (channels 3) figure 15.15 example of phase counting mode 1 operation table 15.8 up/down-count condit ions in phase counting mode 1 tpu_ti2a (channel 2) tpu_ti3a (channel 3) tpu_ti2b (channel 2) tpu_ti3b (channel 3) operation high level up-count low level low level high level high level down-count low level high level low level [legend] : rising edge : falling edge section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 542 of 1458 rej09b0033-0300 (b) phase counting mode 2 figure 15.16 shows an example of phase counting mode 2 operation, and table 15.9 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tpu_ ti2a (channel 2) tpu_ ti3a (channel 3) tpu_ ti2b (channel 2) tpu_ ti3b (channel 3) figure 15.16 example of phase counting mode 2 operation table 15.9 up/down-count condit ions in phase counting mode 2 tpu_ti2a (channel 2) tpu_ti3a (channel 3) tpu_ti2b (channel 2) tpu_ti3b (channel 3) operation high level don't care low level low level high level up-count high level don't care low level high level low level down-count [legend] : rising edge : falling edge section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 543 of 1458 rej09b0033-0300 (c) phase counting mode 3 figure 15.17 shows an example of phase counting mode 3 operation, and table 15.10 summarizes the tcnt up/down-count conditions. tcnt value time up-count tpu_ ti2a (channel 2) tpu_ ti3a (channel 3) tpu_ ti2b (channel 2) tpu_ ti3b (channel 3) down-count figure 15.17 example of phase counting mode 3 operation table 15.10 up/down-count condit ions in phase counting mode 3 tpu_ti2a (channel 2) tpu_ti3a (channel 3) tpu_ti2b (channel 2) tpu_ti3b (channel 3) operation high level don't care low level low level high level up-count high level down-count low level don't care high level low level [legend] : rising edge : falling edge section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 544 of 1458 rej09b0033-0300 (d) phase counting mode 4 figure 15.18 shows an example of phase counting mode 4 operation, and table 15.11 summarizes the tcnt up/down-count conditions. time tpu_ ti2a (channel 2) tpu_ ti3a (channel 3) tpu_ ti2b (channel 2) tpu_ ti3b (channel 3) up-count down-count tcnt value figure 15.18 example of phase counting mode 4 operation table 15.11 up/down-count condit ions in phase counting mode 4 tpu_ti2a (channel 2) tpu_ti3a (channel 3) tpu_ti2b (channel 2) tpu_ti3b (channel 3) operation high level up-count low level low level don't care high level high level down-count low level high level don't care low level [legend] : rising edge : falling edge section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 545 of 1458 rej09b0033-0300 15.5 usage notes note that the kinds of operation and contention described below can occur during tpu operation. (1) input clock restrictions the input clock pulse width must be at least 2 states in the case of single-edge detection, and at least 3 states in the case of both-edge detection. the tpu will not operate properly with a narrower pulse width. in phase counting mode, the phase difference and ove rlap between the two inpu t clocks must be at least 2 states, and the pulse width must be at least 3 states. figure 15.19 shows the input clock conditions in phase counting mode. overlap phase differ- ence phase differ- ence overlap tpu_tclka (tpu_tclkc) tpu_tclkb (tpu_tclkd) pulse width pulse width pulse width pulse width notes: phase difference and overlap pulse width : 2 states or more : 3 states or more figure 15.19 phase difference, overlap, and pulse width in phase counting mode section 15 16-bit timer pulse unit (tpu) rev. 3.00 jan. 18, 2008 page 546 of 1458 rej09b0033-0300 section 16 compare match timer (cmt) timcmt1a_000020011000 rev. 3.00 jan. 18, 2008 page 547 of 1458 rej09b0033-0300 section 16 compare match timer (cmt) this lsi includes a 32-bit compare match timer (cmt ) of five channels (channel 0 to channel 4). 16.1 features ? 16 bits/32 bits can be selected. ? each channel is provided with an auto-reload up counter. ? all channels are provided with 32-bit constant registers and 32-bit up counters that can be written or read at any time. ? allows selection among three counter input clocks for channel 0 to channel 4: ? peripheral clock (p ): 1/8, 1/32, and 1/128 ? one-shot operation and free-runn ing operation are selectable. ? allows selection of compare match or overflow for the interrupt source. ? generate a dma transfer request when compare match or overflow occurs in channels 0 to 4. ? module standby mode can be set. section 16 compare match timer (cmt) rev. 3.00 jan. 18, 2008 page 548 of 1458 rej09b0033-0300 figure 16.1 shows a block diagram of the cmt. [legend] cmstr: cmcsr: compare match timer start register compare match timer control/status register cmcnt: cmcor: compare match timer counter compare match timer constant register pre-scaller pre-scaller pre-scaller pre-scaller pre-scaller internal interrupt dma transfer internal interrupt dma transfer internal interrupt dma transfer internal interrupt dma transfer internal interrupt dma transfer cmstr p ch0 cmt cmcnt_0 cmcor_0 cmcsr_0 interrupt control ch1 cmcnt_1 cmcor_1 cmcsr_1 ch2 cmcnt_2 cmcor_2 cmcsr_2 ch3 cmcnt_3 cmcor_3 cmcsr_3 ch4 cmcnt_4 cmcor_4 cmcsr_4 peripheral bus interrupt control interrupt control interrupt control interrupt control figure 16.1 block diagram of cmt section 16 compare match timer (cmt) rev. 3.00 jan. 18, 2008 page 549 of 1458 rej09b0033-0300 16.2 register descriptions the cmt has the following registers. refer to sectio n 37, list of registers, for more details on the addresses and states of these registers in eac h operating mode. notation for the cmt registers takes the form xxx_n, where xxx including the register name and n indicating the channel number. for example, cmcsr_0 denotes the cmcsr for channel 0. (1) common ? compare match timer start register (cmstr) (2) channel 0 ? compare match timer control/status register_0 (cmcsr_0) ? compare match timer counter_0 (cmcnt_0) ? compare match timer constant register_0 (cmcor_0) (3) channel 1 ? compare match timer control/status register_1 (cmcsr_1) ? compare match timer counter_1 (cmcnt_1) ? compare match timer constant register_1 (cmcor_1) (4) channel 2 ? compare match timer control/status register_2 (cmcsr_2) ? compare match timer counter_2 (cmcnt_2) ? compare match timer constant register_2 (cmcor_2) (5) channel 3 ? compare match timer control/status register_3 (cmcsr_3) ? compare match timer counter_3 (cmcnt_3) ? compare match timer constant register_3 (cmcor_3) (6) channel 4 ? compare match timer control/status register_4 (cmcsr_4) ? compare match timer counter_4 (cmcnt_4) ? compare match timer constant register_4 (cmcor_4) section 16 compare match timer (cmt) rev. 3.00 jan. 18, 2008 page 550 of 1458 rej09b0033-0300 16.2.1 compare match tim er start register (cmstr) cmstr is a 16-bit register that selects whethe r the compare match timer counter (cmcnt) is operated or halted. bit bit name initial value r/w description 15 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 2 1 0 str4 str3 str2 str1 str0 0 0 0 0 0 r/w r/w r/w r/w r/w count start 4 to 0 selects whether to operate or halt the compare match timer counter for each channel (cmcnt_4 to cmcnt_0). 0: cmcntn count operation halted 1: cmcntn count operation n: 4 to 0 (corresponds to each channel) section 16 compare match timer (cmt) rev. 3.00 jan. 18, 2008 page 551 of 1458 rej09b0033-0300 16.2.2 compare match timer co ntrol/status register (cmcsr) cmcsr is a 16-bit register that indicates the oc currence of compare matc hes, enables interrupts and dma transfer request, and sets the counter input clocks. do not change bits other than bits cmf and ovf during the compare match timer counter (cmcnt) operation. bit bit name initial value r/w description 15 cmf 0 r/(w) * 1 compare match flag this flag indicates whether or not values of the compare match timer counter (cmcnt) and compare match timer constant register (cmcor) have matched. software cannot write 1 to the bit. when one-shot is selected for the counter operation, counting resumes by clearing this bit. 0: cmcnt and cmcor values have not matched [clearing condition] ? write 0 to cmf after reading cmf=1 1: cmcnt and cmcor values have matched 14 ovf 0 r/(w) * 1 overflow flag this flag indicates whether or not the compare match timer counter (cmcnt) has overflowed and been cleared to 0. software cannot write 1 to this bit. 0: cmcnt has not overflowed [clearing condition] ? write 0 to ovf after reading ovf=1 1: cmcnt has overflowed 13 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 16 compare match timer (cmt) rev. 3.00 jan. 18, 2008 page 552 of 1458 rej09b0033-0300 bit bit name initial value r/w description 9 cms 0 r/w compare match timer counter size selects whether the compare match timer counter (cmcnt) is used as a 16-bit counter or a 32-bit counter. this setting becomes the valid size for the compare match timer constant register (cmcor). 0: operates as a 32-bit counter 1: operates as a 16-bit counter 8 cmm 0 r/w compare match mode selects one-shot operation or free-running operation of the counter. 0: one-shot operation 1: free-running operation 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 4 cmr1 cmr0 0 0 r/w r/w compare match request 1, 0 selects enable or disable for a dma transfer request or internal interrupt request in a compare match. 00: disables a dma transfer request and internal interrupt request 01: enables dma transfer request 10: enables an internal interrupt request 11: setting prohibited 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 16 compare match timer (cmt) rev. 3.00 jan. 18, 2008 page 553 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 these bits select the clock input to cmcnt. when the strn (n: 4 to 0) bit in cmst r is set to 1, cmcnt begins incrementing with the clock selected by these bits. 000: p /8 001: p /32 010: p /128 011: setting prohibited 100: setting prohibited 101: setting prohibited 110: setting prohibited 111: setting prohibited note: * only 0 can be written to clear the flag. 16.2.3 compare match timer counter (cmcnt) cmcnt is a 32-bit register that is used as an up-counter. a counter operation is set by the compare ma tch timer control/status register (cmcsr). therefore, set cmcsr first, before starting a channel operation corresponding to the compare match timer start register (cmstr). when the 16 -bit counter operation is selected by the cms bit, bits 15 to 0 of this register become valid. wh en the register should be written to, write the data that is added h'0000 to the upper half in a 32- bit operation. the contents of this register are initialized to h'00000000. 16.2.4 compare match timer constant register (cmcor) cmcor is a 32-bit register that sets the comp are match period with cmcnt for each channel. when the 16-bit counter operation is selected by the cms bit in cmcsr, bits 15 to 0 of this register become valid. when the register should be written to, write the data that is added h'0000 to the upper half in a 32-bit operation. an overflow is detected when cmcnt is cleared to 0 and this register is h'ffffffff. the contents of this register are initialized to h'ffffffff. section 16 compare match timer (cmt) rev. 3.00 jan. 18, 2008 page 554 of 1458 rej09b0033-0300 16.3 operation 16.3.1 counter operation the cmt starts the operation of the counter by writing a 1 to the strn bit in cmstr of a channel that has been selected for operation. complete all of the settings before starting the operation. do not change the register settings other than by clearing flag bits. the counter operates in one of two ways. ? one-shot operation one-shot operation is selected by setting the cmm bit in cmcsr to 0. when the value in cmcnt matches the value in cmcor, the value in cmcnt is cleared to h'00000000 and the cmf bit in cmcsr is set to 1. counting by cmcnt stops after it has been cleared. to detect an overflow interrupt, set the va lue in cmcor to h'ffffffff. when the value in cmcnt matches the value in cmcor, cmcnt is cleared to h'00000000 and bits cmf and ovf in cmcsr are set to 1. value in cmcnt cmcor cmf = 1 ovf = 1 (when an overflow is detected) h'00000000 time figure 16.2 counter oper ation (one-shot operation) section 16 compare match timer (cmt) rev. 3.00 jan. 18, 2008 page 555 of 1458 rej09b0033-0300 ? free-running operation free-running operation is selected by setting th e cmm bit in cmcsr to 1. when the value in cmcnt matches the value in cmcor, cmcnt is cleared to h'00000000 and the cmf bit in cmcsr is set to 1. cmcnt resumes co unting-up after it has been cleared. to detect an overflow inte rrupt, set cmcor to h'ffffffff. when the values in cmcnt and cmcor match, cmcnt is cleared to h'00000000 and bits cmf and ovf in cmcsr are set to 1. cmcor h'00000000 value in cmcnt cmf=1 ovf=1 (when an overflow is detected) time figure 16.3 counter oper ation (free-running operation) 16.3.2 counter size in this module, the size of the counte r is selectable as either 16 or 32 bits. this is selected by the cms bit in cmcsr. when the 16-bit size is selected, use a 32-bit va lue which has h'0000 as its upper half to set cmcor. to detect an overflow interrupt, the value must be set to h'0000ffff. section 16 compare match timer (cmt) rev. 3.00 jan. 18, 2008 page 556 of 1458 rej09b0033-0300 16.3.3 timing for counting by cmcnt in this module, the clock for the counter can be selected from among the following: ? for channels 0 to 4: ? peripheral clock (p ): 1/8, 1/32, or 1/128 the clock for the counter is sel ected by bits cks2 to cks0 in cmcsr. cmcnt is incremented at the rising edge of the selected clock. 16.3.4 dma transfer requests and internal interrupt requests to cpu the setting of bits cmr1 and cmr0 in cmcsr selects the sending of a request for a dma transfer or for an internal interrupt to the cpu at a compare match. a dma transfer request has different specifications according to the cmt channel as described below. 1. for channels 0 and 1, a single dma transf er request is output at a compare match. 2. for channels 2 to 4, a dma transfer request continues until the amount of data transferred has reached the value set in the dmac, and the out put of the request then automatically stops. to clear the interrupt request, the cmf bit should be set to 0. set the cmf bit to 0 in the handling routine for the cmt interrupt. section 16 compare match timer (cmt) rev. 3.00 jan. 18, 2008 page 557 of 1458 rej09b0033-0300 16.3.5 compare match flag set timing (all channels) the cmf bit in cmcsr is set to 1 by the compare match signal generated when cmcor and cmcnt match. the compare match signal is generated upon the final state of the match (timing at which the cmcnt value is updated to h'0000). consequently, after cmcor and cmcnt match, a compare match signal will not be generated until a cmcnt counter clock is input. figure 16.4 shows the set timing of the cmf bit. peripheral operating clock (p ) counter clock cmcnt cmcor compare match signal and interrupt signal n + 1 clock n 0 n figure 16.4 cmf set timing section 16 compare match timer (cmt) rev. 3.00 jan. 18, 2008 page 558 of 1458 rej09b0033-0300 section 17 realtime clock (rtc) rtcs320b_000020020900 rev. 3.00 jan. 18, 2008 page 559 of 1458 rej09b0033-0300 section 17 realtime clock (rtc) this lsi has a realtime clock (rtc) with its own 32.768-khz crystal oscillator. 17.1 features ? clock and calendar functions (bcd format): seconds, minutes, hours, date, day of the week, month, and year ? 1-hz to 64-hz timer (binary format) 64-hz counter indicates the state of the rtc divider circuit between 64 hz and 1 hz ? start/stop function ? 30-second adjust function ? alarm interrupt: frame comparison of seconds, minutes, hours, date, day of the week, month, and year can be used as conditions for the alarm interrupt ? periodic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds ? carry interrupt: a carry interrupt indicates when a carry occurs during a counter read ? automatic leap year adjustment section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 560 of 1458 rej09b0033-0300 figure 17.1 shows the block diagram of rtc. rseccnt: rmincnt: rhrcnt: rwkcnt: rdaycnt: rmoncnt: ryrcnt: r64cnt: rcr1: second counter (8 bits) minute counter (8 bits) hour counter (8 bits) day of week counter (8 bits) date counter month counter (8 bits) year counter (16 bits) 64-hz counter (8 bits) rtc control register 1 (8 bits) rsecar: rminar: rhrar: rwkar: rdayar: rmonar: ryrar: rcr2: rcr3: second alarm register (8 bits) minute alarm registger (8 bits) hour alarm register (8 bits) day of week alarm register (8 bits) date alarm register (8 bits) month alarm register (8 bits) year alarm register (16 bits) rtc control register 2 (8 bits) rtc control register 3 [legend] rhrcnt rmincnt interrupt control circuit rdaycnt ryrcnt rmoncnt oscillator circuit extal_rtc xtal_rtc rcr2 rcr3 rwkcnt rhrar rminar rdayar rwkar externally connected circuit prescaler 32.768khz 128hz ati pri cu rcr1 rtc operation control circuit r64cnt rseccnt rsecar rtcclk (16khz) count interrupt signals rmonar ryrar bus interface peripheral module internal bus figure 17.1 rtc block diagram section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 561 of 1458 rej09b0033-0300 17.2 input/output pin table 17.1 shows the rtc pin configuration. table 17.1 pin configuration name abbreviation i/o description rtc external clock extal_rtc input c onnects crystal resonator for rtc. also used to input external clock for rtc. rtc crystal xtal_rtc output connec ts crystal resonator for rtc. rtc power supply v cc _rtc ? power-supply pin for rtc (1.5 v) * rtc gnd v ss _rtc ? gnd pin for rtc * rtc power supply v cc q_rtc ? power-supply pin for rtc (3.3 v) * note: * power-supply pins for rtc should be power supplied even when the rtc is not used. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 562 of 1458 rej09b0033-0300 17.3 register descriptions the rtc has the following registers. refer to section 37, list of registers, for more details on the addresses and access size of these registers. ? 64-hz counter (r64cnt) ? second counter (rseccnt) ? minute counter (rmincnt) ? hour counter (rhrcnt) ? day of week counter (rwkcnt) ? date counter (rdaycnt) ? month counter (rmoncnt) ? year counter (ryrcnt) ? second alarm register (rsecar) ? minute alarm register (rminar) ? hour alarm register (rhrar) ? day of week alarm register (rwkar) ? date alarm register (rdayar) ? month alarm register (rmonar) ? year alarm register (ryrar) ? rtc control register 1 (rcr1) ? rtc control register 2 (rcr2) ? rtc control register 3 (rcr3) section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 563 of 1458 rej09b0033-0300 17.3.1 64-hz counter (r64cnt) r64cnt indicates the state of the divider circuit between 64 hz and 1 hz. reading this register, when carry from 128-hz divider stage is generated, sets the cf bit in the rtc control register 1 (rcr1) to 1 so that the carrying and reading 64 hz counter are performed at the same time is indicated. in this case, the r 64cnt should be read again after writing 0 to the cf bit in rcr1 since the read value is not valid. after the reset bit or adj bit in the rtc control register 2 (rcr2) is set to 1, the rtc divider circuit is initialized and r64cnt is initialized to h'00. r64cnt is not initialized by a power-on re set or manual reset, or in standby mode. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. writing has no effect. 6 1 hz undefined r 5 2 hz undefined r 4 4 hz undefined r 3 8 hz undefined r 2 16 hz undefined r 1 32 hz undefined r 0 64 hz undefined r indicate the state of the divider circuit between 64 hz and 1 hz. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 564 of 1458 rej09b0033-0300 17.3.2 second counter (rseccnt) rseccnt is used for setting/counting in the bcd-c oded second section. the count operation is performed by a carry fo r each second of the 64 - hz counter. the range of second can be set is 00 to 59 (decimal). errant operation will result if any other value is set. carry out write processing after stoppin g the count operation with the start bit in rcr2. rseccnt is not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 to 4 ? undefined r/w counting ten?s position of seconds counts on 0 to 5 for 60-seconds counting. 3 to 0 ? undefined r/w counting one?s position of seconds counts on 0 to 9 once per second. when a carry is generated, 1 is added to the ten?s position. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 565 of 1458 rej09b0033-0300 17.3.3 minute counter (rmincnt) rmincnt is used for setting/counting in the bcd-coded minute section. the count operation is performed by a carry for each minute of the second counter. the range of minute can be set is 00 to 59 (decimal). errant operation will result if any other value is set. carry out write processing after stoppin g the count operation with the start bit in rcr2. rmincnt is not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0.the write value should always be 0. 6 to 4 ? undefined r/w counting ten?s position of minutes counts on 0 to 5 for 60-minutes counting. 3 to 0 ? undefined r/w counting one?s position of minutes counts on 0 to 9 once per second. when a carry is generated, 1 is added to the ten?s position. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 566 of 1458 rej09b0033-0300 17.3.4 hour counter (rhrcnt) rhrcnt is used for setting/counting in the bcd-coded hour section. the count operation is performed by a carry for each 1 hour of the minute counter. the range of hour can be set is 00 to 23 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rhrcnt is not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. though writing has no effect, the write value should always be 0. 5, 4 ? undefined r/w counting ten?s position of hours counts on 0 to 2 for ten?s position of hours. 3 to 0 ? undefined r/w counting one?s position of hours counts on 0 to 9 once per hour. when a carry is generated, 1 is added to the ten?s position. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 567 of 1458 rej09b0033-0300 17.3.5 day of week counter (rwkcnt) rwkcnt is used for setting/counting day of week section. the count operation is performed by a carry for each day of the date counter. the range for day of the week can be set is 0 to 6 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rwkcnt is not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. though writing has n effect, the write value should always be 0. 2 to 0 ? undefined r/w day-of-week counting day-of-week is indicated with a binary code. 000: sunday 001: monday 010: tuesday 011: wednesday 100: thursday 101: friday 110: saturday 111: reserved (setting prohibited) section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 568 of 1458 rej09b0033-0300 17.3.6 date counter (rdaycnt) rdaycnt is used for setting/counting in the bcd-coded date section. the count operation is performed by a carry for each day of the hour counter. though the range of date which can be set is 01 to 31 (decimal). errant operation will result if any other value is set. carry out write processing after stopping the count operation with the start bit in rcr2. rdaycnt is not initialized by a power-on reset or manual reset, or in standby mode. the range of date changes with each month and in leap years. please confirm the correct setting. leap years are recognized by dividing the year counter values by 400, 100, and 4 and obtaining a fractional result of 0. the year counter va lue of 0000 is included in the leap year. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5, 4 ? undefined r/w counting ten?s position of dates 3 to 0 ? undefined r/w counting one?s position of dates counts on 0 to 9 once per date. when a carry is generated, 1 is added to the ten?s position. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 569 of 1458 rej09b0033-0300 17.3.7 month counter (rmoncnt) rmoncnt is used for setting/counting in the bcd-coded month section. the count operation is performed by a carry for each month of the date counter. the range of month can be set is 01 to 12 (decimal). errant operation will result if any other value is set. carry out write processing after stoppin g the count operation with the start bit in rcr2. rmoncnt is not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. though writing has no effect, the write value should always be 0. 4 ? undefined r/w counting ten?s position of months 3 to 0 ? undefined r/w counting one?s position of months counts on 0 to 9 once per month. when a carry is generated, 1 is added to the ten?s position. 17.3.8 year counter (ryrcnt) ryrcnt is used for setting/counting in the bcd-coded year section. the count operation is performed by a carry for each year of the month counter. the range for year which can be set is 0000 to 9999 (decimal). errant operation will result if any other value is set. carry out write processing after halting the count operation with the start bit in rcr2 or using a carry flag. ryrcnt is not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 15 to 12 ? undefined r/w counting thousand?s position of years 11 to 8 ? undefined r/w counting hundred?s position of years 7 to 4 ? undefined r/w counting ten?s position of years 3 to 0 ? undefined r/w counting one?s position of years section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 570 of 1458 rej09b0033-0300 17.3.9 second alarm register (rsecar) rsecar is an alarm register corresponding to the bcd coded second counter rseccnt of the rtc. when the enb bit is set to 1, a comparis on with the rseccnt value is performed. from among rsecar/rminar/rh rar/rwkar/rdayar/rmonar /rcr3, the counter and alarm register comparison is perf ormed only on those with enb bits set to 1, and if each of those coincide, an alarm flag of rcr1 is set to 1. the range of second alarm which ca n be set is 00 to 59 (decimal) + enb bits. errant operation will result if any other value is set. the enb bit in rsecar is initialized to 0 by a power-on reset. the remaining rsecar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w when this bit is set to 1, a comparison with the rseccnt value is performed. 6 to 4 ? undefined r/w ten?s position of seconds setting value 3 to 0 ? undefined r/w one?s position of seconds setting value 17.3.10 minute alarm register (rminar) rminar is an alarm register co rresponding to the minute counter rmincnt. when the enb bit is set to 1, a comparison with the rm incnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/rmonar/rcr3, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an alarm flag of rcr1 is set to 1. the range of minute alarm which can be set is 00 to 59 (decimal). errant op eration will result if any other value is set. the enb bit in rminar is initialized by a power-on reset. the remaining rminar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w when this bit is set to 1, a comparison with the rmincnt value is performed. 6 to 4 ? undefined r/w ten?s position of minutes setting value 3 to 0 ? undefined r/w one?s position of minutes setting value section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 571 of 1458 rej09b0033-0300 17.3.11 hour alarm register (rhrar) rhrar is an alarm register co rresponding to the bcd coded hour counter rhrcnt of the rtc. when the enb bit is set to 1, a comparison w ith the rhrcnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/rmonar/rcr3, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an alarm flag of rcr1 is set to 1. the range of hour alarm which can be set is 00 to 23 (decimal). errant oper ation will result if any other value is set. the enb bit in rhrar is initialized by a power-o n reset. the remaining rhrar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w when this bit is set to 1, a comparison with the rhrcnt value is performed. 6 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 5, 4 ? undefined r/w ten?s position of hours setting value 3 to 0 ? undefined r/w one?s position of hours setting value section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 572 of 1458 rej09b0033-0300 17.3.12 day of week alarm register (rwkar) rwkar is an alarm register co rresponding to the bcd coded day of week counter rwkcnt. when the enb bit is set to 1, a comparison wi th the rwkcnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/rmonar/rcr3, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an alarm flag of rcr1 is set to 1. the range of day of the week alarm which can be set is 0 to 6 (decimal). errant operation will result if any other value is set. the enb bit in rwkar is initialized by a power-on reset. the remaining rwkar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w when this bit is set to 1, a comparison with the rwkcnt value is performed. 6 to 3 ? 0 r reserved these bits are always read as 0. the write value should always be 0. 2 to 0 ? undefined r/w day of week setting value code 0 1 2 3 4 5 6 day sunday monday tuesday w ednesday thursday friday saturday section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 573 of 1458 rej09b0033-0300 17.3.13 date alarm register (rdayar) rdayar is an alarm register corresponding to the bcd coded date counter rdaycnt. when the enb bit is set to 1, a comparison with the rdaycnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/rmonar/rcr3, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an alarm flag of rcr1 is set to 1. the range of date alarm which can be set is 01 to 31 (decimal). errant operation will result if any other value is set. the rdaycnt range that can be set changes with some months and in leap years. please confirm the correct setting. the enb bit in rdayar is initialized by a power-on reset. the remaining rdayar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w when this bit is set to 1, a comparison with the rdaycnt value is performed. 6 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 5, 4 ? undefined r/w ten?s position of dates setting value 3 to 0 ? undefined r/w one?s position of dates setting value section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 574 of 1458 rej09b0033-0300 17.3.14 month alarm register (rmonar) rmonar is an alarm register corresponding to the month counter rm oncnt. when the enb bit is set to 1, a comparison with the rmoncnt value is performed. from among rsecar/rminar/rhrar/rwkar/rdayar/rmonar/rcr3, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an alarm flag of rcr1 is set to 1. the range of month alarm which can be set is 01 to 12 (decimal). errant operation will result if any other value is set. the enb bit in rmonar is initialized by a power-on reset. the remaining rmonar fields are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w when this bit is set to 1, a comparison with the rmoncnt value is performed. 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 ? undefined r/w ten?s positi on of months setting value 3 to 0 ? undefined r/w one?s positi on of months setting value 17.3.15 year alarm register (ryrar) ryrar is an alarm register corr esponding to the year counter ry rcnt. the range of year alarm which can be set is 0000 to 9999 (decimal). errant operation will result if any other value is set. bit bit name initial value r/w description 15 to 12 ? undefined r/w thousand?s pos ition of years setting value 11 to 8 ? undefined r/w hundred?s position of years setting value 7 to 4 ? undefined r/w ten?s position of years setting value 3 to 0 ? undefined r/w one?s position of years setting value section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 575 of 1458 rej09b0033-0300 17.3.16 rtc control register 1 (rcr1) rcr1 is a register that affects carry flags and al arm flags. it also selects whether to generate interrupts for each flag. rcr1 is initialized to h'00 by a power-on reset or a manual reset, all bits are initialized to 0 except for the cf flag, which is undefined. when using the cf flag, it must be initialized beforehand. this register is not initialized in standby mode. bit bit name initial value r/w description 7 cf undefined r/w carry flag status flag that indicates that a carry has occurred. cf is set to 1 when a count-up to 64- hz occurs at the second counter carry or 64-hz counter read. a count register value read at this time cannot be guaranteed; another read is required. 0: no carry of 64-hz counter by second counter or 64-hz counter [clearing condition] when 0 is written to cf 1: carry of 64-hz counter by second counter or 64 hz counter [setting condition] when the second counter or 64-hz counter is read during a carry occurrence by the 64-hz counter, or 1 is written to cf. 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 576 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 cie 0 r/w carry interrupt enable flag when the carry flag (cf) is set to 1, the cie bit enables interrupts. 0: a carry interrupt is not generated when the cf flag is set to 1 1: a carry interrupt is generated when the cf flag is set to 1 3 aie 0 r/w alarm interrupt enable flag when the alarm flag (af) is set to 1, the aie bit allows interrupts. 0: an alarm interrupt is not generated when the af flag is set to 1 1: an alarm interrupt is generated when the af flag is set to 1 2, 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 af 0 r/w alarm flag the af flag is set when the alarm time, which is set by an alarm register(enb bit in rsecar, rminar, rhrar, rwkar, rdayar, rmonar, or ryrar is set to 1), and counter match. 0: alarm register and counter not match [clearing condition] when 0 is written to af. 1: alarm register and counter match * [setting condition] when alarm register (only a register with enb bit set to 1) and counter match note: * writing 1 holds previous value. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 577 of 1458 rej09b0033-0300 17.3.17 rtc control register 2 (rcr2) rcr2 is a register for periodic interrupt contro l, 30-second adjustment adj, divider circuit reset, and rtc count control. rcr2 is initialized to h'09 by a power-on reset. it is initialized except for rtcen and start by a manual reset. it is not initialized in standby mode, and retains its contents. bit bit name initial value r/w description 7 pef 0 r/w periodic interrupt flag indicates interrupt generation with the period designated by the pes2 to pes0 bits. when set to 1, pef generates periodic interrupts. 0: interrupts not generated with the period designated by the bits pes2 to pes0. [clearing condition] when 0 is written to pef 1: interrupts generated with the period designated by the pes2 to pes0 bits. [setting condition] when an interrupt is generated with the period designated by the bits pes0 to pes2 or when 1 is written to the pef flag 6 5 4 pes2 pes1 pes0 0 0 0 r/w r/w r/w interrupt enable flags these bits specify the periodic interrupt. 000: no periodic interrupts generated 001: periodic interrupt generated every 1/256 second 010: periodic interrupt generated every 1/64 second 011: periodic interrupt generated every 1/16 second 100: periodic interrupt generated every 1/4 second 101: periodic interrupt generated every 1/2 second 110: periodic interrupt generated every 1 second 111: periodic interrupt generated every 2 seconds section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 578 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 rtcen 1 r/w crystal oscillator control controls the operation of the crystal oscillator for the rtc. 0: halts the crystal o scillator for the rtc. 1: runs the crystal oscillator for the rtc. 2 adj 0 r/w 30-second adjustment when 1 is written to the adj bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. the divider circuit (rtc prescaler and r64cnt) will be simultaneously reset. this bit always reads 0. 0: runs normally. 1: 30-second adjustment. 1 reset 0 r/w reset when 1 is written, initializes the divider circuit (rtc prescaler and r64cnt). this bit always reads 0. 0: runs normally. 1: divider circuit is reset. 0 start 1 r/w start bit halts and restarts the counter (clock). 0: second/minute/hour/day/week/month/year counter halts. 1: second/minute/hour/day/week/month/year counter runs normally. note: the 64-hz counter always runs unless stopped with the rtcen bit. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 579 of 1458 rej09b0033-0300 17.3.18 rtc control register 3 (rcr3) when the enb bit is set to 1, rcr3 performs a comparison with the ryrcnt. from among rsecar/rminar/rhrar/rwkar/rdayar/rmonar/rcr3, the counter and alarm register comparison is performed only on those with enb bits set to 1, and if each of those coincide, an alarm flag of rcr1 is set to 1. the enb bit in ryrar is initialized by a power -on reset. remaining fields of rcr3 are not initialized by a power-on reset or manual reset, or in standby mode. bit bit name initial value r/w description 7 enb 0 r/w when this bit is set to 1, comparison of the year alarm register (ryrar) and the year counter (ryrcnt) is performed. 6 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 580 of 1458 rej09b0033-0300 17.4 operation rtc usage is shown below. 17.4.1 initial settings of registers after power-on all the registers should be set after the power is turned on. 17.4.2 setting time figure 17.2 shows how to set the time when the clock is stopped. write 1 to reset and 0 to start in the rcr2 register order is irrelevant write 1 to start in the rcr2 register set seconds, minutes, hour, day, day of the week, month, and year stop clock, reset divider circuit start clock figure 17.2 setting time section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 581 of 1458 rej09b0033-0300 17.4.3 reading time figure 17.3 shows how to read the time. disable the carry interrupt clear the carry flag read counter register carry flag = 1? yes no yes no read counter register interrupt disable the carry interrupt write 0 to cf in rcr1 (set af in rcr1 to 1 so that alarm flag is not cleared.) read rcr1 and check cf bit write 1 to cie in rcr1 write 0 to cie in rcr1 clear the carry flag enable the carry interrupt clear the carry flag write 0 to cf in rcr1 (set af in rcr1 to 1 so that alarm flag is not cleared.) read rcr1 and check cf bit write 0 to cie in rcr1 to read the time without using interrupts (b) to use interrupts (a) figure 17.3 reading time if a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. part (a) in figure 17.3 shows the method of reading the time without using interrupts; part (b) in figure 17.3 shows the method using carry interrupts. to keep programming simple, method (a) should normally be used. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 582 of 1458 rej09b0033-0300 17.4.4 alarm function figure 17.4 shows how to use the alarm function. write 0 to aie in rcr1 to prevent errorneous interrupt clock running set alarm time disable alarm interrupt always clear, since the flag may have been set while the alarm time was being set. write 1 to aie in rcr1 clear alarm flag enable alarm interrupt monitor alarm time (wait for interrupt or check alarm flag) figure 17.4 using alarm function alarms can be generated using seconds, minutes, hours, day of the week, date, month, year, or any combination of these. set the enb bit in the regist er on which the alarm is placed to 1, and then set the alarm time in the lower bits. clear the enb bit in the register on which the alarm is not placed to 0. when the clock and alarm times match, 1 is set in the af bit in rcr1. alarm detection can be checked by reading this bit, but normally it is done by interrupt. if 1 is set in the aie bit in rcr1, an interrupt is generated when an alarm occurs. the alarm flag is set when the clock and alarm times match. however, the alarm flag can be cleared by writing 0. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 583 of 1458 rej09b0033-0300 17.5 usage notes 17.5.1 register writing during rtc count the following rtc registers cannot be written to during an rtc count (while bit 0 = 1 in rcr2). rseccnt, rmincnt, rhrcnt, rd aycnt, rwkcnt, rmoncnt, ryrcnt the rtc count must be stopped before writing to any of the above registers. 17.5.2 use of real time clock (rtc) periodic interrupts the method of using the periodic interrupt function is shown in figure 17.5. a periodic interrupt can be generated periodically at the interval set by the flags pes0 to pes2 in rcr2. when the time set by the pes0 to pes2 has elapsed, the pef is set to 1. the pef is cleared to 0 upon periodic interrupt generation or when the flags pes0 to pes2 are set. periodic interrupt generation can be confirmed by reading this bit, but normally the interrupt function is used. set pes0 to pes2, and clear pef to 0, in rcr2 clear pef to 0 set pes, clear pef elapse of time set by pes clear pef figure 17.5 using periodic interrupt function 17.5.3 transition to standby mode after setting register when a transition to standby mode is made after registers in the rtc are set, sometimes counting is not performed correctly. in case the registers are set, be sure to make a transition to standby mode after waiting for two rtc clocks or more. section 17 realtime clock (rtc) rev. 3.00 jan. 18, 2008 page 584 of 1458 rej09b0033-0300 17.5.4 crystal oscillator circuit crystal oscillator circuit constants (recommended values) are shown in table 17.2, and the rtc crystal oscillator circuit in figure 17.5. table 17.2 recommended oscillator circu it constants (recommended values) f osc c in c out 32.768 khz 10 to 22 pf 10 to 22 pf this lsi extal_rtc xtal_rtc xtal c in c out r f r d notes: 1. select either the c in or c out side for frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc. 2. built-in resistance value r f (typ value) = 10 m ? , r d (typ value) = 400 k ? 3. c in and c out values include floating capacitance due to the wiring. take care when using a ground plane. 4. the crystal oscillation settling time depends on the mounted circuit constants, stray capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. 5. place the crystal resonator and load capacitors c in and c out as close as possible to the chip. (correct oscillation may not be possible if there is externally induced noise in the extal_rtc and xtal_rtc pins.) 6. ensure that the crystal resonator connection pin (extal_rtc, xtal_rtc) wiring is routed as far away as possible from other power lines (except gnd) and signal lines. figure 17.6 example of crysta l oscillator circuit connection section 18 serial communicati on interface with fifo (scif) scis3c0c_000020030200 rev. 3.00 jan. 18, 2008 page 585 of 1458 rej09b0033-0300 section 18 serial communi cation interface with fifo (scif) this lsi has single-channel serial communicati on interface with fifo (scif) that supports asynchronous serial communication. the scif can perform asynchronous and synchronous serial communication. it also has 64-stage fifo register s for both transmission and reception that enable this lsi efficient high-s peed continuous communication. chan nel 0 operates as an irda interface while optional module irda is used. 18.1 features ? asynchronous or synchronous mode can be selected for serial communication mode. ? on-chip baud rate generator with selectable bit rates ? internal or external tr ansmit/receive clock source: from either baud rate generator (internal) or sck pin (external) ? six types of interrupts (asynchronous mode): transmit-data-stop, transmit-fi fo-data-empty, receive-fifo-da ta-full, receive-error (framing error/parity error), break-receiv e, and receive-data-ready interru pts. a common interrupt vector is assigned to each interrupt source. ? two types of interrupts (synchronous mode) ? the direct memory access controller (dmac) can be activated to execute a data transfer by a transmit-fifo-data-em pty or receive-fifo-data-full interrupt. ? on-chip modem control functions (cts and rts) ? transmit data stop function is available ? while the scif is not used, it can be stopped by stopping the clock for it to reduce power consumption. ? the number of data in the tran smit and receive fifo registers an d the number of receive errors of the receive data in the receiv e fifo register can be known. ? channel 0 operates as an irda interface. ? full-duplex communication capability the transmitter and receiver are independent units , enabling transmission and reception to be performed simultaneously. the transmitter and receiver both have a 64-stage fifo buffer structure, enabling fast and continuous serial data transmission and reception. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 586 of 1458 rej09b0033-0300 ? asynchronous mode: serial data communications are performed by start-stop in character units. the sci can communicate with a un iversal asynchronous receiver/tran smitter (uart), an asynchronous communication interface adapter (acia), or any other communicat ions chip that employs a standard asynchronous serial sy stem. there are eight selectable serial data communication formats. ? data length: seven or eight bits ? stop bit length: one or two bits ? parity: even, odd, or none ? lsb first ? receive error detection: parity , framing, and overrun errors ? break detection: break is detected when the receive data next the generated framing error is the space 0 level and has the framing error. ? synchronous mode: serial data communication is synchronized with a clock. serial data communication can be carried out with other chips that have a synchronous communication function. ? data length: 8 bits ? lsb-first transfer section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 587 of 1458 rej09b0033-0300 figure 18.1 shows the block diagram of scif. module data bus bus interface peripheral bus scfrdr (64 stages) scrsr rxd scftdr (64 stages) sctsr scfdr scfcr scfer scssr scscr scsmr sctdsr clock external clock parity generation parity check scbrr p p /4 p /16 p /64 scif interrupt sck cts rts txd scrsr: scfrdr: sctsr: scftdr: scsmr: scscr: receive shift register receive fifo data register transmit shift register transmit fifo data register serial mode register serial control register scfer: scssr: scbrr: scfcr: scfdr: sctdsr: fifo error count register serial status register bit rate register fifo control register fifo data count register transmit data stop register scif [legend] transmission/ reception control baud rate generator figure 18.1 block diagram of scif section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 588 of 1458 rej09b0033-0300 18.2 input/output pins table 18.1 shows the pin configuration of scif. table 18.1 pin configuration channel pin name abbreviation * 1 i/o function scif0_sck sck input * 3 clock input/output scif0_rxd rxd input receive data input scif0_txd txd output transmit data output scif0_cts cts * 2 input clear to send 0 scif0_rts rts * 2 output request to send scif1_sck sck input * 3 clock input/output scif1_rxd rxd input receive data input scif1_txd txd output transmit data output scif1_cts cts * 2 input clear to send 1 scif1_rts rts * 2 output request to send notes: 1. pin names sck, rxd, txd, cts , and rts are used in this manual for all channels, omitting the channel designation. 2. these pins are used as serial pins by se tting the scif with the te and re bits in scif and the mce bit in scfcr. 3. the sck pin can be set as input (input enabled or disabled). section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 589 of 1458 rej09b0033-0300 18.3 register descriptions scif has the following registers. refer to section 37, list of registers, for more details on the addresses and states of these registers in each ope rating mode. note that the channel number of each register is omitted. (1) channel 0 ? receive shift register_0 (scrsr_0) ? receive fifo data re gister_0 (scfrdr_0) ? transmit shift register_0 (sctsr_0) ? transmit fifo data register_0 (scftdr_0) ? serial mode register_0 (scsmr_0) ? serial control register_0 (scscr_0) ? fifo error count register_0 (scfer_0) ? serial status regi ster_0 (scssr_0) ? bit rate register_0 (scbrr_0) ? fifo control register_0 (scfcr_0) ? fifo data count register_0 (scfdr_0) ? transmit data stop register_0 (sctdsr_0) (2) channel 1 ? receive shift register_1 (scrsr_1) ? receive fifo data re gister_1 (scfrdr_1) ? transmit shift register_1 (sctsr_1) ? transmit fifo data register_1 (scftdr_1) ? serial mode register_1 (scsmr_1) ? serial control register_1 (scscr_1) ? fifo error count register_1 (scfer_1) ? serial status regi ster_1 (scssr_1) ? bit rate register_1 (scbrr_1) ? fifo control register_1 (scfcr_1) ? fifo data count register_1 (scfdr_1) ? transmit data stop register_1 (sctdsr_1) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 590 of 1458 rej09b0033-0300 18.3.1 receive shift register (scrsr) scrsr receives serial data. data input at the rx d pin is loaded into the scrsr in the order received, lsb (bit 0) first, converting the data to parallel form. when one byte has been received, it is automatically transferred to the scfrdr, which is a receive fifo data register. the cpu cannot read from or write to the scrsr directly. 18.3.2 receive fifo da ta register (scfrdr) the 64-byte receive fifo data re gister (scfrdr) stores serial receive data. the scif completes the reception of one byte of serial data by moving the received data from th e receive shift register (scrsr) into the scfrdr for storage. continuous receive is enabled until 64 bytes are stored. the cpu can read but not write the scfrdr. when data is read without received data in the scfrdr, the value is undefined. when the receive d data in this register becomes full, the subsequent serial data is lost. bit bit name initial value r/w description 7 to 0 scfrd7 to scfrd0 undefined r fi fo data registers for serial receive data 18.3.3 transmit shift register (sctsr) sctsr transmits serial data. the scif loads transm it data from the transmit fifo data register (scftdr) into the sctsr, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one data byte, the sci automatically loads the next transmit data from the scftdr into the sctsr and starts transmitting again. the cpu cannot read or write the sctsr directly. 18.3.4 transmit fifo data register (scftdr) scftdr is a 64-byte 8-bit-length fifo register that stores data for serial transmission. when the scif detects that the transmit shift register (sct sr) is empty, it moves transmit data written in the scftdr into the sctsr and starts serial tr ansmission. continuous serial transmission is performed until the transmit data in the scftdr becomes empty. the cp u can always write to the scftdr. when the transmit data in the scftdr is full (64 bytes), next data cannot be written. if attempted to write, the data is ignored. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 591 of 1458 rej09b0033-0300 bit bit name initial value r/w description 7 to 0 scftd7 to scftd0 undefined r fifo data registers for serial transmit data 18.3.5 serial mode register (scsmr) scsmr is a 16-bit register that specifies the sc if serial commun ication format and selects the clock source for the baud rate generator and the sampling rate. bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits are always read 0. the write value should always be 0. 10 9 8 src2 src1 src0 0 0 0 r/w r/w r/w sampling control 2 to 0 select sampling rate. 000: sampling rate 1/16 001: sampling rate 1/5 010: sampling rate 1/7 011: sampling rate 1/11 100: sampling rate 1/13 101: sampling rate 1/17 110: sampling rate 1/19 111: sampling rate 1/27 7 c/a 0 r/w communication mode selects whether the sci operates in the asynchronous or synchronous mode. 0: asynchronous mode 1: synchronous mode section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 592 of 1458 rej09b0033-0300 bit bit name initial value r/w description 6 chr 0 r/w character length selects seven-bit or eight-bit data. this bit is only valid in asynchronous mode. in synchronous mode, the data length is always eight bits, regardless of the chr setting. 0: eight-bit data 1: seven-bit data * note: * when seven-bit data is selected, the msb (bit 7) in scftdr is not transmitted. 5 pe 0 r/w parity enable selects whether to add a parity bit to transmit data and to check the parity of receive data. this setting is only valid in asynchronous mode. in synchronous mode, parity bit addition and checking is not performed, regardless of the pe setting. 0: parity bit not added or checked 1: parity bit added and checked note: * when pe is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (o/e) setting. receive data parity is checked according to the even/odd (o/e) mode setting. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 593 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 o/e 0 r/w parity mode selects even or odd parity when parity bits are added and checked. the o/e setting is used only when the pe is set to 1 to enable parity addition and check. the o/e setting is ignored when parity addition and check is disabled. 0: even parity * 1 1: odd parity * 2 notes: 1. if even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. if odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 594 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 stop 0 r/w stop bit length selects one or two bits as the stop bit length. in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. this setting is only valid in asynchronous mode. in synchronous mode, this setting is invalid since stop bits are not added. 0: one stop bit * 1 1: two stop bits * 2 notes: 1. in transmitting, a single bit of 1 is added at the end of each transmitted character. 2. in transmitting, two bits of 1 are added at the end of each transmitted character. 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 0 cks1 cks0 0 0 r/w r/w clock select 1 and 0 these bits select the internal clock source of the on- chip baud rate generator. 00: p 01: p /4 10: p /16 11: p /64 note: in synchronous mode, bits other than cks1 and cks0 are fixed 0. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 595 of 1458 rej09b0033-0300 18.3.6 serial control register (scscr) scscr is a 16-bit readable/writable register that operates the sci transmitter/receiver, enables/disables interrupt requests, and se lects the transmit/receive clock source. bit bit name initial value r/w description 15 tdrqe 0 r/w transmit data transfer request enable selects whether to iss ue the transmit-fifo-data- empty interrupt request or dma transfer request when tie = 1 and transmit fifo empty interrupt is generated at the transmission. 0: interrupt request is issued to cpu 1: transmit data transfer request is issued to dmac 14 rdrqe 0 r/w receive data transfer request enable selects whether to issue the receive-fifo-data-full interrupt or dma transfer request when rie = 1 and receive fifo data full interrupt is generated at the reception. 0: interrupt request is issued to cpu 1: receive data transfer request is issued to dmac 13,12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 tsie 0 r/w transmit data stop interrupt enable enables or disables the generation of the transmit- data-stop interrupt requested when the tse bit in scfcr is enabled and the tsf flag in scssr is set to 1. 0: the transmit-data-stop-interrupt disabled * 1: the transmit-data-stop-interrupt enabled note: * the transmit data stop interrupt request is cleared by reading the tsf flag after it has been set to 1, then clearing the flag to 0, or clearing the tsie bit to 0. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 596 of 1458 rej09b0033-0300 bit bit name initial value r/w description 10 erie 0 r/w receive error interrupt enable enables or disables the generation of a receive-error (framing error/parity error) interrupt requested when the er flag in scssr is set to 1. 0: the receive-error interrupt disabled * 1: the receive-error interrupt enabled note: * the receive-error interrupt request is cleared by reading the er flag after it has been set to 1, then clearing the flag to 0, or clearing the erie bit to 0. 9 brie 0 r/w break interrupt enable enables or disables the generation of break-receive interrupt requested when the brk flag in scssr is set to 1. 0: the break-receive interrupt disabled * 1: the break receive interrupt enabled note: * the break-receive interrupt request is cleared by reading the brk flag after it has been set to 1, then clearing the flag to 0, or clearing the brie bit to 0. 8 drie 0 r/w receive data ready interrupt enable disables or enables the generation of receive-data- ready interrupt when the dr flag in scssr is set to 1. 0: the receive-data-ready interrupt disabled 1: the receive-data-ready interrupt enabled note: * the receive-data-ready interrupt request is cleared by reading the dr flag after it has been set to 1, then clearing the flag to 0, or clearing the drie bit to 0. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 597 of 1458 rej09b0033-0300 bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable enables or disables the transmit-fifo-data-empty interrupt requested when the tdfe flag of scssr is set to 1. 0: transmit-fifo-data-empty interrupt request disabled * 1: transmit-fifo-data-empty interrupt request enabled note: * the transmit-fifo-data empty interrupt request can be cleared by writing the greater number of transmit data than the specified number of transmission triggers to scftdr and by clearing tdfe to 0 after reading 1 from tdfe, or can be cleared by clearing tie to 0. 6 rie 0 r/w receive interrupt enable enables or disables the receive-fifo-data-full interrupt requested when the rdf flag of scssr is set to1. 0: receive-fifo-data-full interrupt request disabled * 1: receive-fifo-data-fu ll interrupt request enabled note: * the receive-fifo- data -full interrupt request can be cleared by reading the rdf flag after it has been set to 1, then clearing the flag to 0, or by clearing the rie bit to 0. 5 te 0 r/w transmit enable enables or disables the scif serial transmitter. 0: transmitter disabled 1: transmitter enabled * note: * the serial mode register (scsmr) and fifo control register (scfcr) should be set to select the transmit format and reset the transmit fifo before setting the te bit to 1. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 598 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 re 0 r/w receive enable enables or disables the scif serial receiver. 0: receiver disabled * 1 1: receiver enabled * 2 notes: 1. clearing re to 0 does not affect the receive flags (dr, er, brk, rdf, fer, per, and orer). these flags retain their previous values. 2. the serial mode register (scsmr) and fifo control register (scfcr) should be set to select the receive format and reset the receive fifo before setting the re bit to 1. 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 cke1 cke0 0 0 r/w r/w clock enable 1and 0 these bits select the scif clock source. the bits cke1 and cke0 should be set before selecting the scif operating mode by scsmr. 00: internal clock, sck pin used for input pin (input signal is ignored) * 1 01: internal clock, sck pin used for synchronous clock output * 2 10: external clock, sck pin used for clock input * 3 11: external clock, sck pin used for clock input * 3 notes: 1. when the data sampling is executed using on- chip baud rate generator, cke1 and cke0 should be set to 00. 2. in synchronous mode, a clock with a frequency equal to the bit rate is output. when the channel 0 is used as the irda interface, cke1 and cke0 should be set to 01. 3. in asynchronous mode, input the clock which is appropriate for the sampling rate. for example, when the sampling rate is 1/16, input the clock frequency 8 times the bit rate. when the external clock is not input, cke1 and cke0 should be set to 00. when the sck pin is set as an i/o port pin, cke1 and cke0 should be set to 00. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 599 of 1458 rej09b0033-0300 18.3.7 fifo error count register (scfer) scfer is a 16-bit read-only register that indicates the number of receive data errors (framing error/parity error). bit bit name initial value r/w description 15,14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 11 10 9 8 per5 per4 per3 per2 per1 per0 0 0 0 0 0 0 r r r r r r parity error indicates the number of dat a, in which parity errors are generated, in receive data stored in the receive fifo data register (scfrdr) in asynchronous mode. bits 13 to 8 indicate the number of data with parity errors after the er bit in scssr is set. if all 64-byte receive data in scfrdr have parity errors, bits per5 to per0 indicate 0s. 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 4 3 2 1 0 fer5 fer4 fer3 fer2 fer1 fer0 0 0 0 0 0 0 r r r r r r framing error indicates the number of data, in which framing errors are generated, in receive data stored in the receive fifo data register (scfrdr) in asynchronous mode. bits 5 to 0 indicate the number of data with framing errors after the er bit in scssr is set. if all 64-byte receive data in scfrdr have framing errors, bits fer5 to fer0 indicate 0s. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 600 of 1458 rej09b0033-0300 18.3.8 serial status register (scssr) scssr is a 16-bit readable/writable register th at indicates scif states. the orer, tsf, er, tdfe, brk, rdf, or dr flag cannot be set to 1. th ese flags can be cleared to 0 only if they have first been read (after being set to 1). the flags tend, fer, and per are read-only bits and cannot be modified. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 orer 0 r/(w) * overrun error flag indicates that the overrun error occurred during reception. this bit is valid only in asynchronous mode. 0: indicates during reception, or reception has been completed without any error * 1 [clearing conditions] power-on reset, manual reset writing 0 after reading orer = 1 1: indicates that the overrun error is generated during reception * 2 [setting condition] when receive fifo is full and the next serial data reception is completed notes: 1. when the re bit in scscr is cleared to 0, the orer flag is not affected and retains its previous state. 2. scfrdr holds the data received before the overrun error, and newly received data is lost. when orer is set to 1, subsequent serial data reception cannot be carried out. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 601 of 1458 rej09b0033-0300 bit bit name initial value r/w description 8 tsf 0 r/(w) * transmit data stop flag indicates that the number of transmit data matches the value set in sctdsr. 0: transmit data number does not match the value set in sctdsr [clearing conditions] ? power-on reset, manual reset ? writing 0 after reading tsf = 1 1: transmit data number matches the value set in sctdsr 7 er 0 r/(w) * receive error indicates that a framing error or parity error occurred during reception in asynchronous mode. * 1 0: receive is normally completed without any framing or parity error [clearing conditions] power-on reset, manual reset er is read as 1, then written to with 0. 1: a framing error or a parity error has occurred during receiving [setting conditions] ? the stop bit is 0 after checking whether or not the last stop bit of the receiv ed data is 1 at the end of one-data receive. * 2 ? the total number of 1's in the received data and in the parity bit does not match the even/odd parity specification specified by the o/ e bit in the scsmr. notes: 1. indicates clearing the re bit to 0 in scscr does not affect the er bit, which retains its previous value. even if a receive error occurs, the received data is transferred to scfrdr and the receive operation is continued. whether or not the data read from scrdr includes a receive error can be detected by the fer and per bits in scssr. 2. n the stop mode, only the first stop bit is checked; the second stop bit is not checked. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 602 of 1458 rej09b0033-0300 bit bit name initial value r/w description 6 tend 1 r transmit end indicates that when the last bit of a serial character was transmitted, the scftdr did not contain valid data, so transmission has ended. 0: transmission is in progress [clearing condition] data is written to scftdr. 1: end of transmission [setting condition] scftdr contains no transmit data when the last bit of a one- byte serial character is transmitted. 5 tdfe 1 r/(w) * transmit fifo data empty indicates that data is transferred from the transmit fifo data register (scftdr) to the transmit shift register (sctsr), the number of data in scftdr becomes less than the number of transmission triggers specified by the ttrg1 and ttrg0 bits in the fifo control register (scfcr), and writing the transmit data to scftdr is enabled. 0: the number of transmit data written to scftdr is greater than the specified number of transmission triggers [clearing condition] data exceeding the specified number of transmission triggers is written to scftdr, software reads tdfe after it has been set to 1, then writes 0 to tdfe. 1: the number of transmission data in scftdr becomes less than the specified number of transmission triggers [setting conditions] ? power-on reset, manual reset ? the number of transmission data in scftdr becomes less than the specified number of transmission triggers as a result of transmission * note: * since scftdr is a 64-byte fifo register, the maximum number of data which can be written when tdfe is 1 is "64 minus the specified number of transmission triggers". if attempted to write additional data, the data is ignored. the number of data in scftdr is indicated by scfdr. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 603 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 brk 0 r/(w) * break detection indicates that a break signal is detected in received data in asynchronous mode. 0: no break signal is being received [clearing conditions] ? power-on reset, manual reset ? brk is read as 1, then written to with 0 1: a break signal is received * [setting conditions] data including a framing error is received ? a framing error with space 0 occurs in the subsequent received data note: * when a break is detected, transfer of the received data (h'00) to scfrdr stops after detection. when the break ends and the receive signal becomes mark 1, the transfer of the received data resumes. 3 fer 0 r framing error indicates a framing error in the data read from the receive fifo data register (scfrdr) in asynchronous mode. 0: no framing error occurred in the data read from scfrdr [clearing conditions] ? power-on reset, manual reset ? no framing error is present in the data read from scfrdr 1: a framing error occurred in the data read from scfrdr [setting condition] ? a framing error is present in the data read from scfrdr section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 604 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 per 0 r parity error indicates a parity error in the data read from the receive fifo data register (scfrdr) in asynchronous mode. 0: no parity error occurred in the data read from scfrdr [clearing conditions] ? power-on reset, manual reset ? no parity error is present in the data read from scfrdr 1: a parity error occurred in the data read from scfrdr [setting condition] ? a parity error is present in the data read from scfrdr section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 605 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 rdf 0 r/(w) * receive fifo data full indicates that received data is transferred to the receive fifo data register (scfrdr), the number of data in scfrdr becomes more than the number of receive triggers specified by the rtrg1 and rtrg0 bits in scfcr. 0: the number of transmit data written to scfrdr is less than the specified number of receive triggers [clearing conditions] ? power-on reset, manual reset ? scfrdr is read until the number of receive data in scfrdr becomes less than the specified number of receive triggers, and rdf is read as 1, then written to with 0. 1: the number of receive data in scfrdr is more than the specified number of receive triggers [setting condition] the number of receive data which is greater than the specified number of receive triggers is being stored to scfrdr. * note: * since scftdr is a 64-byte fifo register, the maximum number of data which can be read when rdf is 1 is the specified number of receive triggers. if attempted to read after all data in scfrdr have been read, the data is undefined. the number of receive data in scfrdr is indicated by the lower bits of scftdr. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 606 of 1458 rej09b0033-0300 bit bit name initial value r/w description 0 dr 0 r/(w) * receive data ready indicates that the rece ive fifo data register (scfrdr) stores the data which is less than the specified number of receive triggers, and that next data is not yet received after 15 etu has elapsed from the last stop bit in asynchronous mode. 0: receive is in progress, or no received data remains in scfrdr after the receive ended normally. [clearing conditions] (initial value) ? power-on reset, manual reset ? all receive data in scfrdr is read, and dr is read as 1, then written to with 0. 1: next receive data is not received [setting condition] scfrdr stores the data which is less than the specified number of receive triggers, and that next data is not yet received after 15 etu has elapsed from the last stop bit. * note: * this is equivalent to 1.5 frames with the 8-bit 1-stop-bit format. (etu: element time unit) note: * the only value that can be writ ten is 0 to clear the flag. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 607 of 1458 rej09b0033-0300 18.3.9 bit rate register (scbrr) scbrr is an eight-bit readable/writable register that , together with the baud rate generator clock source selected by the cks1 and cks0 bits in th e serial mode register (scsmr), determines the serial transmit/receive bit rate. bit bit name initial value r/w description 7 to 0 scbrd7 to scbrd0 h'ff r/w bit rate set the scbrr setting is calculated as follows: asynchronous mode: 1. when sampling rate is 1/16 n = p 32 2 2n-1 b 10 6 - 1 2. when sampling rate is 1/5 n = p 10 2 2n-1 b 10 6 - 1 3. when sampling rate is 1/11 n = p 22 2 2n-1 b 10 6 - 1 4. when sampling rate is 1/13 n = p 26 2 2n-1 b 10 6 - 1 5. when sampling rate is 1/27 n = p 54 2 2n-1 b 10 6 - 1 synchronous mode: n = p 4 2 2n-1 b 10 6 - 1 section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 608 of 1458 rej09b0033-0300 b: bit rate (bits/s) n: scbrr setting for baud rate generator asynchronous mode: 0 n 255 synchronous mode: 1 n 255 p : peripheral module operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) scsmr settings n clock source cks1 cks0 0 p 0 0 1 p /4 0 1 2 p /16 1 0 3 p /64 1 1 find the bit rate error in asynchronous mode by the following formula: 1. when sampling rate is 1/16 error (%) = p 10 6 (1+n) b 32 2 2n-1 - 1 100 2. when sampling rate is 1/5 error (%) = p 10 6 (1+n) b 10 2 2n-1 - 1 100 3. when sampling rate is 1/11 error (%) = p 10 6 (1+n) b 22 2 2n-1 - 1 100 4. when sampling rate is 1/13 error (%) = p 10 6 (1+n) b 26 2 2n-1 - 1 100 5. when sampling rate is 1/27 error (%) = p 10 6 (1+n) b 58 2 2n-1 - 1 100 section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 609 of 1458 rej09b0033-0300 18.3.10 fifo control register (scfcr) scfcr is a 16-bit readable/writable register that resets the number of data in the transmit and receive fifo registers, sets the nu mber of trigger data, and contains an enable bit for the loop back test. bit bit name initial value r/w description 15 tse 0 r/w transmit data stop enable enables or disables transm it data stop function. this function is enabled only in asynchronous mode. since this function is not supported in synchronous mode, clear this bit to 0 in synchronous mode. 0: transmit data stop function disabled 1: transmit data stop function enabled 14 tcrst 0 r/w transmit count reset clears the transmit count to 0. this bit is available while the transmit data stop function is enabled. 0: transmit count reset disabled * 1: transmit count reset enabled (cleared to 0) note: * the transmit count is reset (cleared to 0) by a power-on reset or manual reset. 13 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 rstrg2 rstrg1 rstrg0 0 0 0 r/w r/w r/w trigger of the rts output active 2 to 0 the rts signal goes to high, when the number of receive data count stored in the receive fifo data register (scfrdr) is increased more than the number of setting triggers listed below. 000: 63 001: 1 010: 8 011: 16 100: 32 101: 48 110: 54 111: 60 section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 610 of 1458 rej09b0033-0300 bit bit name initial value r/w description 7 6 rtrg1 rtrg0 0 0 r/w r/w trigger of the number of receive fifo data 1, 0 set the number of receive data which sets the receive data full (rdf) flag in the serial status register (scssr). these bits set the rdf flag when the number of receive data stored in the receive fifo data register (scfrdr) is increased more than the number of setting triggers listed below. 00: 1 01: 16 10: 32 11: 48 5 4 ttrg1 ttrg0 0 0 r/w r/w trigger of the number of transmit fifo data 1, 0 set the number of remaining transmit data which sets the transmit fifo dat a register empty (tdfe) flag in the serial status register (scssr). these bits set the tdfe flag when the number of transmit data in the transmit fifo data register (scftdr) is decreased less than the number of setting triggers listed below. 00: 32 (32) 01: 16 (49) 10: 2 (62) 11: 0 (64) note: * values in brackets mean the number of empty bytes in scftdr when the tdfe is set. 3 mce 0 r/w modem control enable enables the modem control signals cts and rts . 0: disables the modem signal * 1: enables the modem signal note: * the cts is fixed to active 0 regardless of the input value, and the rts is also fixed to 0. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 611 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 tfrst 0 r/w transmit fifo data register reset cancels the transmit data in the transmit fifo data register and resets the data to the empty state. 0: disables reset operation * 1: enables reset operation note: * the reset is executed in a power-on reset or a manual reset. 1 rfrst 0 r/w receive fifo data register reset cancels the receive data in the receive fifo data register and resets the data to the empty state. 0: disables reset operation * 1: enables reset operation note: * the reset is executed in a power-on reset or a manual reset. 0 loop 0 r/w loop back test internally connects the transmit output pin (txd) and receive input pin (rxd) and enables the loop back test. 0: disables the loop back test 1: enables the loop back test section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 612 of 1458 rej09b0033-0300 18.3.11 fifo data count register (scfdr) scfdr is a 16-bit register which indicates the number of data st ored in the receive fifo data register (scfrdr). the scfdr is always read from the cpu. the bits 14 to 8 of this register indicate the number of transmit data items stored in the scftdr that have not yet been transmitted. the bits 6 to 0 of this register indicate the numbe r of receive data items stored in the scfrdr. bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 13 12 11 10 9 8 t6 t5 t4 t3 t2 t1 t0 0 0 0 0 0 0 0 r r r r r r r these bits indicate the number of non-transmitted data stored in the scft dr. the h'00 means no transmit data, and the h'40 means that the full of transmit data are stored in the scftdr. 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 5 4 3 2 1 0 r6 r5 r4 r3 r2 r1 r0 0 0 0 0 0 0 0 r r r r r r r these bits indicate the number of receive data stored in the scfrdr. t he h'00 means no receive data, and the h'40 means t hat the full of receive data are stored in the scfrdr. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 613 of 1458 rej09b0033-0300 18.3.12 transmit data stop register (sctdsr) sctdsr is an 8-bit readable/writable register that sets the number of data to be transmitted. this register is available when the tse bit in the fifo control register (scfcr) is enabled. the transmit operation stops after all data set by this regi ster have been transmitted. settable values are h'00 (1 byte) to h'ff (256 bytes). the initial value of this register is h'ff. 18.4 operation for serial communication, the scif has asynchronous mode in which characters are synchronized individually and synchronous mode in which synchronization is achieved with clock pulses. the scif has the 64-byte fifo buffer for both transmission and recep tion, reduces an overhead of the cpu, and enables continuous high-speed communication. 18.4.1 asynchronous mode operation in asynchronous mode is described below. the transmission and recep tion format is selected in the serial mode register (scsmr), as listed in table 18.2. the clock source of scif is determined by the combination of cke1 and cke0 bits in the serial control register (scscr). ? data length is selectable from seven or eight bits. ? parity and multiprocessor bits are selectable. so is the stop bit length (one or two bits). the combination of the preceding selections constitutes the communication format and character length. ? in receiving, it is possible to detect framing erro rs, parity errors , overrun errors, receive fifo data full, receive data ready, and breaks. ? the number of stored data fo r both the transmit an d receive fifo registers is displayed. ? clock source: internal clock/external clock ? internal clock: scif operates using the on-chip baud rate generator ? external clock: the clock appropriate for the sampling rate should be input. for example, when the sampling rate is 1/16, input the clock frequency 8 times the bit rate. (the internal baud rate generator should not be used.) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 614 of 1458 rej09b0033-0300 table 18.2 scsmr settings and scif transmit/receive scsmr settings scif transmit/receive bit 6 bit 5 bit 3 chr pe stop mode data length multi- processor bit parity bit stop bit length 0 1 bit 0 1 not set 2 bits 0 1 bit 0 1 1 8-bit data set 2 bits 0 1 bit 0 1 not set 2 bits 0 1 bit 1 1 1 asynchro- nous mode 7-bit data not set set 2 bits 18.4.2 serial operation (1) transmit/receive formats table 18.3 lists eight communication formats that can be selected. the format is selected by settings in the serial mode register (scsmr). section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 615 of 1458 rej09b0033-0300 table 18.3 serial transmit/receive formats scsmr bits serial transmit /receive format and frame length chr pe stop 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 start 8-bit data stop 0 0 1 start 8-bit data stop stop 0 1 0 start 8-bit data p stop 0 1 1 start 8-bit data p stop stop 1 0 0 start 7-bit data stop 1 0 1 start 7-bit data stop stop 1 1 0 start 7-bit data p stop 1 1 1 start 7-bit data p stop stop (2) clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as th e sci's serial clock, according to the setting of the cke bit in the serial control register (scscr). when an external clock is input at the sck pin, the clock appropriate for the sampling rate should be input. for example, when the sampling rate is 1/16, the clock frequency should be 8 times the bit rate used. (3) transmitting and receiving data (scif initialization) before transmitting or receiving, cl ear the te and re bits to 0 in scscr, then initialize the scif as follows. when changing the communication format, always cl ear the te and re bits to 0 before following the procedure given below. clearing te to 0 ini tializes the transmit shift register (sctsr). clearing te and re to 0, however, does not initialize the serial status register (scssr), transmit fifo data register (scftdr), or receive fifo data register (scfrdr), which retain their previous contents. clear te to 0 after all transmit data are transmitted and the tend bit in the scssr is set. the transmitting data enters the high impedance state after clearing to 0 although the bit can be cleared section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 616 of 1458 rej09b0033-0300 to 0 in transmitting. set the tfrst bit in the scfcr to 1 and reset the scftdr before te is set again to start transmission. when an external clock is used, the clock should not be stopped during initialization or subsequent operation. scif operation becomes unreliable if the clock is stopped. figure 18.2 is a sample flowchart for initializing the scif. initialization (1) set the clock selection in scscr. be sure to clear bits rie tie, te, and re to 0. (2) set the operating clock source in scsmr. (3) write a value corresponding to the bit rate into scbrr. (not necessary if an external clock is used.) (4) wait at least one bit interval, then set the te bit or re bit in scsr to 1. also set the rie and tie bits. setting the te and re bits enables the txd and rxd pins to be used. when transmitting, the scif will go to the mark state; when receiving, it will go to the idle state. clear te and re bits in scscr to 0 set tfrst and rfrst bits in scfcr to 1 (1) (2) (3) (4) 1-bit interval elapsed? set rtrg1, rtrg0, ttrg1, and ttrg0 in scfcr clear tfrst and rfrst bits to 0 set te and re bits in scscr to 1,and set rie, and tie bits set operating clock source in scsmr yes no set value in scbrr set cke1 and cke0 bits in scscr2 (leaving te and re bits cleared to 0) end wait figure 18.2 sample scif initialization flowchart section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 617 of 1458 rej09b0033-0300 (4) transmitting and receiving da ta (serial data transmission) figure 18.3 shows a sample serial transmission flowchart. after sc if transmission is enabled, use the following procedure to perform serial data transmission. start transmission read tdfe bit in scssr tend= 1? read tend bit in scssr2 clear te bit in scscr2 to 0 set scpdr2 and scpcr2 yes no tdfe= 1? no all data transmitted? no yes yes break output? yes no write transmit data (16 - transmit trigger set number) to scftdr, read 1 from tdfe bit and tend flag in scssr, then clear to 0 end of transmission (1) scif status check and transmit data write: read serial status register (scssr) and check that the tdfe flag is set to 1, then write transmit data to the transmit fifo data register (scftdr), read 1 from the tdfe and tend flags, then clear these flags to 0. the number of transmit data bytes that can be written is 64 - (transmit trigger set number). (2) serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, then write data to scftdr2, and then clear the tdfe flag to 0. (3) break output at the end of serial transmission: to output a break in serial transmission, set the port sc data register (scpdr) and port sc control register (scpcr), then clear the te bit to 0 in the serial control register (scscr). in steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in scftdr indicated by the upper 8 bits of the fifo data count set register 2 (scfdr). (1) (2) (3) figure 18.3 sample serial transmission flowchart section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 618 of 1458 rej09b0033-0300 in serial transmission, the scif operates as described below. 1. when data is written into the transmit fifo data register (scftdr), the scif transfers the data from scftdr to the transmit shift register (sctsr) and starts tran smitting. confirm that the tdfe flag in the serial status register (sc ssr) is set to 1 before writing transmit data to scftdr. the number of data bytes that can be written is (64 ? transmit trigger setting). 2. when data is transferred from scftdr to sctsr and transmission is started, consecutive transmit operations are performed until there is no transmit data left in scftdr. when the number of transmit data bytes in scftdr falls below the transmit trigger number set in the fifo control register (scfcr), the tdfe flag is se t. if the tie bit in the serial control register (scsr) is set to 1 at this time, a transmit-fi fo-data-empty interrupt request is generated. when the number of transmit data matches the data set in the transmit data stop register (sctdsr) while the transmit data stop function is used, the transmit operation is stopped and the tsf flag in the serial status register (scssr) is set. when the tsie bit in the serial control register (scscr) is set to 1, transmit data st op interrupt request is generated. a common interrupt vector is assigned to the transmit-fifo-data-empty interrupt and the transmit-data- stop interrupt. the serial transmit data is sent from the txd pin in the following order. a. start bit: one-bit 0 is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first order. c. parity bit: one parity bit (even or odd parity) is output. (a format in which a parity bit is not output can also be selected.) d. stop bit(s): one- or two-bit 1s (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the scif checks the scftdr transmit data at the timing for sending the stop bit. if data is present, the data is transferred from scftdr to sctsr, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data, the tend flag in the se rial status register (s cssr) is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 619 of 1458 rej09b0033-0300 figure 18.4 shows an example of the operation for transmission in asynchronous mode. 01 1 1 0/1 0 1 tdfe tend parity bit parity bit serial data start bit data stop bit start bit data stop bit idle state (mark state) transmit-fifo- data-empty interrupt request data written to scftdr and tdfe flag read as 1 then cleared to 0 by transmit- fifo-data-empty interrupt handler one frame d 0 d 1 d 7 d 0 d 1 d 7 0/1 transmit-fifo- data-empty interrupt request figure 18.4 example of transmit operation (example with 8-bit data, parity, one stop bit) ? transmit data stop function when the value of the sctdsr register and th e number of transmit data match, transmit operation stops. setting the tsie bit (interrupt enable bit) allows the generation of an interrupt and activation of dmac. figure 18.5 shows an example of the operation for transmit data stop function. tsf flag 0 d0 d1 d6 d7 0/1 0 d0 d1 d6 d7 0/1 start bit transmit data txd parity bit stop bit start bit figure 18.5 example of transmit data stop function section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 620 of 1458 rej09b0033-0300 figure 18.6 shows the transmit data stop function flowchart. start of transmission end of transmission no set transmit data stop number in sctdsr set tse and tsie bits in scfcr to 1 read tsf bit in scssr; if it is 1, clear to 0 after reading 1 from tsf bit yes tsf = 1 ? 1. set the transmit data stop number in sctdsr, then set the tse bit in scfcr to 1.when an interrupt is enabled, also set the tsie bit to 1. 2. if the tsf bit in scssr is set to 1, clear it to 0 after reading 1. when transmit data is written to scftdr in this state, transmit operation is started. 3. if the tsf bit is set to 1 (transmit data stop number is matched with transmit data number), transmit operation is stopped. if the tsie bit is set to 1, an interrupt is generated. serial transmission continuation procedure: set the tcrst bit in scfcr to 1, clear transmit count, and clear the tcrst bit to 0. then follow steps 1, 2, and 3. 1 2 3 figure 18.6 transmit data stop function flowchart section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 621 of 1458 rej09b0033-0300 (5) transmitting and receiving data (serial data reception) figures 18.7 and 18.8 show sample serial receptio n flowcharts. after scif reception is enabled, use the following procedure to perform serial data reception. start reception read per and fer flags in scssr all data received? end reception no yes per or fer = 1? rdf = 1? yes yes clear re bit in scscr to 0 no no read rdf flag in scssr error processing read receive data in scfrdr, and clear rdf flag in scssr to 0 (1) receive error handling and break detection: read the dr, er, and brk flags in scssr2 to identify any error, perform the appropriate error handling, then clear the dr, er, and brk flags to 0. in the case of a framing error, a break can also be detected by reading the value of the rxd2 pin. (2) scif status check and receive data read : read the serial status register (scssr) and check that rdf = 1, then read the receive data in the receive fifo data register (scfrdr), read 1 from the rdf flag, and then clear the rdf flag to 0. (3) serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of receive data bytes from scfrdr, read 1 from the rdf flag, then clear the rdf flag to 0. the number of receive data bytes in scfrdr can be ascertained by reading the lower bits of scfdr. (1) (2) (3) figure 18.7 sample serial reception flowchart (1) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 622 of 1458 rej09b0033-0300 error processing end brk= 1? dr= 1? er = 1? yes yes clear dr, er, brk flags in scssr to 0 no no no receive error processing break processing read receive data in scfrdr 1. whether a framing error or parity error has occurred in the receive data read from scfrdr can be ascertained from the fer and per bits in scssr. 2. when a break signal is received, receive data is not transferred to scfrdr while the brk flag is set. however, note that the last data in scfrdr is h'00 and the break data in which a framing error occurred is stored. figure 18.8 sample serial reception flowchart (2) in serial reception, the scif operates as described below. 1. the scif monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr in lsb-to-msb order. 3. the parity bit and stop bit are received. after receiving these bits, the scif carries out the following checks. a. stop bit check: the scif checks whether the st op bit is 1. if there are two stop bits, only the first is checked. b. the scif checks whether receive data can be transferred from the receive shift register (scrsr) to scfrdr. c. break check: the scif checks that the brk fl ag is 0, indicating that the break state is not set. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 623 of 1458 rej09b0033-0300 if all the above checks are passed, the receive data is stored in scfrdr. note: even when the receive error (framing error/parity error) is generated, receive operation is continued. 4. if the rie bit in scscr is set to 1 when the rdf flag changes to 1, a receive-fi fo-data-full interrupt request is generated. if the erie bit in scscr is set to 1 when the er flag changes to 1, a receive-error interrupt request is generated. if the brie bit in scscr is set to 1 when th e brk flag changes to 1, a break reception interrupt request is generated. if the drie bit in scscr is set to 1 when the dr flag changes to 1, a receive data ready interrupt request is generated. note that a common vector is assi gned to each interrupt source. figure 18.9 shows an example of the operation for reception. rdf fer receive-error interrupt request generated by receive error one frame data read and rdf flag read as 1 then cleared to 0 by receive-fifo-data-ful interrupt handler receive-fifo-data-full interrupt request 01 1 1 0/1 0 1 parity bit parity bit serial data start bit data stop bit start bit data stop bit idle state (mark state) d 0 d 1 d 7 d 0 d 1 d 7 0/1 figure 18.9 example of scif receive operation (example with 8-bit data, parity, one stop bit) when modem control is enabled, transmission can be stopped and restarte d in accordance with the cts input value. when cts is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. when cts is set to 0, the next transmit data is output starting from the start bit. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 624 of 1458 rej09b0033-0300 figure 18.10 shows an example of the operation when modem control is used. cts transmission stops when cts goes high transmission starts again when cts goes low 0 d0 d1 d6 d7 0/1 0 d0 d1 d6 d7 0/1 start bit transmit data txd parity bit stop bit start bit figure 18.10 example of cts control operation when modem control is enabled, the rts signal goes high after th e number of receive fifo (scfrdr) has exceeded the number of rts output triggers. rts rts goes high when receive data is at least number of rts output trigger 0d0d1 d6d7 0/1 start bit transmit data txd parity bit stop bit rts goes low when receive data is less than number of rts output trigger figure 18.11 example of rts control operation 18.4.3 synchronous mode operation in synchronous mode is described below. the scif has 64-stage fifo buffers for both transmission and reception, reducing the cpu overhead and enabling fast, continuous communication to be performed. the operating clock source is se lected using the serial mode re gister (scsmr). the scif clock source is determined by the cke1 and cke0 b its in the serial control register (scscr). ? transmit/receive format: fixed 8-bit data ? indication of the number of data bytes stored in the transmit and receive fifo registers ? internal clock or external cloc k used as the scif clock source when the internal clock is selected: the scif operates on the baud rate generator clock and outputs a serial clock from sck pin. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 625 of 1458 rej09b0033-0300 when the external clock is selected: the scif operates on the external clock input through the sck pin. 18.4.4 serial operation in synchronous mode don't care don't care * * lsb msb note: * high in continuous transmission/reception serial data serial clock bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 one unit of transfer data (character or frame) figure 18.12 data format in synchronous communication in synchronous serial communication, data on the communication line is output from a falling edge of the serial clock to the next falling edge. data is guaranteed valid at the rising edge of the serial clock. in serial communication, each char acter is output starting with th e lsb and ending with the msb. after the msb is output, the communication line remains in the state of the msb. in synchronous mode, the scif receives data in sync hronization with the risi ng edge of the serial clock. (1) data transfer format a fixed 8-bit data format is used. no parity or multiprocessor bits are added. (2) clock an internal clock generated by the on-chip baud rate generator or an external clock input through the sck pin can be selected as the serial clock for the scif, according to the setting of the cke1 and cke0 bits in scscr. eight serial clock pulses are output in th e transfer of one character, and when no transmission/reception is performed, the clock is fixed high. however, when the operation mode is reception only, the sy nchronous clock output continues while th e re bit is set to 1. to fix the clock high every time one character is transferre d, write to the transmit fifo data register (scftdr) the same number of du mmy data bytes as the data bytes to be received and set the te and re bits to 1 at the same time to transmit the dummy data. when the specified number of data bytes are transmitted, the clock is fixed high. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 626 of 1458 rej09b0033-0300 (3) data transfer operatio ns (scif initialization) before transmitting and receiving data, it is necessa ry to clear the te and re bits in scscr to 0, then initialize the scif as described below. when the clock source, etc., is changed, the te an d re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the transmit shift register (sctsr) is initialized. note that clearing the te and re bits to 0 does not change the contents of scssr, scftdr, or sc frdr. the te bit should be cl eared to 0 after all transmit data has been sent and the tend bit in scssr has been set to 1. the te bit should not be cleared to 0 during transmission; if attempted, the txd pin will go to the high-impedance state. before setting te to 1 again to start transmission, the tfrs t bit in scfcr should first be set to 1 to reset scftdr. figure 18.13 shows sample scif initialization flowcharts. no yes wait end 1-bit interval elapsed? set transmit trigger number in ttrg1 and ttrg0 in scfcr, write transmit data exceeding transmit trigger setting number, and clear tdfe flag to 0 after reading 1 from it initialization clear te and re bits in scscr to 0 set tfrst bit in scfcr to 1 set cke1 and cke0 bits in scscr (leaving te and re bits cleared to 0) set c/a bit in scsmr to 1 set cks1 and cks0 bits set value in scbrr clear tfrst bit to 0 1. be sure to set the tfrst bit in scfcr to 1, to reset the fifos. 2. set the clock selection in scscr. be sure to clear bits rie, tie, te, and re to 0. 3. set the clock source selection in scsmr. 4. write a value corresponding to the bit rate into scbrr. 5. clear the tfrst bit in scfcr to 0. 6. set the transmit trigger number, write transmit data exceeding the transmit trigger setting number, and clear the tdfe flag to 0 after reading it. 7. wait one bit interval. 1 2 3 4 5 6 7 figure 18.13 sample scif initialization flowchart (1) (transmission) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 627 of 1458 rej09b0033-0300 no yes wait 1. be sure to set the rfrst bit in scfcr to 1, to reset the fifos. 2. set the clock selection in scscr. be sure to clear bits rie, tie, te, and re to 0. 3. set the clock source selection in scsmr. 4. write a value corresponding to the bit rate into scbrr. 5. clear the rfrst bit in scfcr to 0. 6. wait one bit interval. initialization clear te and re bits in scscr to 0 set rfrst bit in scfcr to 1 set cke1 and cke0 bits in scscr (leaving te and re bits cleared to 0) set c/a bit in scsmr to 1 set cks1 and cks0 bits set value in scbrr clear rfrst bit to 0 1-bit interval elapsed? end 1 2 3 4 5 6 figure 18.13 sample scif init ialization flowchart (2) (reception) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 628 of 1458 rej09b0033-0300 no yes wait 1. be sure to set the tfrst bit in scfcr to 1, to reset the fifos. 2. set the clock selection in scscr. be sure to clear bits rie, tie, te, and re to 0. 3. set the clock source selection in scsmr. 4. write a value corresponding to the bit rate into scbrr. 5. clear the tfrst and rfrst bits in scfcr to 0. 6. set the transmit trigger number, write transmit data exceeding the transmit trigger setting number, and clear the tdfe flag to 0 after reading it. 7. wait one bit interval. initialization clear te and re bits in scscr to 0 set tfrst and rfrst bits in scfcr to 1 set cke1 and cke0 bits in scscr (leaving te and re bits cleared to 0) set c/a bit in scsmr to 1 set cks1 and cks0 bits set value in scbrr clear tfrst and rfrst bits to 0 set transmit trigger number in ttrg1 and ttrg0 in scfcr, write transmit data exceeding transmit trigger setting number, and clear tdfe flag to 0 after reading 1 from it 1-bit interval elapsed? end 1 2 3 4 5 6 7 figure 18.13 sample scif initialization flowchart (3) (simultaneous transmi ssion and reception) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 629 of 1458 rej09b0033-0300 (4) data transfer operations (serial data transmission) figure 18.14 shows sample flowcharts for serial transmission. no yes 1. write the remaining transmit data to scftdr. 2. transmission is started when the te bit in scscr is set to 1. 3. after the end of transmission, clear the te bit to 0. start of transmission write remaining transmit data to scftdr set te bit in scscr when using transmit fifo data interrupt, set tie bit to 1 tend =1? clear te bit in scscr to 0 end of transmission 1 2 3 figure 18.14 sample serial transmission flowchart (1) (first transmission after initialization) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 630 of 1458 rej09b0033-0300 no yes no wait yes 1. set the transmit trigger number in scfcr. 2. write transmit data to scftdr, and clear the tdfe flag to 0 after reading 1 from it. 3. wait for one bit interval. 4. transmission is started when the te bit in scscr is set to 1. 5. after the end of transmission, clear the te bit to 0. start of transmission set transmit trigger number in ttrg1 and ttrg0 in scfcr write transmit data exceeding transmit trigger setting number, and clear tdfe flag to 0 after reading 1 from it 1-bit interval elapsed? set te bit in scscr when using transmit fifo data interrupt, set tie bit to 1 tend =1? clear te bit in scscr to 0 end of transmission 1 2 3 4 5 figure 18.14 sample serial transmission flowchart (2) (second and subsequent transmission) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 631 of 1458 rej09b0033-0300 (5) data transfer operations (serial data reception) figure 18.15 shows sample flow charts for serial reception. no yes 1. set the receive trigger number in scfcr. 2. reception is started when the re bit in scscr is set to 1. 3. read receive data while the rdf bit is 1. 4. after the end of reception, clear the re bit to 0. start of reception set receive trigger number in rtrg1 and rtrg0 in scfcr set re bit in scscr when using receive fifo data interrupt, set rie bit to 1 rdf =1? read receive trigger number of receive data bytes from scfrdr clear re bit in scscr to 0 end of reception 1 2 3 4 figure 18.15 sample serial reception flowchart (1) (first reception a fter initialization) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 632 of 1458 rej09b0033-0300 no yes no wait yes 1. set the receive trigger number in scfcr. 2. reset the receive fifo. 3. wait for one bit interval. 4. reception is started when the re bit in scscr is set to 1. 5. read receive data while the rdf bit is 1. 6. after the end of reception, clear the re bit to 0. start of reception set receive trigger number in rtrg1 and rtrg0 in scfcr set rfrst bit in scfcr to 1 clear rfrst bit in scfcr to 0 1-bit interval elapsed? set re bit in scscr when using receive fifo data interrupt, set rie bit to 1 rdf =1? read receive trigger number of receive data bytes from scfrdr clear re bit in scscr to 0 end of reception 1 2 3 4 5 6 figure 18.15 sample serial reception flowchart (2) (second and subsequent reception) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 633 of 1458 rej09b0033-0300 (6) data transfer operations (simultaneou s serial data transm ission and reception) figure 18.16 shows sample flowcharts for simu ltaneous serial transmission and reception. no yes no yes 1. set the receive trigger number in scfcr. 2. write the remaining transmit data to scftdr, and if there is receive data in the fifo, read receive data until there is less than the receive trigger setting number, read the tdfe and rdf bits in scssr, and if 1, clear to 0. 3. transmission/reception is started when the te and re bits in scscr are set to 1. the te and re bits must be set simultaneously. 4. after the end of transmission/reception, clear the te and re bits to 0. start of simultaneous transmission/reception set receive trigger number in rtrg1 and rtrg0 in scfcr write remaining transmit data to scftdr read tdfe and rdf bits in scssr tdfe =1? rdf =1? write 0 to tdfe and rdf bits in scssr after reading 1 from them set te and re bits in scscr simultaneously when using transmit fifo data interrupt, set tie bit to 1 when using receive fifo data interrupt, set rie bit to 1 tdfe =1? rdf =1? read receive trigger number of receive data bytes from scfrdr clear te and re bits in scscr to 0 end of transmission/reception 2 1 3 4 figure 18.16 sample simultaneous serial transmission and reception flowchart (1) (first transfer after initialization) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 634 of 1458 rej09b0033-0300 no yes yes no yes no wait 1. set the receive trigger number and transmit trigger number in scfcr. 2. reset the receive fifo and transmit fifo. 3. write transmit data to scftdr, and if there is receive data in the fifo, read receive data until there is less than the receive trigger setting number, read the tdfe and rdf bits in scssr, and if 1, clear to 0. 4. wait for one bit interval. 5. transmission/reception is started when the te and re bits in scscr are set to 1. the te and re bits must be set simultaneously. 6. after the end of transmission/reception, clear the te and re bits to 0. start of simultaneous transmission/reception set receive trigger number in rtrg1 and rtrg0 in scfcr, and set transmit trigger number in ttrg1 and ttrg0 set tfrst and rfrst bits in scfcr to 1 clear tfrst and rfrst bits in scfcr to 0 write transmit data to scftdr read tdfe and rdf bits in scssr tdfe =1? rdf =1? write 0 to tdfe and rdf bits in scssr after reading 1 from them 1-bit interval elapsed? set te and re bits in scscr simultaneously when using transmit fifo data interrupt, set tie bit to 1 when using receive fifo data interrupt, set rie bit to 1 tdfe =1? rdf =1? read receive trigger number of receive data bytes from scfrdr end of transmission/reception clear te and re bits in scscr to 0 1 2 3 4 5 6 figure 18.16 sample simultaneous serial transmission and reception flowchart (2) (second and subsequent transfer) section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 635 of 1458 rej09b0033-0300 18.5 interrupt sources and dmac in asynchronous mode, the scif supports six interrupts: transmit-fifo-data-empty, transmit data stop, receive-error, receive-fifo-data-full, break receive, and receive data ready. a common interrupt vector is assigned to each interrupt source. in synchronous mode, the scif supports two interrupts : transmit-fifo-data-empty and receive- fifo-data-full. table 18.4 shows the interrupt sources. the interrup t sources are enabled or disabled by means of the tie, rie, erie, brie, drie, and tsie bits in scscr. when the tdfe flag in scssr is set to 1, th e transmit-fifo-d ata-empty interrupt request is generated. when the tsf flag in scssr is set to 1, the transmit-data-stop interrupt request is generated. activating the dmac and transferring data can be performed by the transmit-fifo- data-empty interrupt and data stop interrupt requ ests. the dmac transfer request is automatically cleared when the number of data written to scftdr by the dmac is increased more than that of setting transmit triggers. when the rdf flag in scssr is set to 1, a recei ve-fifo-data-full interrupt request is generated. activating the dmac and transferring data can be performed by the receive-fifo-data-full interrupt request. the dmac transfer request is au tomatically cleared when receive data is read from scfrdr by the dmac until the number of receive data in scfrdr is decreased less than that of receive triggers. when executing the data transmission and reception, set the dmac, and then set scif after entered in the enabled state. the completion of the dma transfer is the completion of transmission and reception. for the dmac setti ng procedure, see section 10, direct memory access controller (dmac). an interrupt request is generated when the er flag in scssr is set to1; the brk flag in scssr is set to 1; the dr flag in scssr is set to 1; or the tsf flag in scssr is set to 1. a common interrupt vector is assigned to each interrupt sour ce. the activation of dmac and generation of an interrupt are not executed at the same time by the same source. when act ivating the dmac, carry out the following procedure. ? set the interrupt enable bits (tie, rie) that correspond to the interrupt sources used for activation of the dmac. clear the other interrupt enable bits (tsie, erie, brie, and drie) to 0. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 636 of 1458 rej09b0033-0300 table 18.4 scif interrupt sources interrupt source dmac activation interrupt initiated by receive error (er) or break (brk) not possible interrupt initiated by receive fifo data full flag (rdf) or data ready flag (dr) possible * 1 interrupt initiated by receive fifo data empty flag (tdfe) or transmit data stop flag (tsf) possible * 2 notes: 1. dmac can be activated only by the receive-fifo-data-full interrupt request. 2. dmac can be activated only by t he transmit-fifo-data-empty interrupt request. see section 7, exception handling, for priorities and the relationship with non-scif interrupts. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 637 of 1458 rej09b0033-0300 18.6 usage notes (1) scftdr writing and the tdfe flag the tdfe flag in the serial status register (sc ssr) is set when the number of transmit data bytes written in the transmit fifo data register (scftd r) has fallen below the transmit trigger number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr). after tdfe is set, transmit data up to the number of empty bytes in scft dr can be written, allowi ng efficient continuous transmission. however, if the number of data bytes written in scftdr is less than or equal to the transmit trigger number, the tdfe flag will be set to 1 again after being cleared to 0. the tdfe flag should therefore be cleared to 0 after a number of data bytes exceeding the transmit trigger number has been written to scftdr. the number of transmit da ta bytes in scftdr can be found in the bits 14 to 8 of the fifo data count set register (scfdr). (2) scfrdr reading and the rdf flag the rdf flag in the serial status register (scssr) is set when the number of receive data bytes in the receive fifo data register (scfrdr) has beco me equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr). after rdf is set, receive data equivalent to th e trigger number can be read from scfrdr, allowing efficient continuous reception. however, if the number of data bytes in scfr dr exceeds the trigger nu mber, the rdf flag will be set to 1 again after being cleared to 0. the rdf flag should therefore be cleared to 0 when 1 has been written to rdf after all receive data has been read. the number of receive data bytes in scfrdr can be found in the bits 6 to 0 of the fifo data count set register (scfdr). (3) break detection and processing break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break stat e the input from the rxd pin consists of all 0s, so the fer flag is set and the parity error flag (p er) may also be set. note that, al though transfer of receive data to scfrdr is halted in the break state, th e scif receiver continues to operate. section 18 serial communicati on interface with fifo (scif) rev. 3.00 jan. 18, 2008 page 638 of 1458 rej09b0033-0300 (4) receive data sampling ti ming and receive margin an example with a sampling rate 1/16 is give n. the scif operates on a base clock with a frequency of 8 times the transfer rate. in reception, the scif synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth base clock pulse. the timing is shown in figure 18.17. 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 base clock receive data (rxd) synchro- nization sampling timing data sampling timing 8 clocks 16 clocks start bit ? 7.5 clocks +7.5 clocks d0 d1 figure 18.17 receive data samplin g timing in asynchronous mode the receive margin in asynchron ous mode can therefore be expres sed as shown in equation (1). equation 1: m = 0.5 ? 1 2n d ? 0.5 n ? (l ? 0.5) f ? (1 + f) 100% ....................... (1) m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5, the receive margin is 46.8 75%, as given by equation (2). when d = 0.5 and f = 0: m = (0.5 ? 1/(2 16)) 100 % = 46.875 % ...................................................................................................... (2) this is a theoretical value. a reasonable margin to allow in system designs is 20% to 30%. section 19 infrared data association module (irda) ifirda0a_000020010900 rev. 3.00 jan. 18, 2008 page 639 of 1458 rej09b0033-0300 section 19 infrared data association module (irda) this lsi has an on-chip infrared data association (irda) interface that is based on the irda 1.0 system and can perform infrared communication. the irda is an optional module used for modulation and demodulation of signals for the scif_0 module, and it must always be used together with the scif_0 module. 19.1 features ? conforms to the irda 1.0 system ? asynchronous serial communication ? data length: 8 bits ? stop bit length: 1 bit ? parity bit: none ? on-chip 64-stage fifo buffers for bo th transmit and r eceive operations ? on-chip baud rate generator with selectable bit rates ? guard functions to protect the receiver during transmission ? clock supply halted to redu ce power consumption when not using the irda interface figure 19.1 shows a block diagram of the irda. scif_0 txd transfer clock rxd switching irda/scif irda irtx irrx modulation unit demodulation unit [legend] scif: serial communication interface with fifo figure 19.1 block diagram of irda section 19 infrared data association module (irda) rev. 3.00 jan. 18, 2008 page 640 of 1458 rej09b0033-0300 19.2 input/output pins table 19.1 shows the irda pin configuration. table 19.1 pin configuration name pin name i/o function irda receive data irrx input receive data input irda transmit data irtx output transmit data output note: clock input from the serial clock pin cannot be set in irda mode. 19.3 register description the irda has the following internal registers. re fer to section 37, list of registers, for more details on the addresses and states of these registers in each operating mode. ? irda mode register (scimr) 19.3.1 irda mode register (scimr) scimr selects irda or scif mode and selects the irda output pulse width. irda operates when the irmod bit is set to 1. when the irmod bit is cl eared to 0, irda can operate as an scif. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 irmod 0 r/w irda mode selects whether this module operates as an irda serial communication interface or as an scif. 0: operates as an scif 1: operates as an irda section 19 infrared data association module (irda) rev. 3.00 jan. 18, 2008 page 641 of 1458 rej09b0033-0300 bit bit name initial value r/w description 6 to 3 ick3 to ick0 all 0 r/w ou tput pulse division ratio 3 to 0 ? specifies the ratio for dividing the peripheral clock (p ) to generate the irclk clock pulse to be used for irda. irclk is obtained as follows: irclk = 1/(2n + 2) p n = value set by ick3 to ick0 2 psel 0 r/w output pulse width select selects an irda output puls e width that is 3/16 of the bit length for 115 kbps or 3/16 of the bit length for the selected baud rate. 0: pulse width is 3/ 16 of the bit length 1: pulse width is 3/16 of 115 kbps bit length for the baud rate selected by ick3 to ick0 1, 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. note: ? recommended value of irda for example, when the transfer rate in 115.2kbps, set the value (nb+1):(ni+1) = 2:1. setting (nb+1):(ni+1) = 2:1 (115.2 kbps) allo ws operation in synchronization while the scif module and irda module perform a synchronous operation. synchronous operation equalizes errors in the ir frame wh en such bit rate errors occur. use bit 2 (psel) in scimr as psel = 1 to adjust transfer and receive data. [legend] nb: the baud rate value in scif (scbrd7 to scbrd0 in scbrr) ni : the baud rate value in irda (ick3 to ick0 in scimr) b : bit rate (bits/s) setting example as p =33.1776mhz: nb nb+1 b ni ni+1 17 18 115.2 8 9 35 36 57.6 8 9 53 54 38.4 8 9 107 108 19.2 8 9 215 2196 9.6 8 9 section 19 infrared data association module (irda) rev. 3.00 jan. 18, 2008 page 642 of 1458 rej09b0033-0300 19.4 operation the irda module can perform infrared communication conforming to irda 1.0 by connecting infrared transmit/receive units. the serial communi cation interface unit in cludes a buffer in the transmit unit and the recei ve unit, allowing cpu overhead to be reduced and continuous high- speed communication to be performed. the irda module modifies irtx/ irrx transmit/receive data wave forms to satisfy the irda 1.0 specification for infr ared communication. in the irda 1.0 specification, co mmunication is first performed at a speed of 9600 bps, and the communication speed is changed. however, th e communication rate cannot be automatically changed in this module, so the communication sp eed should be confirmed, and the appropriate speed set for this module by software. 19.4.1 transmitting the waveforms of a serial output signal (uart frame) from the scif are modified and the signal is converted into the ir frame serial output signal by the irda module, as shown in figure 19.2. when serial data is 0, a pulse of 3/16 the ir frame bit width is generated and output. when serial data is 1, no pulse is output. 19.4.2 receiving received 3/16 ir frame bit-widt h pulses are demodulated and converted to a uart frame, as shown in figure 19.2. demodulation to 0 is performed for pulse output, and demodulation to 1 is performed for no pulse output. section 19 infrared data association module (irda) rev. 3.00 jan. 18, 2008 page 643 of 1458 rej09b0033-0300 01 0 1 00 1 1 0 1 01 01 0 01 1 0 1 uart frame start bit ir frame start bit bit cycle 3/16-bit cycle pulse width uart frame data ir frame data receive transmit stop bit stop bit figure 19.2 transmit/receive operation 19.4.3 data form at specification the data format of uart frames used for irda communication must be specified by the scif_0 registers. the uart frame has eight data bits, no parity bit, and one stop bit. irda communication is performed in asynchronous mode, and this mode must also be specified by the scif_0 registers. the sampling rate must be set to 1/16. when using irda, set the scif_0 operating clock by setting the cke1 and cke0 bits in the serial control register to 01. the irda communication rate is the same as th e scif_0 bit rate, which is specified by the scif_0 registers. for details on scif_0 re gisters, refer to section 18, serial communication in terface with fifo (scif). section 19 infrared data association module (irda) rev. 3.00 jan. 18, 2008 page 644 of 1458 rej09b0033-0300 section 20 i 2 c bus interface (iic) ifiic10a_000020020200 rev. 3.00 jan. 18, 2008 page 645 of 1458 rej09b0033-0300 section 20 i 2 c bus interface (iic) the i 2 c bus interface supports and provides a subset of the philips i 2 c bus (inter-ic bus) interface functions. the register configuration that controls the i 2 c bus differs partly from the philips configuration, however. figure 20.1 shows a block diagram of the i 2 c bus interface. figure 20.2 shows an example of i/o pin connections to external circuits. 20.1 features ? continuous transmission/reception since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmi ssion/reception can be performed. ? start and stop conditions generated automatically in master mode ? selection of acknowledge output levels when receiving ? automatic loading of acknowledge bit when transmitting ? bit synchronization/wait function in master mode, the state of scl is monitored per bit, and the timing is synchronized automatically. if transmission/reception is not yet possible, set the scl to low un til preparations are completed. ? six interrupt sources transmit data empty (including slave-address matc h), transmit end, receive data full (including slave-address match), arbitration lost, nack detection, and stop condition detection ? direct bus drive two pins, scl and sda pins, function as nmos open-drain outputs when the bus drive function is selected. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 646 of 1458 rej09b0033-0300 scl iccr1 transfer clock generation circuit address comparator interrupt generator interrupt request bus state decision circuit arbitration decision circuit noise canceller noise canceller output control output control transmission/ reception control circuit iccr2 icmr icsr iceir icdrr icdrs icdrt i 2 c bus control register 1 i 2 c bus control register 2 i 2 c bus mode register i 2 c bus status register i 2 c bus interrupt enable register i 2 c bus transmit data register i 2 c bus receive data register i 2 c bus shift register slave address register [legend ] iccr1: iccr2: icmr: icsr: icier: icdrt: icdrr: icdrs: sar: iccks: i 2 c bus master transfer clock select register sar sda internal data bus iccks figure 20.1 block diagram of i 2 c bus interface section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 647 of 1458 rej09b0033-0300 vcc vcc scl in scl out scl sda in sda out sda scl (master) (slave 1) (slave 2) sda scl in scl out scl sda in sda out sda scl in scl out scl sda in sda out sda figure 20.2 external circu it connections of i/o pins section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 648 of 1458 rej09b0033-0300 20.2 input/output pins table 20.1 summarizes the input/output pins used by the i 2 c bus interface. table 20.1 i 2 c bus interface pins name pin name abbreviation i/o function iic clock iic_scl scl i/o iic serial clock input/output iic data i/o iic_sda sda i/o iic serial data input/output 20.3 register descriptions the i 2 c bus interface has the fo llowing registers: ? i 2 c bus control register 1 (iccr1) ? i 2 c bus control register 2 (iccr2) ? i 2 c bus mode register (icmr) ? i 2 c bus interrupt enable register (icier) ? i 2 c bus status register (icsr) ? slave address register (sar) ? i 2 c bus transmit data register (icdrt) ? i 2 c bus receive data register (icdrr) ? i 2 c bus shift register (icdrs) ? i 2 c bus master transfer cloc k select register (iccks) section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 649 of 1458 rej09b0033-0300 20.3.1 i 2 c bus control register 1 (iccr1) iccr1 enables or disables the i 2 c bus interface, controls transmi ssion or reception, and selects master or slave mode, transmission or reception , and transfer clock frequ ency in master mode. bit bit name initial value r/w description 7 ice 0 r/w i 2 c bus interface enable 0: this module is halted. 1: this bit is enabled for transfer operations. 6 rcvd 0 r/w reception disable this bit enables or disables the next operation when trs is 0 and icdrr is read. 0: enables next reception 1: disables next reception 5 4 mst trs 0 0 r/w r/w master/slave select transmit/receive select in master mode with the i 2 c bus format, when arbitration is lost, mst and trs are both reset by hardware, causing a transition to slave receive mode. modification of the trs bit should be made between transfer frames. after data receive has been started in slave receive mode, when the first seven bits of the receive data agree with the slave address that is set to sar and the eighth bit is 1, trs is automatically set to 1. operating modes are described below according to mst and trs combination. 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 650 of 1458 rej09b0033-0300 20.3.2 i 2 c bus control register 2 (iccr2) iccr1 issues start/stop conditions, manipulates the sda pin, monitors the scl pin, and controls reset in the control part of the i 2 c bus interface. bit bit name initial value r/w description 7 bbsy 0 r/w bus busy this bit enables to confirm whether the i 2 c bus is occupied or released and to issue start/stop conditions in master mode. with the i 2 c bus format, this bit is set to 1 when the sda level changes from high to low under the condition of scl = high, assuming that the start condition has been issued. this bit is cleared to 0 when the sda level changes from low to high under the condition of scl = high, assuming that the st op condition has been issued. write 1 to bbsy and 0 to scp to issue a start condition. follow this procedure when also re-transmitting a start condition. write 0 in bbsy and 0 in scp to issue a stop condition. to issue start/stop conditions, use the mov instruction. 6 scp 1 w start/stop issue condition disable the scp bit controls the iss ue of start/stop conditions in master mode. to issue a start condition, write 1 in bbsy and 0 in scp. a retransmit start condition is issued in the same way. to issue a stop condition, write 0 in bbsy and 0 in scp. this bit is always read as 1. if 1 is written, the data is not stored. 5 sdao 1 r/w sda output value control this bit is used with sdaop when modifying output level of sda. this bit should not be manipulated during transfer. 0: when reading, sda pin outputs low. when writing, sda pin is changed to output low. 1: when reading, sda pin outputs high. when writing, sda pin is changed to output hi-z (outputs high by external pull-up resistance). section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 651 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 sdaop 1 r/w sdao write protect this bit controls change of output level of the sda pin by modifying the sdao bit. to change the output level, clear sdao and sdaop to 0 or set sdao to 1 and clear sdaop to 0 by the mov instruction. this bit is always read as 1. 3 sclo 1 r this bit monitors scl output level. when sclo is 1, scl pin outputs high. when sclo is 0, scl pin outputs low. 2 ? 1 ? reserved this bit is always read as 1. 1 iicrst 0 r/w iic control part reset this bit resets the control part except for i 2 c registers. if this bit is set to 1 when hang-up occurs because of communication failure during i 2 c operation, i 2 c control part can be reset without setting ports and initializing registers. 0 ? 1 ? reserved this bit is always read as 1. 20.3.3 i 2 c bus mode register (icmr) icmr selects whether the msb or lsb is transfer red first, performs master mode wait control, and selects the tran sfer bit count. bit bit name initial value r/w description 7 mls 0 r/w msb-first/lsb-first select 0: msb-first 1: lsb-first set this bit to 0 when the i 2 c bus format is used. 6 ? 0 ? reserved this bit is always read as 0. the write value should always be 0. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 652 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5, 4 ? all 1 ? reserved these bits are always read as 1. 3 bcwp 1 r/w bc write protect this bit controls the bc2 to bc0 modifications. when modifying bc2 to bc0, this bit should be cleared to 0 and use the mov instruction. 0: when writing, values of bc2 to bc0 are set. 1: when reading, 1 is always read. when writing, settings of bc2 to bc0 are invalid. 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter 2 to 0 these bits specify the number of bits to be transferred next. when read, the remaining number of transfer bits is indicated. with the i 2 c bus format, the data is transferred with one addition acknowledge bit. bit bc2 to bc0 settings should be made during an interval between transfer frames. if bits bc2 to bc0 are set to a value other than 000, the setting should be made while the scl pin is low. the value returns to 000 at the end of a data transfer, including the acknowledge bit. i 2 c bus format 000: 9 bits 001: 2 bits 010: 3 bits 011: 4 bits 100: 5 bits 101: 6 bits 110: 7 bits 111: 8 bits section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 653 of 1458 rej09b0033-0300 20.3.4 i 2 c bus interrupt enable register (icier) icier enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and conf irms acknowledge bits to be received. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when the tdre bit in icsr is set to 1, this bit enables or disables the transmit dat a empty interrupt (txi). 0: transmit data empty interru pt request (txi) is disabled. 1: transmit data empty interru pt request (txi) is enabled. 6 teie 0 r/w transmit end interrupt enable this bit enables or disables the transmit end interrupt (tei) at the rising of the nint h clock while the tdre bit in icsr is 1. tei can be canceled by clearing the tend bit or the teie bit to 0. 0: transmit end interrupt request (tei) is disabled. 1: transmit end interrupt request (tei) is enabled. 5 rie 0 r/w receive interrupt enable this bit enables or disables the receive data full interrupt request (rxi) when a receive data is transferred from icdrs to icdrr and the rdrf bit in icsr is set to 1. rxi can be canceled by clearing the rdrf or rie bit to 0. 0: receive data full interrupt request (rxi) is disabled. 1: receive data full interrupt request (rxi) is enabled. 4 nakie 0 r/w nack receive interrupt enable this bit enables or disables the nack receive interrupt request (naki) when the nackf and al bits in icsr are set to 1. naki can be canceled by clearing the nackf, ove, or nakie bit to 0. 0: nack receive interrupt request (naki) is disabled. 1: nack receive interrupt request (naki) is enabled. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 654 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 stie 0 r/w stop condition detection interrupt enable 0: stop condition detection interrupt request (stpi) is disabled. 1: stop condition detection interrupt request (stpi) is enabled. 2 acke 0 r/w acknowledge bit judgement select 0: the value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: if the receive acknowledge bit is 1, continuous transfer is halted. 1 ackbr 0 r receive acknowledge in transmit mode, this bit stores the acknowledge data that are returned by the receive device. this bit cannot be modified. 0: receive acknowledge = 0 1: receive acknowledge = 1 0 ackbt 0 r/w transmit acknowledge in receive mode, this bit specif ies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing. 1: 1 is sent at the acknowledge timing. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 655 of 1458 rej09b0033-0300 20.3.5 i 2 c bus status register (icsr) icsr performs confirmation of interrupt request flags and status. bit bit name initial value r/w description 7 tdre 0 r/w transmit data register empty [setting condition] ? when data is transferred from icdrt to icdrs and icdrt becomes empty ? when trs is set ? when a start condition (including re-transfer) has been issued ? when transmit mode is entered from receive mode in slave mode [clearing conditions] ? when 0 is written in tdre after reading tdre = 1 ? when data is written to icdrt with an instruction 6 tend 0 r/w transmit end [setting conditions] ? when the ninth clock of scl rises with the i 2 c bus format while the tdre flag is 1 [clearing conditions] ? when 0 is written in tend after reading tend = 1 ? when data is written to icdrt with an instruction 5 rdrf 0 r/w receive data register full [setting condition] ? when a receive data is transferred from icdrs to icdrr [clearing conditions] ? when 0 is written in rdrf after reading rdrf = 1 ? when icdrr is read with an instruction section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 656 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 nackf 0 r/w no acknowledge detection flag [setting condition] ? when no acknowledge is detected from the receive device in transmission while the acke bit in icier is 1 [clearing condition] ? when 0 is written in nackf after reading nackf = 1 3 stop 0 r/w stop condition detection flag [setting conditions] ? in master mode: when a stop condition is detected after frame transfer is completed ? in slave mode: when a stop condition is detected after the address set in sar matches the salve address that comes as the first byte after the detection of a start condition [clearing condition] ? when 0 is written in stop after reading stop = 1 2 al/ove 0 r/w arbitration lost flag/overrun error flag this flag indicates that arbitration was lost in master mode with the i 2 c bus format. when two or more master devices attempt to seize the bus at nearly the same time, if the i 2 c bus interface detects data differing from the data it sent, it sets al to 1 to indicate that the bus has been taken by another master. [setting conditions] ? if the internal sda and sda pin disagree at the rise of scl in master transmit mode ? when the sda pin outputs high in master mode while a start condition is detected [clearing condition] ? when 0 is written in al/ove after reading al/ove = 1 section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 657 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 aas 0 r/w slave addr ess recognition flag in slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits sva6 to sva0 in sar. [setting conditions] ? when the slave address is detected in slave receive mode ? when the general call address is detected in slave receive mode. [clearing condition] ? when 0 is written in aas after reading aas = 1 0 adz 0 r/w general call address recognition flag this bit is valid in i 2 c bus format slave receive mode. [setting condition] ? when the general call address is detected in slave receive mode [clearing conditions] ? when 0 is written in adz after reading adz = 1 20.3.6 slave address register (sar) sar selects the communica tion format and sets the slave address. when the chip is in slave mode with the i 2 c bus format, if the upper 7 bits of sar match the upper 7 bits of the first frame received after a start condition, the ch ip operates as the slave device. bit bit name initial value r/w description 7 to 1 sva6 to sva0 all 0 r/w slave address 6 to 0 these bits set a unique address in bits sva6 to sva0, differing form the addresses of other slave devices connected to the i 2 c bus. 0 ? 0 r reserved these bits are always read as 0. the write value should always be 0. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 658 of 1458 rej09b0033-0300 20.3.7 i 2 c bus transmit data register (icdrt) icdrt is an 8-bit readable/writable register that stores the transmit data. when icdrt detects the space in the shift register (icdrs), it transfers th e transmit data which is written in icdrt to icdrs and starts transferring data. if the next transfer data is written to icdrt during transferring data of icdrs, conti nuous transfer is possible. if the mls bit of icmr is set to 1 and when the data is written to icdrt, the msb/ls b inverted data is read. the initial value of icdrt is h'ff. 20.3.8 i 2 c bus receive data register (icdrr) icdrr is an 8-bit register that stores the receiv e data. when data of one byte is received, icdrr transfers the receive data from icdrs to icdrr and the next data can be received. icdrr is a receive-only register, therefore the cpu cannot write to this register . the initial value of icdrr is h'ff. 20.3.9 i 2 c bus shift register (icdrs) icdrs is a register that is used to transfer/receive data. in transm ission, data is transferred from icdrt to icdrs and the data is sent from the sda pin. in reception, data is transferred from icdrs to icdrr after data of one byte is received. this register cannot be read directly from the cpu. 20.3.10 i 2 c bus master transfer cloc k select register (iccks) iccks is enabled in master mode and selects a transfer clock used in master mode. specify iccks according to the requir ed transfer rate. for tran sfer rate, see table 20.2. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 2 1 0 cks4 cks3 cks2 cks1 cks0 0 0 0 0 0 r/w r/w r/w r/w r/w master transfer clock select 4 to 0 specify these bits according to the required transfer rate in master mode. in slave mode, these bits are used to ensure the data setup time in transmit mode. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 659 of 1458 rej09b0033-0300 table 20.2 transfer rate bit 4 bit 3 bit 2 bit 1 bit 0 transfer rate cks4 cks3 cks2 cks1 cks0 peripheral clock p = 10 mhz p = 16 mhz p = 20 mhz p = 25 mhz p = 30 mhz p = 32 mhz 0 0 0 0 0 p /28 357khz ? ? ? ? ? 0 0 0 0 1 p /40 250khz 400khz ? ? ? ? 0 0 0 1 0 p /48 208khz 333khz ? ? ? ? 0 0 0 1 1 p /64 156khz 250khz 313khz 391khz ? ? 0 0 1 0 0 p /80 125khz 200khz 250khz 313khz 375khz 400khz 0 0 1 0 1 p /100 100khz 160khz 200khz 250khz 300khz 320khz 0 0 1 1 0 p /112 89khz 143khz 179khz 223khz 268khz 286khz 0 0 1 1 1 p /128 78khz 125khz 156khz 195khz 234 khz 250khz 0 1 0 0 0 p /56 179khz 286khz 357khz 446khz 536khz 571khz 0 1 0 0 1 p /80 125khz 200khz 250khz 313khz 375khz 400khz 0 1 0 1 0 p /96 104khz 167khz 208khz 260khz 313khz 333khz 0 1 0 1 1 p /128 78khz 125khz 156khz 195khz 234 khz 250khz 0 1 1 0 0 p /160 63khz 100khz 125khz 156khz 188khz 200khz 0 1 1 0 1 p /200 50khz 80khz 100khz 125khz 150khz 160khz 0 1 1 1 0 p /224 45khz 71khz 89khz 112khz 134 khz 143khz 0 1 1 1 1 p /256 39khz 63khz 78khz 98khz 117khz 125khz 1 0 0 0 0 p /112 89khz 143khz 179khz 223khz 268khz 286khz 1 0 0 0 1 p /160 63khz 100khz 125khz 156khz 188khz 200khz 1 0 0 1 0 p /192 52khz 83khz 104 khz 130khz 156khz 167khz 1 0 0 1 1 p /256 39khz 63khz 78khz 98khz 117khz 125khz 1 0 1 0 0 p /320 31khz 50khz 63khz 78khz 94khz 100khz 1 0 1 0 1 p /400 25khz 40khz 50khz 63khz 75khz 80khz 1 0 1 1 0 p /448 22khz 36khz 45khz 56khz 67khz 71khz 1 0 1 1 1 p /512 20khz 31khz 39khz 49khz 59khz 63khz 1 1 0 0 0 p /224 45khz 71khz 89khz 112khz 134khz 143khz 1 1 0 0 1 p /320 31khz 50khz 63khz 78khz 94khz 100khz 1 1 0 1 0 p /384 26khz 42khz 52khz 65khz 78khz 83khz 1 1 0 1 1 p /512 20khz 31khz 39khz 49khz 59khz 63khz 1 1 1 0 0 p /640 16khz 25khz 31khz 39khz 47khz 50khz section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 660 of 1458 rej09b0033-0300 bit 4 bit 3 bit 2 bit 1 bit 0 transfer rate cks4 cks3 cks2 cks1 cks0 peripheral clock p = 10 mhz p = 16 mhz p = 20 mhz p = 25 mhz p = 30 mhz p = 32 mhz 1 1 1 0 1 p /800 13khz 20khz 25khz 31khz 38khz 40khz 1 1 1 1 0 p /896 11khz 18khz 22khz 28khz 33khz 36khz 1 1 1 1 1 p /1024 10khz 16khz 20khz 24khz 29khz 31khz note: in master mode, a transfer rate of 300 khz or lower should be used. in slave mode, a transfer rate of 400 khz or lower should be used. 20.4 operation 20.4.1 i 2 c bus format figure 20.3 shows the i 2 c bus formats. figure 20.4 shows the i 2 c bus timing. the first frame following a start condition always consists of 8 bits. s sla r/ w a data a a/ a p 111 1 n 7 1 m (a) i 2 c bus format (fs = 0) (b) i 2 c bus format (start condition retransmission, fs = 0) n: transfer bit count (n = 1 to 8) m: transfer frame count (m 1) s sla r/ w a data 11 1 n1 7 1 m1 s sla r/ w a data a/ a p 11 1 n2 7 1 m2 1 1 1 a/ a n1 and n2: transfer bit count (n1 and n2 = 1 to 8) m1 and m2: transfer frame count (m1 and m2 1) 11 figure 20.3 i 2 c bus formats section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 661 of 1458 rej09b0033-0300 sda scl s 1-7 sla 8 r/ w 9 a 1-7 data 89 1-7 89 a data p a figure 20.4 i 2 c bus timing [legend] s: start condition. the master device driv es sda from high to low while scl is high. sla: slave address r/ w : indicates the direction of data transfer: fr om the slave device to the master device when r/ w is 1, or from the master device to the slave device when r/ w is 0. a: acknowledge. the receive device drives sda to low. data: transfer data p: stop condition. the master device drives sda from low to high while scl is high. 20.4.2 master transmit operation in master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. for ma ster transmit mode operation timing, refer to figures 20.5 and 20.6. the transmission procedure and operations in master transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls bit in icmr and the cks4 to cks0 bits in iccks to 1. (initial setting) 2. read the bbsy flag in iccr2 to confirm that the bus is free. set the mst and trs bits in iccr1 to select master transmit mode. then , write 1 to bbsy and 0 to scp using mov instruction. (start condition issued) this generates the start condition. 3. after confirming that tdre in icsr has been set, write the transmit data (the first byte data show the slave address and r/ w ) to icdrt. at this time, tdre is automatically cleared to 0, and data is transferred from icdrt to icdrs. tdre is set again. 4. when transmission of one byte data is completed while tdre is 1, tend in icsr is set to 1 at the rise of the 9th transmit clock pulse. read the ackbr bit in icier, and confirm that the slave device has been selected. then, write second byte data to icdrt. when ackbr is 1, the slave device has not been acknowledged, so issue the stop condition. to issue the stop condition, write 0 to bbsy and scp using mov instruction. scl is fixed low until the transmit data is prepared or the stop condition is issued. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 662 of 1458 rej09b0033-0300 5. the transmit data after the second byte is written to icdrt every time tdre is set. 6. write the number of bytes to be transmitted to icdrt. wait until tend is set (the end of last byte data transmission) while tdre is 1, or wait for nack (nackf in icsr = 1) from the receive device while acke in icier is 1. then , issue the stop condition to clear tend or nackf. 7. when the stop bit in icsr is set to 1, the operation returns to the slave receive mode. tdre scl (master output) sda (master output) sda (slave output) tend [5] write data to icdrt (third byte) icdrt icdrs [2] instruction of start condition issuance [3] write data to icdrt (first byte) [4] write data to icdrt (second byte) user processing 1 bit 7 slave address address + r/ w data 1 data 1 data 2 address + r/ w bit 6 bit 7 bit 6 bit 5bit 4bit 3bit 2bit 1bit 0 212 3456789 a r/ w figure 20.5 master transmit mode operation timing (1) section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 663 of 1458 rej09b0033-0300 tdre [6] issue stop condition. clear tend. [7] set slave receive mode tend icdrt icdrs 1 9 23456789 a a/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 data n data n bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [5] write data to icdrt user processing figure 20.6 master transmit mode operation timing (2) 20.4.3 master receive operation in master receive mode, the master device outputs th e receive clock, receives data from the slave device, and returns an acknowledge signal. for master receive mode operation timing, refer to figures 20.7 and 20.8. the reception procedure and operations in master receive mode are shown below. 1. clear the tend bit in icsr to 0, then clear the trs bit in iccr1 to 0 to switch from master transmit mode to master receive mode . then, clear the tdre bit to 0. 2. when icdrr is read (dummy data read), reception is started, and the receive clock is output, and data received, in synchronization with the internal clock. the master device outputs the level specified by ackbt in icier to sda, at the 9th receive clock pulse. 3. after the reception of first frame data is complete d, the rdrf bit in icst is set to 1 at the rise of 9th receive clock pulse. at this time, the r eceive data is read by reading icdrr, and rdrf is cleared to 0. 4. the continuous reception is performed by reading icdrr every time rdrf is set. if 8th receive clock pulse falls after reading icdrr by the other processing while rdrf is 1, scl is fixed low until icdrr is read. 5. if next frame is the last receive data, set th e rcvd bit in iccr1 to 1 before reading icdrr. this enables the issuance of the stop condition after the next reception. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 664 of 1458 rej09b0033-0300 6. when the rdrf bit is set to 1 at rise of th e 9th receive clock pulse, issue the stage condition. 7. when the stop bit in icsr is set to 1, read icdrr. then clear the rcvd bit to 0. 8. the operation returns to the slave receive mode. tdre tend icdrs icdrr [1] clear tdre after clearing tend and trs [2] read icdrr (dummy read) [3] read icdrr 1 a 21 3456789 9 a trs rdrf scl (master output) sda (master output) sda (slave output) bit 7 master transmit mode master receive mode bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing data 1 data 1 figure 20.7 master receive mode operation timing (1) section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 665 of 1458 rej09b0033-0300 rdrf rcvd icdrs icdrr data n-1 data n data n data n-1 [5] read icdrr after setting rcvd [6] issue stop condition [7] read icdrr, and clear rcvd [8] set slave receive mode 1 9 23456789 a a/ a scl (master output) sda (master output) sda (slave output) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user processing figure 20.8 master receive mode operation timing (2) 20.4.4 slave transmit operation in slave transmit mode, the slave device outputs th e transmit data, while the master device outputs the receive clock and returns an acknowledge sign al. for slave transmit mode operation timing, refer to figures 20.9 and 20.10. the transmission procedure and operations in slave transmit mode are described below. 1. set the ice bit in iccr1 to 1. set the mls bit in icmr and the cks4 to cks0 bits in iccks1 to 1. (in itial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the leve l specified by ackbt in icier to sda, at the rise of the 9th clock pulse. at this time, if the 8th bit data (r/ w ) is 1, the trs and icsr bits in iccr1 are set to 1, and the mode changes to slave transmit mode automatically. the continuous transmission is performed by writing transmit data to icdrt every time tdre is set. 3. if tdre is set after writing la st transmit data to icdrt, wait until tend in icsr is set to 1, with tdre = 1. when te nd is set, clear tend. 4. clear trs for the end processing, and read icdrr (dummy read). scl is free. 5. clear tdre. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 666 of 1458 rej09b0033-0300 tdre tend icdrs icdrr 1 a 21 3456789 9 a trs icdrt scl (master output) slave receive mode slave transmit mode sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 data 1 data 1 data 2 data 3 data 2 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [2] write data to icdrt (data 1) [2] write data to icdrt (data 2) [2] write data to icdrt (data 3) user processing figure 20.9 slave transmit mode operation timing (1) section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 667 of 1458 rej09b0033-0300 tdre data n tend icdrs icdrr 1 9 2345678 9 trs icdrt a scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 slave transmit mode slave receive mode bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 a [3] clear tend [5] clear tdre [4] read icdrr (dummy read) after clearing trs user processing figure 20.10 slave transmit mode operation timing (2) 20.4.5 slave receive operation in slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. for slave receive mode operation timing, refer to figures 20.11 and 20.12. the reception procedure and operations in slave receive mode are described below. 1. set the ice bit in iccr1 to 1. set the mls bit in icmr and the cks4 to cks0 bits in iccks1 to 1. (in itial setting) set the mst and trs bits in iccr1 to select slave receive mode, and wait until the slave address matches. 2. when the slave address matches in the first frame following detection of the start condition, the slave device outputs the leve l specified by ackbt in icier to sda, at the rise of the 9th clock pulse. at the same time, rdrf in icsr is set to read icdrr (d ummy read). (since the read data show the slave address and r/ w , it is not used.) section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 668 of 1458 rej09b0033-0300 3. read icdrr every time rdrf is set. if 8th r eceive clock pulse falls while rdrf is 1, scl is fixed low until icdrr is read. the change of the acknowledge before reading icdrr, to be returned to the master device, is reflected to the next transmit frame. 4. the last byte data is read by reading icdrr. icdrs icdrr 12 1 345678 9 9 a a rdrf data 1 data 2 data 1 scl (master output) sda (master output) sda (slave output) scl (slave output) bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [2] read icdrr (dummy read) [2] read icdrr user processing figure 20.11 slave receive mode operation timing (1) section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 669 of 1458 rej09b0033-0300 icdrs icdrr 12345678 9 9 a a rdrf scl (master output) sda (master output) sda (slave output) scl (slave output) user processing bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 data 1 [3] set ackbt [3] read icdrr [4] read icdrr data 2 data 1 figure 20.12 slave receive mode operation timing (2) section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 670 of 1458 rej09b0033-0300 20.4.6 noise canceller the logic levels at the scl and sda pins are routed through noise cancellers before being latched internally. figure 20.16 shows a block diagram of the noise canceller circuit. the noise canceller consists of two cascaded la tches and a match detector. the scl (or sda) input signal is sampled on the peripheral clock, but is not passed forward to the next circuit unless the outputs of both latches agree. if they do not agree, the previous value is held. c q d march detector internal scl or sda signal scl or sda input signal sampling clock sampling clock peripheral clock period latch latch c q d figure 20.13 block diagram of noise conceller 20.4.7 example of use flowcharts in respective modes that use the i 2 c bus interface are shown in figures 20.17 to 20.20. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 671 of 1458 rej09b0033-0300 bbsy=0 ? no tend=1 ? no yes start [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] initialize set mst and trs in iccr1 to 1. write 1 to bbsy and 0 to scp. write transmit data in icdrt write 0 to bbsy and scp set mst and trs to 0 in iccr1 read bbsy in iccr2 read tend in icsr read ackbr in icier mater receive mode yes ackbr=0 ? write transmit data in icdrt read tdre in icsr read tend in icsr clear tend in icsr read stop in icsr clear tdre in icsr end write transmit data in icdrt transmit mode? no yes tdre=1 ? last byte? stop=1 ? no no no no no yes yes tend=1 ? yes yes yes [1] test the status of the scl and sda lines. [2] set master transmit mode. [3] issue the start candition. [4] set the first byte (slave address + r/ w ) of transmit data. [5] wait for 1 byte to be transmitted. [6] test the acknowledge transferred from the specified slave device. [7] set the second and subsequent bytes (except for the final byte) of transmit data. [8] wait for icdrt empty. [9] set the last byte of transmit data. [10] wait for last byte to be transmitted. [11] clear the tend flag. [12] clear the stop flag. [13] issue the stop condition. [14] wait for the creation of stop condition. [15] set slave receive mode. clear tdre. [12] clear stop in icsr figure 20.14 sample flowchar t for master transmit mode section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 672 of 1458 rej09b0033-0300 no yes rdrf=1 ? no yes rdrf=1 ? last receive - 1? mater receive mode clear tend in icsr clear trs in iccr1 to 0 clear tdre in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 set rcvd in iccr1 to 1 read icdrr read rdrf in icsr write 0 to bbsy and scp read stop in icsr read icdrr clear rcvd in iccr1 to 0 clear mst in iccr1 to 0 note: 1. do not activate an interrupt during the execution of steps [1] to [3]. end no yes stop=1 ? no yes [1] clear tend, select master receive mode, and then clear tdre. * 1 * 2 [2] set acknowledge to the transmit device. * 1 [3] dummy-read icddr. * [4] wait for 1 byte to be received [5] check whether it is the (last receive - 1). [6] read the receive data last. [7] set acknowledge of the final byte. disable continuous reception (rcvd = 1). [8] read the (final byte - 1) of receive data. [9] wait for the last byte to be receive. [10] clear the stop flag. [11] issue the stop condition. [12] wait for the creation of stop condition. [13] read the last byte of receive data. [14] clear rcvd. [15] set slave receive mode. [1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [13] clear stop in icsr. [10] [14] [15] 2. when one byte is received, steps [2] to [6] are skipped; step [7] is executed after step [1]. setp [8] is icdrr dummy read. figure 20.15 sample flowch art for master receive mode section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 673 of 1458 rej09b0033-0300 tdre=1 ? yes yes no slave transmit mode clear aas in icsr write transmit data in icdrt read tdre in icsr last byte? write transmit data in icdrt read tend in icsr clear tend in icsr clear trs in iccr1 to 0 dummy read icdrr clear tdre in icsr end [1] clear the aas flag. [2] set transmit data for icdrt (except for the last data). [3] wait for icdrt empty. [4] set the last byte of transmit data. [5] wait for the last byte to be transmitted. [6] clear the tend flag . [7] set slave receive mode. [8] dummy-read icdrr to release the scl line. [9] clear the tdre flag. no no yes tend=1 ? [1] [2] [3] [4] [5] [6] [7] [8] [9] figure 20.16 sample flowch art for slave transmit mode section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 674 of 1458 rej09b0033-0300 no yes rdrf=1 ? no yes rdrf=1 ? last receive - 1? slave receive mode clear aas in icsr clear ackbt in icier to 0 dummy-read icdrr read rdrf in icsr read icdrr set ackbt in icier to 1 read icdrr read rdrf in icsr read icdrr end no yes [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [1] clear the aas flag. * [2] set acknowledge to the transmit device. [3] dummy-read icdrr. [4] wait for 1 byte to be received. [5] check whether it is the (last receive - 1). [6] read the receive data. [7] set acknowledge of the last byte. [8] read the (last byte - 1) of receive data. [9] wait the last byte to be received. [10] read for the last byte of receive data. note: when one byte is received, steps [2] to [6] are skipped; step [7] is executed after step [1]. setp [8] is icdrr dummy read. figure 20.17 sample flowch art for slave receive mode section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 675 of 1458 rej09b0033-0300 20.5 interrupt request there are six interrupt requ ests in this module; transmit data em pty, transmit end, receive data full, nack receive, stop recogn ition, and arbitration lost/overrun error. table 20.3 shows the contents of each interrupt request. table 20.3 interrupt requests interrupt request abbreviat ion interrupt condition transmit data empty txi (tdre=1) ? (tie=1) transmit end tei (tend=1) ? (teie=1) receive data full rxi (rdrf=1) ? (rie=1) stop recognition stpi (stop=1) ? (stie=1) nack receive arbitration lost/overrun error naki {(nackf=1)+(al=1)} ? (nakie=1) when interrupt conditions described in table 20.3 are 1 and the i bit in ccr is 0, the cpu executes an interrupt exception pr ocessing. interrupt sources should be cleared in the exception processing. tdre and tend are automatically cl eared to 0 by writing the transmit data to icdrt. rdrf are automatically cl eared to 0 by readin g icdrr. tdre is set to 1 again at the same time when transmit data is written to icdrt. when tdre is cleared to 0, then an excessive data of one byte may be transmitted. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 676 of 1458 rej09b0033-0300 20.6 bit synchronous circuit in master mode, this module has a possibility that high level period may be short in the two states described below. ? when scl is driven to low by the slave device ? when the rising speed of scl is lowered by the load of the scl line (load capacitance or pull- up resistance) therefore, it monitors scl and communicates by bit with synchronization. figure 20.21 shows the timing of the bit synchronous circuit and table 20.4 shows the time when scl output changes from low to hi-z then scl is monitored. scl vih scl monitor timing reference clock internal scl figure 20.18 the timing of the bit synchronous circuit table 20.4 time for monitoring scl cks3 cks2 time for monitoring scl 0 7.5 tpcyc 0 1 19.5 tpcyc 0 17.5 tpcyc 1 1 41.5 tpcyc section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 677 of 1458 rej09b0033-0300 20.7 usage notes a stop condition or retransmit start condition should be issued after the falling edge of the ninth clock is recognized. the falling edge of the ninth clock is recognized by checking the sclo bit in the i 2 c bus control register 2 (iccr2). a stop condition or retransmit start condition may no t be output normally if issuance of a stop or retransmit start condition is attempted with a certa in timing under either of the following cases. there is no problem in uses under conditions other than the blow. 1. when the rising speed of scl is lowered due to the load of the scl line (load capacitance or pull-up resistance) exceeding the time defined in section 20.6, bit synchronous circuit. 2. when the bit synchronous circuit works because the low-level period between the eighth and ninth clock pulses is extended by the slave device. section 20 i 2 c bus interface (iic) rev. 3.00 jan. 18, 2008 page 678 of 1458 rej09b0033-0300 section 21 serial i/o with fifo (siof) scis3f2c_000020030200 rev. 3.00 jan. 18, 2008 page 679 of 1458 rej09b0033-0300 section 21 serial i/o with fifo (siof) this lsi includes a clock-synchronized serial i/o module with fifo (siof) that comprises two channels. the functions of siof_0 and siof_1 are the same. 21.1 features ? serial transfer ? 16-stage 32-bit fifos (independent transmission and reception) ? supports 8-bit data/16-bit data/16-bit stereo audio input and output ? msb first for data transmission ? supports a maximum of 48-khz sampling rate ? synchronization by either frame synchronization pulse or left/right channel switch ? supports codec control data interface ? connectable to linear, audio, or a-law or -law codec chip ? supports both master and slave modes ? serial clock ? an external pin input or internal clock (p ) can be selected as the clock source. ? interrupts: one type ? dma transfer ? supports dma transmission and reception by a transfer request for transmission and reception section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 680 of 1458 rej09b0033-0300 figure 21.1 shows a block diagram of the siof. p/s s/p p 1/nmclk siofmclk siofsck siofsync sioftxd siofrxd timing control siof interrupt request peripheral bus bus interface control registers transmit fifo (32 bits x16 stages) receive fifo (32 bits x16 stages) transmit control data receive control data baud rate generator figure 21.1 block diagram of siof section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 681 of 1458 rej09b0033-0300 21.2 input/output pins the pin configuration in this module is shown in table 21.1. table 21.1 pin configuration channel pin name abbreviation * i/o function siof0_mclk siofmclk input master clock input siof0_sck siofsck i/o serial clock (common to transmission/reception) siof0_sync siofsync i/o frame synchronous signal (common to transmission/reception) siof0_txd sioftxd output transmit data 0 siof0_rxd siofrxd input receive data siof1_mclk siofmclk input master clock input siof1_sck siofsck i/o serial clock (common to transmission/reception) siof1_sync siofsync i/o frame synchronous signal (common to transmission/reception) siof1_txd sioftxd output transmit data 1 siof1_rxd siofrxd input receive data note: * the pins for channel 0 and channel 1 are collectively called siofmclk, siofsck, siofsync, sioftxd, and siofrxd in the following descriptions. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 682 of 1458 rej09b0033-0300 21.3 register descriptions the siof has the following registers. refer to section 37, list of registers, for more details on the addresses and states of these registers in each operating mode. in the register descriptions following this section, channel numbers are omitted. (1) channel 0 ? mode register_0 (simdr_0) ? control register_0 (sictr_0) ? transmit data register_0 (sitdr_0) ? receive data register_0 (sirdr_0) ? transmit control data register_0 (sitcr_0) ? receive control data register_0 (sircr_0) ? status register_0 (sistr_0) ? interrupt enable register_0 (siier_0) ? fifo control register_0 (sifctr_0) ? clock select register_0 (siscr_0) ? transmit data assign register_0 (sitdar_0) ? receive data assign re gister_0 (sirdar_0) ? control data assign register_0 (sicdar_0) (2) channel 1 ? mode register_1 (simdr_1) ? control register_1 (sictr_1) ? transmit data register_1 (sitdr_1) ? receive data register_1 (sirdr_1) ? transmit control data register_1 (sitcr_1) ? receive control data register_1 (sircr_1) ? status register_1 (sistr_1) ? interrupt enable register_1 (siier_1) ? fifo control register_1 (sifctr_1) ? clock select register_1 (siscr_1) ? transmit data assign register_1 (sitdar_1) ? receive data assign re gister_1 (sirdar_1) ? control data assign register_1 (sicdar_1) section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 683 of 1458 rej09b0033-0300 21.3.1 mode re gister (simdr) simdr is a 16-bit readable/writable register that sets the siof operating mode. bit bit name initial value r/w description 15 14 trmd1 trmd0 1 0 r/w r/w transfer mode 1, 0 select transfer mode. for details, see table 21.2. 00: slave mode 1 01: slave mode 2 10: master mode 1 11: master mode 2 13 syncat 0 r/w siofsync pin valid timing indicates the position of the siofsync signal to be output as a synchronization pulse. 0: at the start-bit data of frame 1: at the last-bit data of slot 12 redg 0 r/w receive data sampling edge 0: the siofrxd signal is sa mpled at the falling edge of siofsck (the sioftxd signal is transmitted at the rising edge of siofsck.) 1: the siofrxd signal is samp led at the rising edge of siofsck (the sioftxd signal is transmitted at the falling edge of siofsck.) note: this bit is valid only in master mode. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 684 of 1458 rej09b0033-0300 bit bit name initial value r/w description 11 10 9 8 fl3 fl2 fl1 fl0 0 0 0 0 r/w r/w r/w r/w frame length 3 to 0 00xx: data length is 8 bits and frame length is 8 bits. 0100: data length is 8 bits and frame length is 16 bits. 0101: data length is 8 bits and frame length is 32 bits. 0110: data length is 8 bits and frame length is 64 bits. 0111: data length is 8 bits and frame length is 128 bits. 10xx: data length is 16 bits and frame length is 16 bits. 1100: data length is 16 bits and frame length is 32 bits. 1101: data length is 16 bits and frame length is 64 bits. 1110: data length is 16 bits and frame length is 128 bits. 1111: data length is 16 bits and frame length is 256 bits. note: when data length is specified as 8 bits, control data cannot be transmitted or received. x: don't care 7 txdiz 0 r/w sioftxd pin output when transmission is invalid * 0: high output (1 output) when invalid 1: high-impedance state when invalid note: invalid means when disabled, and when a slot that is not assigned as transmit data or control data is being transmitted. 6 rcim 0 r/w receive control data interrupt mode 0: sets the rcrdy bit in sistr when the contents of sircr change. 1: sets the rcrdy bit in sistr each time when the sircr receives the control data. 5 syncac 0 r/w siofsync pin polarity valid when the siofsync signal is output as synchronous pulse in master mode. 0: active-high 1: active-low section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 685 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 syncdl 0 r/w data pin bit delay for siofsync pin valid when the siofsync signal is output as synchronous pulse. only one-bit delay is valid for transmission in slave mode. 0: no bit delay 1: 1-bit delay 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. table 21.2 operation in each transfer mode transfer mode master/slave siofsync bit delay control data method * 1 slave mode 1 slave synchronous pulse slot position slave mode 2 slave synchronous pulse secondary fs master mode 1 master synchronous pulse syncdl bit slot position master mode 2 master l/r no * 2 not supported notes: * 1 the control data method is valid only when the fl bit is specified as 1xxx. (x: don't care.) * 2 depending on the timing to start sync signal output in master mode 2, the sync signal of the head frame in the high period can be extended to i bit. for details, see section 21.5, usage notes. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 686 of 1458 rej09b0033-0300 21.3.2 control register (sictr) sictr is a 16-bit readable/writable register that sets the siof operating state. bit bit name initial value r/w description 15 scke 0 r/w serial clock output enable this bit is valid in master mode. 0: disables the siofsck output (outputs 0) 1: enables the siofsck output ? if this bit is set to 1, the siof initializes the baud rate generator and initiate s the operation. at the same time, the siof outputs the clock generated by the baud rate generator to the siofsck pin. this bit is initialized in module stop mode. 14 fse 0 r/w frame synchrono us signal output enable this bit is valid in master mode. 0: disables the siofsync output (outputs 0) 1: enables the siofsync output ? if this bit is set to 1, the siof initializes the frame counter and initiates the operation. this bit is initialized in module stop mode. 13 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 687 of 1458 rej09b0033-0300 bit bit name initial value r/w description 9 txe 0 r/w transmit enable 0: disables data transmission from the sioftxd pin 1: enables data transmission from the sioftxd pin ? this bit setting becomes valid at the start of the next frame (at the rising edge of the siofsync signal). ? when the 1 setting for this bit becomes valid, the siof issues a transmit transfer request according to the setting of the tfwm bit in sifctr. when transmit data is stored in the transmit fifo, transmission of data from the sioftxd pin begins. ? this bit is initialized upon a transmit reset. this bit is initialized in module stop mode. 8 rxe 0 r/w receive enable 0: disables data reception from siofrxd 1: enables data reception from siofrxd ? this bit setting becomes valid at the start of the next frame (at the rising edge of the siofsync signal). ? when the 1 setting for this bit becomes valid, the siof begins the recept ion of data from the siofrxd pin. when receiv e data is stored in the receive fifo, the siof issues a reception transfer request according to the setting of the rfwm bit in sifctr. ? this bit is initialized upon receive reset. this bit is initialized in module stop mode. 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 688 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 txrst 0 r/w transmit reset 0: does not reset transmit operation 1: resets transmit operation ? this bit setting becomes valid immediately. this bit should be cleared to 0 before setting the register to be initialized. ? when the 1 setting for this bit becomes valid, the siof immediately sets transmit data from the sioftxd pin to 1, and initializes the transmit data register and transmit-related status. the following are initialized. ? sitdr ? sitcr ? transmit fifo write pointer and read pointer ? tcrdy, tfemp, and tdreq bits in sistr ? txe bit 0 rxrst 0 r/w receive reset 0: does not reset receive operation 1: resets receive operation ? this bit setting becomes valid immediately. this bit should be cleared to 0 before setting the register to be initialized. ? when the 1 setting for this bit becomes valid, the siof immediately disables reception from the siofrxd pin, and initializes the receive data register and receive-related status. the following are initialized. ? sirdr ? sircr ? receive fifo write pointer and read pointer ? rcrdy, rfful, and rdreq bits in sistr ? rxe bit section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 689 of 1458 rej09b0033-0300 21.3.3 transmit data register (sitdr) sitdr is a 32-bit write-only register th at specifies the siof transmit data. sitdr is initialized by the conditions specified in s ection 37, list of registers, or by a transmit reset caused by the txrst bit in sictr. sitdr is initialized in module stop mode. bit bit name initial value r/w description 31 to 16 sitdl 15 to 0 all 0 w left-channel transmit data specify data to be output from the sioftxd pin as left- channel data. the position of the left-channel data in the transmit frame is specified by the tdla bit in sitdar. ? these bits are valid only when the tdle bit in sitdar is set to 1. 15 to 0 sitdr 15 to 0 all 0 w right-channel transmit data specify data to be output fr om the sioftxd pin as right-channel data. the pos ition of the right-channel data in the transmit frame is specified by the tdra bit in sitdar. ? these bits are valid only when the tdre bit and tlrep bit in sitdar are set to 1 and cleared to 0, respectively. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 690 of 1458 rej09b0033-0300 21.3.4 receive data register (sirdr) sirdr is a 32-bit read-only register that reads recei ve data of the siof. si rdr stores data in the receive fifo and is initialized by the conditions specified in section 37, list of registers, or by a receive reset caused by the rxrst bit in sictr. bit bit name initial value r/w description 31 to 16 sirdl 15 to 0 all 0 r left-channel receive data store data received from the siofrxd pin as left- channel data. the position of the left-channel data in the receive frame is specified by the rdla bit in sirdar. ? these bits are valid only when the rdle bit in sirdar is set to 1. 15 to 0 sirdr 15 to 0 all 0 r right-channel receive data store data received from t he siofrxd pin as right- channel data. the position of the right-channel data in the receive frame is specified by the rdra bit in sirdar. ? these bits are valid only when the rdre bit in sirdar is set to 1. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 691 of 1458 rej09b0033-0300 21.3.5 transmit control data register (sitcr) sitcr is a 32-bit readable/writable register that specifies transmit control data of the siof. sitcr can be specified only when the fl bit in simdr is specified as 1xxx (x: don't care.). sitcr is initialized in module stop mode. bit bit name initial value r/w description 31 to 16 sitc0 15 to 0 all 0 r/w control channel 0 transmit data specify data to be output fr om the sioftxd pin as control channel 0 transmit data. the position of the control channel 0 data in the transmit or receive frame is specified by the cd0a bit in sicdar. ? these bits are valid only when the cd0e bit in sicdar is set to 1. 15 to 0 sitc1 15 to 0 all 0 r/w control channel 1 transmit data specify data to be output fr om the sioftxd pin as control channel 1 transmit data. the position of the control channel 1 data in the transmit or receive frame is specified by the cd1a bit in sicdar. ? these bits are valid only when the cd1e bit in sicdar is set to 1. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 692 of 1458 rej09b0033-0300 21.3.6 receive control data register (sircr) sircr is a 32-bit readable/writable register that stores receive control data of the siof. sircr can be specified only when the fl bit in si mdr is specified as 1xxx (x: don't care.). bit bit name initial value r/w description 31 to 16 sirc0 15 to 0 all 0 r/w control channel 0 receive data store data received from t he siofrxd pin as control channel 0 receive data. t he position of the control channel 0 data in the transmit or receive frame is specified by the cd0a bit in sicdar. ? these bits are valid only when the cd0e bit in sicdar is set to 1. 15 to 0 sirc1 15 to 0 all 0 r/w control channel 1 receive data store data received from t he siofrxd pin as control channel 1 receive data. t he position of the control channel 1 data in the transmit or receive frame is specified by the cd1a bit in sicdar. ? these bits are valid only when the cd1e bit in sicdar is set to 1. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 693 of 1458 rej09b0033-0300 21.3.7 status register (sistr) sistr is a 16-bit read-only register that shows the si of state. each bit in this register becomes an siof interrupt source when the corresponding bit in siier is set to 1. sistr is initialized in module stop mode. bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 tcrdy 0 r transmit control data ready 0: indicates that a write to sitcr is disabled 1: indicates that a write to sitcr is enabled ? if sitcr is written when this bit is cleared to 0, sitcr is over-written and the prev ious contents of sitcr are not output from the sioftxd pin. ? this bit is valid when the txe bit in sitcr is set to 1. ? this bit indicates a state of the siof. if sitcr is written, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 13 tfemp 0 r transmit fifo empty 0: indicates that transmit fifo is not empty 1: indicates that transmit fifo is empty ? this bit is valid when the txe bit in sictr is 1. ? this bit indicates a state; if sitdr is written, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 694 of 1458 rej09b0033-0300 bit bit name initial value r/w description 12 tdreq 0 r transmit data transfer request 0: indicates that the size of empty space in the transmit fifo does not exceed the size specified by the tfwm bit in sifctr. 1: indicates that the size of empty space in the transmit fifo exceeds the size specified by the tfwm bit in sifctr. a transmit data transfer request is issued when the empty space in the transmit fifo e xceeds the size specified by the tfwm bit in sifctr. when using transmit data transfer through the dmac, this bit is always cleared by one dmac access. after dmac access, when conditions for setting this bit are satisfied, the siof again indicates 1 for this bit. ? this bit is valid when the txe bit in sictr is 1. ? this bit indicates a state; if the size of empty space in the transmit fifo is less than the size specified by the tfwm bit in sifctr, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 rcrdy 0 r receive control data ready 0: indicates that the sircr stores no valid data. 1: indicates that the sircr stores valid data. ? if sircr is written when this bit is set to 1, sircr is modified by the latest data. ? this bit is valid when the rxe bit in sictr is set to 1. ? this bit indicates a state of the siof. if sircr is read, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 695 of 1458 rej09b0033-0300 bit bit name initial value r/w description 9 rfful 0 r receive fifo full 0: receive fifo not full 1: receive fifo full ? this bit is valid when the rxe bit in sictr is 1. ? this bit indicates a state; if sirdr is read, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 8 rdreq 0 r receive data transfer request 0: indicates that the size of valid space in the receive fifo does not exceed the si ze specified by the rfwm bit in sifctr. 1: indicates that the size of valid space in the receive fifo exceeds the size specified by the rfwm bit in sifctr. a receive data transfer request is issued when the valid space in the receive fifo e xceeds the size specified by the rfwm bit in sifctr. when using receive data transfer through the dmac, this bit is always cleared by one dmac access. after dmac access, when conditions for setting this bit are satisfied, the siof again indicates 1 for this bit. ? this bit is valid when the rxe bit in sictr is 1. ? this bit indicates a state; if the size of valid space in the receive fifo is less than the size specified by the rfwm bit in sifctr, the siof clears this bit. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 696 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 saerr 0 r/w slot assign error 0: indicates that no slot assign error occurs 1: indicates that a slot assign error occurs a slot assign error occurs when the specifications in sitdar, sirdar, and sicdar overlap. if a slot assign error occurs, the siof does not transmit data to the sioftxd pin and does not receive data from the siofrxd pin. note that the siof does not clear the txe bit or rxe bit in sictr at a slot assign error. ? this bit is valid when the txe bit or rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 4 fserr 0 r/w frame synchronization error 0: indicates that no frame synchronization error occurs 1: indicates that a frame synchronization error occurs a frame synchronization error occurs when the next frame synchronization timing appears before the previous data or control data transfers have been completed. if a frame synchronization error occurs, the siof performs transmission or reception for slots that can be transferred. ? this bit is valid when the txe or rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 697 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 tfovf 0 r/w transmit fifo overflow 0: no transmit fifo overflow 1: transmit fifo overflow a transmit fifo overflow means that there has been an attempt to write to sitdr w hen the transmit fifo is full. when a transmit fifo overflow occurs, the siof indicates overflow, and writing is invalid. ? this bit is valid when the txe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 2 tfudf 0 r/w transmit fifo underflow 0: no transmit fifo underflow 1: transmit fifo underflow a transmit fifo underflow means that loading for transmission has occurred when the transmit fifo is empty. when a transmit fifo underflow occurs, the siof repeatedly sends the previous transmit data. ? this bit is valid when the txe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 698 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 rfudf 0 r/w receive fifo underflow 0: no receive fifo underflow 1: receive fifo underflow a receive fifo underflow means that reading of sirdr has occurred when the receive fifo is empty. when a receive fifo underflow occurs, the value of data read from sirdr is not guaranteed. ? this bit is valid when the rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. 0 rfovf 0 r/w receive fifo overflow 0: no receive fifo overflow 1: receive fifo overflow a receive fifo overflow means that writing has occurred when the receive fifo is full. when a receive fifo overflow occurs, the siof indicates overflow, and receive data is lost. ? this bit is valid when the rxe bit in sictr is 1. ? when 1 is written to this bit, the contents are cleared. writing 0 to this bit is invalid. ? if the issue of interrupts by this bit is enabled, an siof interrupt is issued. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 699 of 1458 rej09b0033-0300 21.3.8 interrupt enab le register (siier) siier is a 16-bit readable/writable register that enables the issue of siof interrupts. when each bit in this register is set to 1 and the correspondi ng bit in sistr is set to 1, the siof issues an interrupt. bit bit name initial value r/w description 15 tdmae 0 r/w transmit data dma transfer request enable transmits an interrupt as an interrupt to the cpu/dma transfer request. the tdreqe bit can be set as transmit interrupts. 0: used as a cpu interrupt 1: used as a dma transfer request to the dmac 14 tcrdye 0 r/w transmit control data ready enable 0: disables interrupts due to transmit control data ready 1: enables interrupts due to transmit control data ready 13 tfempe 0 r/w transmit fifo empty enable 0: disables interrupts due to transmit fifo empty 1: enables interrupts due to transmit fifo empty 12 tdreqe 0 r/w transmit data transfer request enable 0: disables interrupts due to transmit data transfer requests 1: enables interrupts due to transmit data transfer requests 11 rdmae 0 r/w receive data dma transfer request enable transmits an interrupt as an interrupt to the cpu/dma transfer request. the rdreqe bit can be set as receive interrupts. 0: used as a cpu interrupt 1: used as a dma transfer request to the dmac 10 rcrdye 0 r/w receive control data ready enable 0: disables interrupts due to receive control data ready 1: enables interrupts due to receive control data ready section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 700 of 1458 rej09b0033-0300 bit bit name initial value r/w description 9 rffule 0 r/w receive fifo full enable 0: disables interrupts due to receive fifo full 1: enables interrupts due to receive fifo full 8 rdreqe 0 r/w receive data transfer request enable 0: disables interrupts due to receive data transfer requests 1: enables interrupts due to receive data transfer requests 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 saerre 0 r/w slot assign error enable 0: disables interrupts due to slot assign error 1: enables interrupts due to slot assign error 4 fserre 0 r/w frame synchronization error enable 0: disables interrupts due to frame synchronization error 1: enables interrupts due to frame synchronization error 3 tfovfe 0 r/w transmit fifo overflow enable 0: disables interrupts due to transmit fifo overflow 1: enables interrupts due to transmit fifo overflow 2 tfudfe 0 r/w transmit fifo underflow enable 0: disables interrupts due to transmit fifo underflow 1: enables interrupts due to transmit fifo underflow 1 rfudfe 0 r/w receive fifo underflow enable 0: disables interrupts due to receive fifo underflow 1: enables interrupts due to receive fifo underflow 0 rfovfe 0 r/w receive fifo overflow enable 0: disables interrupts due to receive fifo overflow 1: enables interrupts due to receive fifo overflow section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 701 of 1458 rej09b0033-0300 21.3.9 fifo control register (sifctr) sifctr is a 16-bit readable/writable register that indicates the area available for the transmit/receive fifo transfer. bit bit name initial value r/w description 15 14 13 tfwm2 tfwm1 tfwm0 0 0 0 r/w r/w r/w transmit fifo watermark 000: issue a transfer request when 16 stages of the transmit fifo are empty. 001: setting prohibited 010: setting prohibited 011: setting prohibited 100: issue a transfer request when 12 or more stages of the transmit fifo are empty. 101: issue a transfer request when 8 or more stages of the transmit fifo are empty. 110: issue a transfer request when 4 or more stages of the transmit fifo are empty. 111: issue a transfer request when 1 or more stages of transmit fifo are empty. ? a transfer request to the transmit fifo is issued by the tdreq bit in sistr. ? the transmit fifo is always used as 16 stages of the fifo regardless of these bit settings. 12 11 10 9 8 tfua4 tfua3 tfua2 tfua1 tfua0 1 0 0 0 0 r r r r r transmit fifo usable area indicate the number of word s that can be transferred by the cpu or dmac as b'00000 (full) to b'10000 (empty). section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 702 of 1458 rej09b0033-0300 bit bit name initial value r/w description 7 6 5 rfwm2 rfwm1 rfwm0 0 0 0 r/w r/w r/w receive fifo watermark 000: issue a transfer request when 1 stage or more of the receive fifo are valid. 001: setting prohibited 010: setting prohibited 011: setting prohibited 100: issue a transfer request when 4 or more stages of the receive fifo are valid. 101: issue a transfer request when 8 or more stages of the receive fifo are valid. 110: issue a transfer request when 12 or more stages of the receive fifo are valid. 111: issue a transfer request when 16 stages of the receive fifo are valid. ? a transfer request to the receive fifo is issued by the rdreq bit in sistr. ? the receive fifo is always used as 16 stages of the fifo regardless of these bit settings. 4 3 2 1 0 rfua4 rfua3 rfua2 rfua1 rfua0 0 0 0 0 0 r r r r r receive fifo usable area indicate the number of word s that can be transferred by the cpu or dmac as b'00000 (empty) to b'10000 (full). section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 703 of 1458 rej09b0033-0300 21.3.10 clock select register (siscr) siscr is a 16-bit readable/writable register that se ts the serial clock generation conditions for the master clock. siscr can be specified when th e trmd1 and trmd0 bits in simdr are specified as b'10 or b'11. bit bit name initial value r/w description 15 mssel 1 r/w master clock source selection 0: uses the input signal of the siofmclk pin as the master clock 1: uses p as the master clock the master clock is the clock input to the baud rate generator. 14 msimm 1 r/w master clock direct selection 0: uses the output clock of the baud rate generator as the serial clock 1: uses the master clock itself as the serial clock 13 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 12 11 10 9 8 brps4 brps3 brps2 brps1 brps0 0 0 0 0 0 r/w r/w r/w r/w r/w prescalar setting set the master clock division ratio according to the count value of the prescalar of the baud rate generator. the range of settings is from b'00000 ( 1/1) to b'11111 ( 1/32). 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 704 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 1 0 brdv2 brdv1 brdv0 0 0 0 r/w r/w r/w baud rate generator's division ratio setting set the frequency division ratio for the output stage of the baud rate generator. 000: prescalar output 1/2 001: prescalar output 1/4 010: prescalar output 1/8 011: prescalar output 1/16 100: prescalar output 1/32 101: setting prohibited 110: setting prohibited 111: prescalar output 1/1 * the final frequency division ratio of the baud rate generator is determined by brps brdv (maximum 1/1024). note: * this setting is valid on ly when the brps4 to brps0 bits are set to b'00000. 21.3.11 transmit data a ssign register (sitdar) sitdar is a 16-bit readable/writable register that specifies the position of the transmit data in a frame (slot number). bit bit name initial value r/w description 15 tdle 0 r/w transmit left-channel data enable 0: disables left-channel data transmission 1: enables left-channel data transmission 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 705 of 1458 rej09b0033-0300 bit bit name initial value r/w description 11 10 9 8 tdla3 tdla2 tdla1 tdla0 0 0 0 0 r/w r/w r/w r/w transmit left-channel data assigns 3 to 0 specify the position of left-channel data in a transmit frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? transmit data for the left channel is specified in the sitdl bit in sitdr. 7 tdre 0 r/w transmit right-channel data enable 0: disables right-channel data transmission 1: enables right-channel data transmission 6 tlrep 0 r/w transmit left-channel repeat 0: transmits data specified in the sitdr bit in sitdr as right-channel data 1: repeatedly transmits data specified in the sitdl bit in sitdr as right-channel data ? this bit setting is valid when the tdre bit is set to 1. ? when this bit is set to 1, the sitdr settings are ignored. 5, 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 tdra3 tdra2 tdra1 tdra0 0 0 0 0 r/w r/w r/w r/w transmit right-channel data assigns 3 to 0 specify the position of right-channel data in a transmit frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? transmit data for the right channel is specified in the sitdr bit in sitdr. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 706 of 1458 rej09b0033-0300 21.3.12 receive data a ssign register (sirdar) sirdar is a 16-bit readable/writable register that specifies the position of the receive data in a frame (slot number). bit bit name initial value r/w description 15 rdle 0 r/w receive left-channel data enable 0: disables left-channel data reception 1: enables left-channel data reception 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 10 9 8 rdla3 rdla2 rdla1 rdla0 0 0 0 0 r/w r/w r/w r/w receive left-channel data assigns 3 to 0 specify the position of left-channel data in a receive frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? receive data for the left channel is stored in the sirdl bit in sirdr. 7 rdre 0 r/w receive right-channel data enable 0: disables right-channel data reception 1: enables right-channel data reception 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 rdra3 rdra2 rdra1 rdra0 0 0 0 0 r/w r/w r/w r/w receive right-channel data assigns 3 to 0 specify the position of right-channel data in a receive frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? receive data for the right channel is stored in the sirdr bit in sirdr. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 707 of 1458 rej09b0033-0300 21.3.13 control data assign register (sicdar) sicdar is a 16-bit readable/writable register that specifies the position of the control data in a frame (slot number). sicdar can be specified only when the fl bit in simdr is specified as 1xxx (x: don't care.). bit bit name initial value r/w description 15 cd0e 0 r/w control channel 0 data enable 0: disables transmission and reception of control channel 0 data 1: enables transmission and reception of control channel 0 data 14 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 10 9 8 cd0a3 cd0a2 cd0a1 cd0a0 0 0 0 0 r/w r/w r/w r/w control channel 0 data assigns 3 to 0 specify the position of control channel 0 data in a receive or transmit frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? transmit data for the control channel 0 data is specified in the sitd0 bit in sitcr. ? receive data for the control channel 0 data is stored in the sird0 bit in sircr. 7 cd1e 0 r/w control channel 1 data enable 0: disables transmission and reception of control channel 1 data 1: enables transmission and reception of control channel 1 data 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 708 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 2 1 0 cd1a3 cd1a2 cd1a1 cd1a0 0 0 0 0 r/w r/w r/w r/w control channel 1 data assigns 3 to 0 specify the position of control channel 1 data in a receive or transmit frame as b'0000 (0) to b'1110 (14). 1111: setting prohibited ? transmit data for the control channel 1 data is specified in the sitd1 bit in sitcr. ? receive data for the control channel 1 data is stored in the sird1 bit in sircr. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 709 of 1458 rej09b0033-0300 21.4 operation 21.4.1 serial clocks (1) master/slave modes the following two modes are ava ilable as the siof clock mode. ? slave mode: siofsck, siofsync input ? master mode: siofsck, siofsync output (2) baud rate generator in siof master mode, the baud rate generator (brg) is used to generate the serial clock. the division ratio is from 1/1 to 1/1024. figure 21.2 shows connections for supply of the serial clock. brg mclk 1/1 to 1/1024 mclk scke siofsck siofmclk p timing control master figure 21.2 serial clock supply section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 710 of 1458 rej09b0033-0300 table 21.3 shows an example of serial clock frequency. table 21.3 siof serial clock frequency sampling rate frame length 8 khz 44.1 khz 48 khz 32 bits 256 khz 1.4112 mhz 1.536 mhz 64 bits 512 khz 2.8224 mhz 3.072 mhz 128 bits 1.024 mhz 5.6448 mhz 6.144 mhz 256 bits 2.048 mhz 11.289 mhz 12.289 mhz section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 711 of 1458 rej09b0033-0300 21.4.2 serial timing (1) siofsync the siofsync is a frame synchronous signal. depending on the transfer mode, it has the following two functions. ? synchronous pulse: 1-bit-width pulse indicating the start of the frame ? l/r: 1/2-frame-width pulse indicating the left-channel stereo data (l) in high level and the right-channel stereo data (r) in low level figure 21.3 shows the siofsync synchronization timing. siofsck siofrxd sioftxd siofsync siofsck siofrxd sioftxd siofsync (a) synchronous pulse (b) l/r 1 frame 1 frame start bit data 1-bit delay start bit of left channel data (1/2 frame length) start bit of right channel data (1/2 frame length) no delay figure 21.3 serial data synchronization timing section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 712 of 1458 rej09b0033-0300 (2) transmit/receive timing the sioftxd transmit timing and siofrxd receive ti ming relative to the siofsck can be set as the sampling timing in the following two ways. the transmit/receive timing is set using the redg bit in simdr. ? falling-edge sampling ? rising-edge sampling figure 21.4 shows the transmit/receive timing. siofsck siofsync sioftxd siofrxd siofsck siofsync sioftxd siofrxd (a) falling-edge sampling (a) rising-edge sampling receive timing transmit timing receive timing transmit timing figure 21.4 siof tr ansmit/receive timing section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 713 of 1458 rej09b0033-0300 21.4.3 transfer data format the siof performs the following transfer. ? transmit/receive data: transfer of 8-b it data/16-bit data/1 6-bit stereo data ? control data: transfer of 16-bit data (u ses the specific register as interface) (1) transfer mode the siof supports the following four transfer modes as listed in table 21.4. the transfer mode can be specified by the trmd1 an d trmd0 bits in simdr. table 21.4 serial transfer modes transfer mode siofsync bit delay control data slave mode 1 synchronous pulse slot position slave mode 2 synchronous pulse secondary fs master mode 1 synchronous pulse syncdl bit slot position master mode 2 l/r no * not supported note: * depending on the timing of sync signal output, bit delay may be generated in head frame. for details, see se ction 21.5, usage notes. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 714 of 1458 rej09b0033-0300 (2) frame length the length of the frame to be transferred by the siof is specified by the fl3 to fl0 bits in simdr. table 21.5 shows the relationship between the fl3 to fl0 bit settings and frame length. table 21.5 frame length fl3 to fl0 slot length number of bits in a frame transfer data 00xx 8 8 8-bit monaural data 0100 8 16 8-bit monaural data 0101 8 32 8-bit monaural data 0110 8 64 8-bit monaural data 0111 8 128 8-bit monaural data 10xx 16 16 16-bit monaural data 1100 16 32 16-bit monaural/stereo data 1101 16 64 16-bit monaural/stereo data 1110 16 128 16-bit monaural/stereo data 1111 16 256 16-bit monaural/stereo data note: x: don't care. (3) slot position the siof can specify the positi on of transmit data, receive data, and control data in a frame (common to transmission and reception) by slot numbers. the slot nu mber of each data is specified by the following registers. ? transmit data: sitdar ? receive data: sirdar ? control data: sicdar only 16-bit data is valid for control data. in additio n, control data is always assigned to the same slot number both in tran smission and reception. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 715 of 1458 rej09b0033-0300 21.4.4 register allocation of transfer data (1) transmit/receive data writing and reading of transmit/receive data ar e performed for the following registers. ? transmit data writing : sitdr (32-bit access) ? receive data reading: sirdr (32-bit access) figure 21.5 shows the transmit/receive data and the sitdr and si rdr bit alignment. 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 l-channel data r-channel data (a) 16-bit stereo data data data data (b) 16-bit monaural data (c) 8-bit monaural data (d) 16-bit stereo data (left and right same audio output) data figure 21.5 transmit/receive data bit alignment note: in the figure, only the sh aded areas are transmitted or received as valid data. data in unshaded areas is not tr ansmitted or received. monaural or stereo can be specified for transmit data by the tdle bit and tdre bit in sitdar. monaural or stereo can be specified for receive data by the rdle bit and rdre bit in sirdar. to achieve left and right same audio output while stereo is specified for tr ansmit data, specify the tlrep bit in sitdar. tables 21.6 and 21.7 show the audio mode specification for transmit data and that for receive data, respectively. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 716 of 1458 rej09b0033-0300 table 21.6 audio mode specifi cation for transmit data bit mode tdle tdre tlrep monaural 1 0 x stereo 1 1 0 left and right same audio output 1 1 1 note: x: don't care table 21.7 audio mode speci fication for receive data bit mode rdle rdre monaural 1 0 stereo 1 1 note: left and right same audio mode is not supported in receive data. to execute 8-bit monaural transmission or reception, use the left channel. (2) control data control data is written to or read from by the following registers. ? transmit control data wr ite: sitcr (32-bit access) ? receive control data read: sircr (32-bit access) figure 21.6 shows the control data and bit alignment in sitcr and sircr. 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 (a) control data: one channel (b) control data: two channels control data (channel 0) control data (channel 0) control data (channel 1) figure 21.6 control data bit alignment section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 717 of 1458 rej09b0033-0300 the number of channels in control data is specified by the cd0e and cd1e bits in sicdar. table 21.8 shows the relationship between the number of channels in control data and bit settings. table 21.8 setting number of channels in control data bit number of channels cd0e cd1e 1 1 0 2 1 1 note: to use only one channel in control data, use channel 0. 21.4.5 control data interface control data performs control command output to the codec and status input from the codec. the siof supports the following tw o control data interface methods. ? control by slot position ? control by secondary fs control data is valid only when data length is specified as 16 bits. (1) control by slot position (m aster mode 1, slave mode 1) control data is transferred for a ll frames transmitted or received by the siof by specifying the slot position of control data. this method can be used in both siof master and slave modes. figure 21.7 shows an example of the control data interface timing by slot position control. siofsck siofrxd sioftxd siofsync l-channel data r-channel data specifications: trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=1, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0001, fl[3:0]=1110 (frame length: 128 bits), tdre=1, rdre=1, cd1e=1, tdra[3:0]=0010, rdra[3:0]=0010, cd1a[3:0]=0011 control channel 0 control channel 1 1 frame slot no.0 slot no.1 slot no.2 slot no.3 figure 21.7 control data interface (slot position) section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 718 of 1458 rej09b0033-0300 (2) control by secondary fs (slave mode 2) the codec normally outputs the siofsync signal as synchronization pulse (fs). in this method, the codec outputs the seco ndary fs specific to the control data transfer after 1/2 frame time has been passed (not the normal fs output tim ing) to transmit or rece ive control data. this method is valid for siof slave mode. the fo llowing summarizes the control data interface procedure by the secondary fs. ? transmit normal transmit data of lsb = 0 (the siof forcibly clears 0). ? to execute control data transmission, send transmit data of lsb = 1 (the siof forcibly set to 1 by writing sitcdr). ? the codec outputs the secondary fs. ? the siof transmits or receives (stores in sircd r) control data (data specified by sitcdr) synchronously with the secondary fs. figure 21.8 shows an example of the contro l data interface timing by the secondary fs. siofsck siofrxd sioftxd siofsync l-channel data specifications: trmd[1:0]=01, tdle=1, rdle=1, cd0e=1, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0000, fl[3:0]=1110 (frame length: 128 bits), tdre=0, rdre=0, cd1e=0, tdra[3:0]=0000, rdra[3:0]=0000, cd1a[3:0]=0000 lsb=1 (secondary fs request) 1 frame 1/2 frame 1/2 frame normal fs normal fs secondary fs control channel 0 slot no.0 slot no.0 figure 21.8 control data interface (secondary fs) section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 719 of 1458 rej09b0033-0300 21.4.6 fifo (1) overview the transmit and receive fifos of the siof have the following features. ? 16-stage 32-bit fifos for transmission and reception ? the fifo pointer can be updated in one read or write cycle re gardless of access size of the cpu and dmac. (one-stage 32-bit fifo access cannot be divided into multiple accesses.) (2) transfer request the transfer request of the fifo can be issued to the cpu or dmac as the following interrupt sources. ? fifo transmit request: tdreq (transmit interrupt source) ? fifo receive request: rdreq (receive interrupt source) the request conditions for fifo transmit or receive can be speci fied individuall y. the request conditions for the fifo transmit and receive are specified by the tfwm 2 to tfwm0 bits and rfwm2 to rfwm0 bits in sifctr, respecti vely. tables 21.9 and 21.10 summarize the conditions specified by sifctr. table 21.9 conditions to issue transmit request tfwm2 to tfwm0 number of requested stages transmit request used areas 000 1 empty area is 16 stages 100 4 empty area is 12 stages or more 101 8 empty area is 8 stages or more 110 12 empty area is 4 stages or more smallest 111 16 empty area is 1 stage or more largest section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 720 of 1458 rej09b0033-0300 table 21.10 conditions to issue receive request rfwm2 to rfwm0 number of requested stages receive request used areas 000 1 valid data is 1 stage or more 100 4 valid data is 4 stages or more 101 8 valid data is 8 stages or more 110 12 valid data is 12 stages or more smallest 111 16 valid data is 16 stages largest the number of stages of the fifo is always sixteen even if the data area or empty area exceeds the fifo size (the number of fifos). accordingly, an overflow error or underflow error occurs if data area or empty area exceeds sixteen fi fo stages. the fifo transmit or receive request is canceled when the above condition is not satisfied even if the fifo is not empty or full. (3) number of fifos the number of fifo stages used in transmission and reception is indicated by the following register. ? transmit fifo: the number of empty fifo stages is indicat ed by the tfua4 to tfua0 bits in sifctr. ? receive fifo: the number of valid data stages is indicated by the rfua4 to rfua0 bits in sifctr. the above indicate possible data numbers that can be transferred by the cpu or dmac. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 721 of 1458 rej09b0033-0300 21.4.7 transmit and receive procedures (1) transmission in master mode figure 21.9 shows an example of settings and operation for master mode transmission. flow chart siof settings siof operation start set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and fifo request threshold value set the scke bit in sictr to 1 start siofsck output set the fse and txe bits in sictr to 1 clear the txe bit in sictr to 0 tdreq = 1? no ye s no ye s set sitdr transmit sitdr from sioftxd synchronously with siofsync transfer ended? end set operation start for baud rate generator set the start for frame synchronous signal output and enable transmission set transmit data set to disable transmission output serial clock output frame synchronous signal and issue transmit transfer request * transmit end transmission no. 1 2 3 4 5 6 7 8 set the fse bit in sictr to 0 set the mssel bit in siscr to 1 set brdv=111 and bprs=00000 in siscr start the setting fse=0, txe=0 and other bit. add pulse (0 1 0) to the txrst in siscr reset the master clock source and baud rate in siscr synchronize this lsi internal frame with fse=0 if restarting transmit later. execute internal initialization of the bit rate generator if restarting transmit later. 'no' requires further setting if transmission is not restarted (no). when returning to the same transmit mode from here, go back to no.4, fse setting, on this flowchart. go to "start" on each flowchart. 9 10 11 12 no ye s change other transmit mode? note: * when interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the txe bit should be set to 1. figure 21.9 example of transmit operation in master mode section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 722 of 1458 rej09b0033-0300 (2) reception in master mode figure 21.10 shows an example of settings and operation for master mode reception. flow chart siof settings siof operation start set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and fifo request threshold value set the scke bit in sictr to 1 start siofsck output set the fse and rxe bits in sictr to 1 clear the rxe bit in sictr to 0 rdreq = 1? no ye s no ye s read sirdr store siofrxd receive data in sirdr synchronously with siofsync transfer ended? set operation start for baud rate generator set the start for frame synchronous signal output and enable reception read receive data set to disable reception output serial clock output frame synchronous signal reception end reception no. 1 2 3 4 5 6 7 8 9 10 11 12 issue receive transfer request according to the receive fifo threshold value end set the fse bit in sictr to 0 set the mssel bit in siscr to 1 set brdv=111 and bprs=00000 in siscr start the setting fse=0, txe=0 and other bit. add pulse (0 1 0) to the rxrst in siscr reset the master clock source and baud rate in siscr synchronize this lsi internal frame with fse=0 if restarting recept later. execute internal initialization of the bit rate generator if restarting recept later. 'no' requires further setting if transmission is not restarted (no). when returning to the same recept mode from here, go back to no.4, fse setting, on this flowchart. go to "start" on each flowchart. no ye s change other transmit mode? figure 21.10 example of recei ve operation in master mode section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 723 of 1458 rej09b0033-0300 (3) transmission in slave mode figure 21.11 shows an example of settings and operation for slave mode transmission. start no ye s no ye s end no. 1 2 3 4 5 6 set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set the txe bit in sictr to 1 tdreq = 1? set sitdr transmit sitdr from sioftxd synchronously with siofsync transfer ended? clear the txe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and fifo request threshold value set transmit data set to disable transmission issue transmit transfer request to enable transmission when frame synchronous signal is input transmit end transmission flow chart siof settings siof operation set to enable transmission figure 21.11 example of transmit operation in slave mode section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 724 of 1458 rej09b0033-0300 (4) reception in slave mode figure 21.12 shows an example of settings and oper ation for slave mode reception. start no ye s no ye s end no. 1 2 3 4 5 6 set simdr, siscr, sitdar, sirdar, sicdar, and sifctr set the rxe bit in sictr to 1 rdreq = 1? transfer ended? clear the rxe bit in sictr to 0 set operating mode, serial clock, slot positions for transmit/receive data, slot position for control data, and fifo request threshold value flow chart siof settings siof operation issue receive transfer request according to the receive fifo threshold value reception end reception read receive data set to disable reception read sirdr store siofrxd receive data in sirdr synchronously with siofsync set to enable reception enable reception when the frame synchronous signal is input figure 21.12 example of recei ve operation in slave mode section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 725 of 1458 rej09b0033-0300 (5) transmit/receive reset the siof can separately reset the transmit and r eceive units by setting the following bits to 1. ? transmit reset: txrst bit in sictr ? receive reset: rxrst bit in sictr table 21.11 shows the details of initializat ion upon transmit or receive reset. table 21.11 transmit and receive reset type objects initialized transmit reset sitdr transmit fifo write pointer and read pointer tcrdy, tfemp, and tdreq bits in sistr txe bit in sictr receive reset sirdr receive fifo write pointer and read pointer rcrdy, rfful, and rdreq bits in sistr rxe bit in sictr notes: refer to the following procedure to operate the transmit reset/receive reset. 1 set the master clock source in the peripheral clock. (write 1 (master clock = p (peripheral clock)) to the mssel bit in the siscr register). 2 set the prescaler count value of the baud ra te generator to 1/1. (write "00000" (division ratio = 1/1) to brps bits 4 to 0 in the siscr register). 3 set the division ratio in the bit rate generat or's output level to 1/1. (write "111" (division ratio =1/1) to brdv bits 2 to 0 in the siscr register). 4 reset transmit/receive operation. (to reset, write "1" to the txrst or rxrst bit in the sictr register). section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 726 of 1458 rej09b0033-0300 (6) module stop mode the siof stops the transmit/receive operation in module stop mode . then the following contents are initialized. ? sitdr ? sitcr ? read pointer of transmit/receive fifo ? write pointer of transmit/receive fifo ? sistr ? sictr section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 727 of 1458 rej09b0033-0300 21.4.8 interrupts the siof has one type of interrupt. (1) interrupt sources interrupts can be issued by several sources. each source is shown as an siof status in sistr. table 21.12 lists the siof interrupt sources. table 21.12 siof interrupt sources no. classification bit name function name description 1 tdreq transmit fifo transfer request the transmit fifo stores data of specified size or more. 2 transmission tfemp transmit fifo empty the transmit fifo is empty. 3 rdreq receive fifo transfer request the receive fifo stores data of specified size or more. 4 reception rfful receive fifo full the receive fifo is full. 5 tcrdy transmit control data ready the transmit control register is ready to be written. 6 control rcrdy receive control data ready the receive control data register stores valid data. 7 tfudf transmit fifo underflow serial data transmit timing has arrived while the transmit fifo is empty. 8 tfovf transmit fifo overflow write to the transmit fifo is performed while the transmit fifo is full. 9 rfovf receive fifo overflow serial data is received while the receive fifo is full. 10 rfudf receive fifo underflow the receive fifo is read while the receive fifo is empty. 11 fserr fs error a synchronous signal is input before the specified bit number has been passed (in slave mode). 12 error saerr assign error the same slot is specified in both serial data and control data. whether an interrupt is issued or not as the result of an interrupt source is determined by the siier settings. if an interrupt source is set to 1 and th e corresponding bit in siier is set to 1, an siof interrupt is issued. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 728 of 1458 rej09b0033-0300 (2) regarding transmit and receive classification the transmit sources and receive sour ces are signals indicating the state; after being set, if the state changes, they are automati cally cleared by the siof. when the dma transfer is used, a dma transfer re quest is pulled low (0 level) for one cycle at the end of dma transfer. (3) processing when errors occur on occurrence of each of the erro rs indicated as a st atus in sistr, the siof performs the following operations. ? transmit fifo underflow (tfudf) the immediately preceding transm it data is again transmitted. ? transmit fifo overflow (tfovf) the contents of the transmit fifo are protected, and the write operation causing the overflow is ignored. ? receive fifo ove rflow (rfovf) data causing the overflow is discarded and lost. ? receive fifo underflow (rfudf) an undefined value is output on the bus. ? fs error (fserr) the internal counter is reset according to the fsyn signal in which an error occurs. ? assign error (saerr) ? if the same slot is assigned to both serial data and control data, the slot is assigned to serial data. ? if the same slot is assigned to two control data items, data cannot be transferred correctly. section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 729 of 1458 rej09b0033-0300 21.4.9 transmit a nd receive timing examples of the siof se rial transmission and reception are shown in figures 21.13 to 21.19. (1) 8-bit monaural data (1) synchronous pulse method, falling ed ge sampling, slot no.0 used fo r transmit and receive data, an frame length = 8 bits siofsck siofrxd sioftxd siofsync l-channel data slot no.0 trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=0, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0000, fl[3:0]=0000 (frame length: 8 bits) tdre=0, rdre=0, cd1e=0, tdra[3:0]=0000, rdra[3:0]=0000, cd1a[3:0]=0000 specifications: 1 frame 1-bit delay figure 21.13 transmit and receive timing (8-bit monaural data (1)) section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 730 of 1458 rej09b0033-0300 (2) 8-bit monaural data (2) synchronous pulse method, falling ed ge sampling, slot no.0 used for transmit and receive data, and frame length = 16 bits siofsck siofrxd sioftxd siofsync l-channel data trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=0, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0000, fl[3:0]=0100 (frame length: 16 bits) tdre=0, rdre=0, cd1e=0, tdra[3:0]=0000, rdra[3:0]=0000, cd1a[3:0]=0000 slot no.0 slot no.1 specifications: 1 frame 1-bit delay figure 21.14 transmit and receive timing (8-bit monaural data (2)) (3) 16-bit monaural data (1) synchronous pulse method, falling ed ge sampling, slot no.0 used for transmit and receive data, and frame length = 64 bits siofsck siofrxd sioftxd siofsync l-channel data trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=0, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0000, fl[3:0]=1101 (frame length: 64 bits) tdre=0, rdre=0, cd1e=0, tdra[3:0]=0000, rdra[3:0]=0000, cd1a[3:0]=0000 slot no.0 slot no.1 slot no.2 slot no.3 specifications: 1 frame 1-bit delay figure 21.15 transmit and receive timing (16-bit monaural data (1)) section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 731 of 1458 rej09b0033-0300 (4) 16-bit stereo data (1) l/r method, rising edge sampling, slot no.0 used for left channel data, slot no.1 used for right channel data, and frame length = 32 bits siofsck siofrxd sioftxd siofsync l-channel data trmd[1:0]=11, tdle=1, rdle=1, cd0e=0, redg=1, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0000, fl[3:0]=1100 (frame length: 32 bits) tdre=1, rdre=1, cd1e=0, tdra[3:0]=0001, rdra[3:0]=0001, cd1a[3:0]=0000 r-channel data slot no.0 slot no.1 specifications: 1 frame no bit delay figure 21.16 transmit and receive timing (16-bit stereo data (1)) (5) 16-bit stereo data (2) l/r method, rising edge sampling, slot no.0 used for left-channel transmit data, slot no.1 used for left-channel receive data, slot no.2 used for right-channel transmit data, slot no.3 used for right- channel receive data, and frame length = 64 bits siofsck siofrxd sioftxd siofsync trmd[1:0]=01, tdle=1, rdle=1, cd0e=0, redg=1, tdla[3:0]=0000, rdla[3:0]=0001, cd0a[3:0]=0000, fl[3:0]=1101 (frame length: 64 bits), tdre=1, rdre=1, cd1e=0, tdra[3:0]=0010, rdra[3:0]=0011, cd1a[3:0]=0000 l-channel data r-channel data l-channel data r-channel data slot no.0 slot no.1 slot no.2 slot no.3 specifications: 1 frame no bit delay figure 21.17 transmit and receive timing (16-bit stereo data (2)) section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 732 of 1458 rej09b0033-0300 (6) 16-bit stereo data (3) synchronous pulse method, falling edge sampling, slot no.0 used for left-channel data, slot no.1 used for right-channel data, slot no.2 used for control channel 0 data, slot no.3 used for control channel 1 data, and frame length = 128 bits siofsck siofrxd sioftxd siofsync trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=1, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0010, fl[3:0]=1110 (frame length: 128 bits), tdre=1, rdre=1, cd1e=1, tdra[3:0]=0001, rdra[3:0]=0001, cd1a[3:0]=0011 l-channel data control channel 0 control channel 1 slot no.0 slot no.1 slot no.2 slot no.3 slot no.4 slot no.5 slot no.6 slot no.7 specifications: 1 frame 1 bit delay r-channel data figure 21.18 transmit and receive timing (16-bit stereo data (3)) (7) 16-bit stereo data (4) synchronous pulse method, falling edge sampling, slot no.0 used for left-channel data, slot no.2 used for right-channel data, slot no.1 used for control channel 0 data, slot no.3 used for control channel 1 data, and frame length = 128 bits siofsck siofrxd sioftxd siofsync trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=1, redg=1, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0001, fl[3:0]=1110 (frame length: 128 bits) tdre=1, rdre=1, cd1e=1, tdra[3:0]=0010, rdra[3:0]=0010, cd1a[3:0]=0011 l-channel data control channel 0 control channel 1 slot no.0 slot no.1 slot no.2 slot no.3 slot no.4 slot no.5 slot no.6 slot no.7 specifications: 1 frame 1 bit delay r-channel data figure 21.19 transmit and receive timing (16-bit stereo data (4)) section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 733 of 1458 rej09b0033-0300 (8) synchronization-pulse output mode at end of each slot (syncat bit = 1) synchronous pulse method, falling edge sampling, slot no.0 used for left-channel data, slot no.1 used for right-channel data, slot no.2 used for control channel 0 data, slot no.3 used for control channel 1 data, and frame length = 128 bits in this mode, valid data must be set to slot no. 0. siofsck siofrxd sioftxd siofsync trmd[1:0]=00 or 10, tdle=1, rdle=1, cd0e=1, redg=0, tdla[3:0]=0000, rdla[3:0]=0000, cd0a[3:0]=0010, fl[3:0]=1110 (frame length: 128 bits), tdre=1, rdre=1, cd1e=1, tdra[3:0]=0001, rdra[3:0]=0001, cd1a[3:0]=0011 l-channel data r-channel data control channel 0 control channel 1 slot no.0 slot no.1 slot no.2 slot no.3 slot no.4 slot no.5 slot no.6 slot no.7 specifications: 1 frame figure 21.20 transmit and recei ve timing (16-bit stereo data) section 21 serial i/o with fifo (siof) rev. 3.00 jan. 18, 2008 page 734 of 1458 rej09b0033-0300 21.5 usage notes 21.5.1 regarding sync signal high width when restarting transmission in master mode 2 (1) problem if sync signal output is enabled (fse bit = 1), while output of the sync signal is disabled by clearing the sictr.fse bit in master mode 2 to 0, the high period of the sync signal may more quickly become 1 bit long with the rising edge of the sync signal in the head frame. however, this period will not be generated after the second frame. sync txd 17 bit width 32 bit (valid data) 32 bit (valid data) 1 bit long 16 bit width 16 bit width 16 bit width figure 21.21 frame length (32-bit) (2) how to avoid the problem to avoid this problem, either counte r-measure (a) or (b) is recommended. (a) when outputting data to the head frame, write dummy data to the transmission fifo and write valid data after the second frame. the data of the head frame should be read and omitted at the receive side. (b) use a configuration that does not occur malfunction, even if the period of the sync signal becomes 1 bit longer than that of the value set in the head frame. section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 735 of 1458 rej09b0033-0300 section 22 analog front end interface (afeif) this lsi has an afe interface that supports soft waremodem. this afe interface can efficiently execute the modem processing, beca use it includes 128 stages of fifo for each of transmission and reception. this afe interf ace also includes the interface to data access arrangement (daa) such as dial pulse generator circuit and ringing de tection. therefore, it is possible to establish a modem system with a minimum of hardware. 22.1 features ? serial interface with fifo ? clock synchronized serial interface ? transmit/receive fifo size is 16 bits (maximum) 128 words ? transmit/receive interrupt thre shold size is programmable ? dial pulse generator circuit is included ? ringing detection (calling signal) function is included figure 22.1 shows a block diagram of afeif. bus i/f 16 16 16 16 16 32 peripheral bus ringing detector dial pulse generator control registers transmit fifo 16 bits 128 words afe control word afe status word hc control p/s s/p afe_rxin afe_hc1 afe_txout afe_sclk afe_fs afe_rlycnt afe_rdet receive fifo 16 bits 128 words 16 16 16 figure 22.1 block di agram of afe interface section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 736 of 1458 rej09b0033-0300 22.2 input/output pins table 22.1 shows the pins for afe interface. table 22.1 pin configuration pin name i/o function afe_rdet input ringing signal input afe_rlycnt output on-hook control signal afe_sclk input shift clock afe_fs input frame synchronization signal afe_rxin input serial receive data afe_hc1 output afe hardware control signal afe_txout output serial transmit data 22.3 register configuration registers for afeif are shown below. byte access registers to these is inhibited. ? afeif control register 1 (actr1) ? afeif control register 2 (actr2) ? afeif status register 1 (astr1) ? afeif status register 2 (astr2) ? make ratio count register (mrcr) ? minimum pose count register (mpcr) ? dial number queue (dpnq) ? ringing pulse counter (rcnt) ? afe control data register (acdr) ? afe status data register (asdr) ? transmit data fifo port (tdfp) ? receive data fifo port (rdfp) section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 737 of 1458 rej09b0033-0300 22.3.1 afeif control register 1 and 2 (actr1, actr2) actr is the control register for afeif and is composed of actr1 and actr2. actr1 is mainly used for fifo control commands. actr2 is used for afe control commands and daa control commands. ? actr1 bit bit name initial value r/w description 15 hc 0 r/w afe hardware control this bit controls afe. afe_hc1 signal is made to high directly often the next serial transmit data transfer, when this bit is written to 1. then acdr data (afe control word) is transferred by founding the second afe.fs. afeif module automatically makes afe_hc1 signal to low and hc bit to 0, directly after transferring the afe control word. see section 22.4.2, afe interface for more detail about afe control sequences. 14 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 dlb 0 r/w fifo digital loop back 0: normal operation 1: digital loop back between transmit fifo and receive fifo is performed. in this time the transmit data is output to afe_txout, too. 6, 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 2 ffsz2 ffsz1 ffsz0 0 0 0 r/w r/w r/w fifo interrupt size set 2 to 0 specifies the size of fifo. fifo size to generate interrupt (tfe, rff, the, and rhf) is assigned as listed in table 22.2. section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 738 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 te 0 r/w transmit enable 0: transmit operation is disabled. the read pointer of fifo is stacked to the first address. write pointer is reset when 0 is written to this bit. tfem and them bits in astr1 is set to 1 at that time. 1: transmit operation is enabled. 0 re 0 r/w receive enable 0: receive operation is disabled. the read /write pointer is fixed to the first address. bits rffm and rhfm in astr1 are set to 1 at that time. 1: receive operation is enabled table 22.2 fifo interrupt size description bit 4: ffsz2 bit 3: ffsz1 bit 2: ffsz0 fifo size tfe/rff the/rhf 0 0 0 128 128 empty/full 64 empty/full (initial value) 1 64 64 empty/full 32 empty/full 1 0 32 32 empty/full 16 empty/full 1 16 16 empty/full 8 empty/full 1 0 0 8 8 empty/full 4 empty/full 1 4 4 empty/full 2 empty/full 1 0 2 2 empty/full 1 empty/full 1 96 96 empty/full 48 empty/full section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 739 of 1458 rej09b0033-0300 ? actr2 bit bit name initial value r/w description 15 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 dpst 0 r/w dial pulse start start bit of dial pulse. dial number within the dpnq register is output to afe_rlycnt as specified by pps, mrcr and mpcr. after all dial number is output, dpe interrupt is generated to modify the dpst bit to 0. see section 22.4.3, daa inte rface for more detail about dial pulse output sequence. take care that afe_rlycnt must be "h" to enable dial pulse generating circuit 3 pps 0 r/w dial pulse duration set 0: 10 pps 1: 20 pps 2 rcen 0 r/w ringing counter enable 0: stop ringing counter 1: start ringing counter note: see section 22.4.3, daa interface for more detail about how to count. 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 rlyc 0 r/w relay control the signal controls hook relay. 0: on hook state. afe_rlycnt goes low level. 1: off hook state. afe_rlycnt goes high level. section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 740 of 1458 rej09b0033-0300 22.3.2 make ratio count register (mrcr) mrcr is the counter that specifies make ratio of dial pulse. make interval is specified with afe_fs as base clock of 9,600 hz. pulse signal is not output when an invalid data (a data that is greater than 1e0h in case of pps = 1 (20 pps), or a data that is greater than 3c0h in case of pps = 0 (10 pps)) was input. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 to 0 mrcr9 to mrcr0 0 r/w specifies make ratio of dial pulse. 22.3.3 minimum pause count register (mpcr) mpcr is a counter that sets the dial number interv al of the dial pulse. th e interval is specified with afe_fs as base clock of 9600 hz. bit bit name initial value r/w description 15 to 0 mpcr15 to mpcr0 0 r/w sets the dial number interval of the dial pulse. 22.3.4 afeif status register 1 and 2 (astr1, astr2) astr is the control register for afeif, and composed of astr1 and astr2. astr1 is mainly used for transmit/receive fifo interrupt contro l commands. astr2 is us ed for daa interrupt control commands. see section 22.4.1, interrupt timing for more detail about interrupt handling. (1) afeif status register 1 (astr1) astr1 is composed by interrupt status flags (4 bits) relating transmit/receive fifo and mask flags (4 bits) for transmit/receive fifo interrupt signal. status flag displays full/empty interrupt status of transmit/receive fifo and half size in terrupt status for fifo. fifo empty (tfe) and fifo half size interrupt (the) sh ows "1" as initial valu e, because transmit fifo is empty after power on reset. these interrupt flags are to be cl eared with the data writ e / read action to fifo from cpu. section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 741 of 1458 rej09b0033-0300 each interrupt mask flag is able to prohibit inte rrupt generation of each inte rrupt that indicated in interrupt status flag. every mask bits are automatically set when te or re bit are modified to 1. tfem and them are 1 when te = 0. rffm and rh fm are 1 when re = 0. each mask bit is reset as 1. bit bit name initial value r/w description 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 tfem 1 r/w transmit fifo empty interrupt mask 0: tfe interrupt enable 1: tfe interrupt masked 10 rffm 1 r/w receive fifo full interrupt mask 0: rff interrupt enable 1: rff interrupt masked 9 them 1 r/w threshold of transmit fifo empty interrupt mask 0: the interrupt enable 1: the interrupt masked 8 rhfm 1 r/w threshold of receive fifo full interrupt mask 0: rhf interrupt enable 1: rhf interrupt masked 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 tfe 1 r transmit fifo empty interrupt 0: normal state [clearing condition] ? data are written into fifo 1: txfifo empty interrupt [setting conditions] ? reset ? no effective data in area of fifo ? te bit (actr1) is set to 0 (tfem bit is set to 1) section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 742 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 rff 0 r receive fifo full interrupt 0: normal state [clearing conditions] ? reset ? number of data in fifo becomes smaller than the size that is indicated with ffsz (actr1) ? re bit (actr1) is set to 0 1: rx fifo full interrupt [setting condition] ? specified size with ffsz (actr1) of receive data is accumulated into fifo 1 the 1 r transmit fifo half size empty 0: normal state [clearing condition] ? number of valid data in fifo becomes greater than the half of the size that is indicated by ffsz 1: tx fifo half size interrupt [setting conditions] ? reset ? number of valid data in fifo becomes smaller than the half of the size that is indicated with ffsz ? te bit (actr1) is set to 0 (them bit is set to 1) section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 743 of 1458 rej09b0033-0300 bit bit name initial value r/w description 0 rhf 0 r receive fifo half size full 0: normal state [clearing conditions] ? reset ? number of data in fifo becomes smaller than the half of the size that is indicated by ffsz ? re bit (actr1) is set to 0 1: rx fifo half size interrupt [setting condition] ? the half of specified size with ffsz (actr1) of receive data is accumulated into fifo (2) afeif status register 2 (astr2) astr2 is the register that is composed of interrupt status flag (2 bits) relating daa control and mask flag (2 bits) of interrupt signals for daa control. status flags shows statuses of ringing detect interrupt, end of dial pulse output interrup t. interrupt flags are cleared by 0 write after read action of this register. each interrupt sign al can be masked by each interrupt masks. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 dpem 1 r/w dial pulse end interrupt mask 0: interrupt enable 1: interrupt mask 8 rdetm 1 r/w ringing detect mask 0: ringing interrupt enable 1: ringing interrupt mask 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 744 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 dpe 0 r/w dial pulse end 0: normal state [clearing conditions] ? reset ? interrupt status 1 is read and then 0 is written to this bit 1: dial pulse end interrupt [setting conditions] ? output of all of dial pulse sequences completed or end command 0h detected ? illegal end (unspecified dial number and dpst set when rlyc bit (actr2) is low level) 0 rdef 0 r/w ringing detect 0: normal state [clearing conditions] ? reset ? interrupt status 1 is read and then 0 is written to this bit 1: ringing waveform detect [setting condition] ? ringing waveform is input to afe_rdet pin (latched at rising edge) section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 745 of 1458 rej09b0033-0300 22.3.5 dial pulse number queue (dpnq) this is the dial pulse number queue up to 4 digits which has 4-bits registers. this queue generates dial pulse according to the following table in the order of dial pulse number. a dial-pulse-end interrupt is sent out after dn3 is output or if 0h or a value other than the corresponding data is detected. bit bit name initial value r/w description 15 to 12 dn03 to dn00 all 0 r/w dn0 11 to 8 dn13 to dn10 all 0 r/w dn1 7 to 4 dn23 to dn20 all 0 r/w dn2 3 to 0 dn33 to dn30 all 0 r/w dn3 table 22.3 telephone number and data tel no. corresponding data 0 ah 1 1h 2 2h 3 3h 4 4h 5 5h 6 6h 7 7h 8 8h 9 9h pause fh end 0h section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 746 of 1458 rej09b0033-0300 22.3.6 ringing pulse counter (rcnt) the result of counting 1 cycle of ringing waveform with afe_fs is shown here. bit bit name initial value r/w description 15 to 0 rcnt15 to rcnt0 all 0 r/w ringing counter value the result of counting 1 cycle of input ringing waveform with afe_fs (output of afe). see section 22.4.3, daa inte rface for more detail about the ringing detect sequence. 22.3.7 afe control data register (acdr) acdr is the register to store th e afe control word. after 1 is written to hc bit (actr1), data is transferred to afe at the timing of 3rd fs. bit bit name initial value r/w description 15 to 0 acdr15 to acdr0 all 0 r/w store the afe control word. 22.3.8 afe status data register (asdr) asdr is the register to store the afe status word. after 1 is written to hc bit (actr2), data is transferred to asdr from afe at the timing of 3rd fs. bit bit name initial value r/w description 15 to 0 asdr15 to asdr0 all 0 r store the afe control word. section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 747 of 1458 rej09b0033-0300 22.3.9 transmit data fifo port (tdfp) tdfp is the write only port for tr ansmit fifo. transmit fifo has 128 stages (maximum), and can generate interrupt of the data empty as well as of the threshold size specified by ffsz (actr1). directly after the reset and when te (actr1) bit is 0, the pointer of fifo is set to the first address and data becomes empty. the interrupt will occur when the te bit (actr1) is written to 1 at that state. in normal case, te bit should be changed after writing data into transmit fifo. bit bit name initial value r/w description 15 to 0 tdfp15 to tdfp0 all 0 w write only port for transmit fifo. 22.3.10 receive data fifo port (rdfp) rdfp is the read only register for receive fifo . receive fifo has 128 stages (maximum), and can generate interrupt of the data full as well as of the threshold size specified by ffsz (actr1). directly after the reset and when re bit (actr1) is 0, the pointer of fifo is fixed at the first address and data from rdfp becomes undetermined. bit bit name initial value r/w description 15 to 0 rdfp15 to rdfp0 undefined r read only register for receive fifo. section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 748 of 1458 rej09b0033-0300 22.4 operation 22.4.1 interrupt timing afe interface module generates 3 types of interrupt: fifo data transfer, ri nging detect, and dial pulse transmit end. the timing of each interruption is described below. (1) fifo interrupt timing figure 22.2 shows interrupt timing of data transfer fifo. transmit fifo generates the tfe and the interrupts after the last data is transfer red shift register. receive fifo generates the rff and rhf interrupt after the last data or specified word is transferred from shift register to fifo. afe_fs data 1 data 2 half-1 half first first+1 half-1 half afe_txout tfe/tte afe_fs afe_rxin rff/rtf figure 22.2 fifo interrupt timing section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 749 of 1458 rej09b0033-0300 (2) ringing interrupt timing as the figure 22.3 shows, the ringing signal from the line is transformed to rectangular wave and then input to afeif. the interrupt is generate d at the falling edge of input wave in afeif module. ringing wave input wave interrupt occur figure 22.3 ringing interrupt occurrence timing (3) dial pulse interrupt timing dial pulse interrupt is generated in the dial pulse transmit sequence when afeif reads 0h (end) data from dpnq register or all of 4 digits are output. refer to section 22.4.3, daa interface about dial pulse sequence. (4) interrupt generator circuit interrupt is generated as is shown in figure 22.4. that is, afeifi signal is generated by performing or operation on the four signals from astr1 in fifo interrupt control and the two signals from astr2 in daa interrupt control, and then sent out to intc as one interrupt signal. astr1 (fifo control) afeifi interrupt mask interrupt factor astr2 (daa control) interrupt mask interrupt factor 2 4 2 4 2 4 figure 22.4 interrupt generator section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 750 of 1458 rej09b0033-0300 22.4.2 afe interface (1) serial data transfer specification the specification for serial data transfer is base on that of stlc7550, which is an afe manufactured by st microelectronics. stlc7550 has a self-oscillation mode, and flame synchronous signal afe_fs used for serial transfer and serial bit clock afe_sclk are supplied by afe. figure 22.5 shows th e serial transfer interface. af ter outputting the valid data, afe_txout holds the value of lsb. afe_fs msb lsb afe_sclk afe_txout afe_rxin sampling period figure 22.5 afe serial interface section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 751 of 1458 rej09b0033-0300 (2) hc control sequence afeif module supports hardware control stlc7550 that is an afe manufactured by st microelectronics. figure 22.6 shows the afe control sequence. data word data word control word data word write 1 to hc bit of actr1 write "1" to hc bit of actr1 fs for data fs for data fs for data fs for data fs for data afe mode change hc1 goes to 0 hc1 goes to 1 fs for control word data data data data data data sampling period 1/2 sampling period mode change (3) (5) (4) (2) (1) afe_fs afe_txout afe_hc1 afeif stlc7550 hc0: kept to 1 1. if the cpu write " 1 " to the hc bit of actr1, the aefif drives afe_hc1 to " h " right after transmit next data. 2. afe fetches the hc1's status of " h " at rising edgge of next afe_fs. 3. afe output the fs at the next 1/2 sampling period and then afeif transfers the control word in synchronization with afe_fs. 4. afeif keeps afe_hc1 to " h " for 2nd afe_fs and return to " l " after transmit the control word. 5. afe fetches the afe_hc1's status of " l " and changes the mode of itself. figure 22.6 afe control sequence section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 752 of 1458 rej09b0033-0300 22.4.3 daa interface figure 22.7 shows the blocks diagram of daa circuit. ringing detect and dial pulse sending sequence are described below. afe_rlycnt afe_rdet afe (stlc7550) afeif tip ring hyblid circuit dc holding circuit hook relay ringing detector figure 22.7 daa block diagram (1) ringing detect sequence after the first ringing interrupt occurs, counting starts with writing 1 into rcen bit of ctr2. afe must be operating before counting, because periodic counter counts afe_fs from falling edge to next falling edge. the value of rcntv register is effective only af ter 2nd interrupt generation, because the value of rcntv register is transferred from counter with a trigger of ending of 1st period cycle. rcntv will be 258 h (600 in decimal) if ringing cycle is 16 hz and counted by 9600 hz which is default value of afe_fs. figure 22.8 shows detecting sequence of ringing. section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 753 of 1458 rej09b0033-0300 count up rcntv set rcntv set rcntv set rcntv set 1. first int occur. rcen (actr2) turns on. 2. from 2nd int, read the rcntv. 3. after acknowledge the ringing, rcen (actr) turns off and goes to off hook operation. figure 22.8 ringing detect sequence (2) dial pulse sending sequence a dial pulse is generated according to the condition s that are specified in actr2, and is sent out to afe_rlycnt. as the basic clock for generating the dial pulse is afe_fs that is input from afe, it is necessary to make afe in operating state. an example of control sequence for dial pulse sending is shown below. note that this sequence cannot be operated when rlyc bit (actr2) is low. [conditions] make ratio: 33% pulse interval: 20 pps minimum pause: 600 ms dial number: 0,1234567 ("," means pause) [control sequence] 1. set pps (actr2) "1", mkr "9eh1", mnrpcnt "1680h" 2. set dpnq "af12h". 3. set rlyc "h". (off hook) 4. detect dial tone or wait speci fic period. (controlled by software) 5. write "1" to dpst (actr2). (start sending dial pulse) section 22 analog front end interface (afeif) rev. 3.00 jan. 18, 2008 page 754 of 1458 rej09b0033-0300 6. after 4 digits of dial pulses are sent, in terrupt is generated. (dpst is reset to "0") 7. set dpnq1 "3456h". 8. write "1" to dpst (actr2). 9. after 4 digits of dial pulses are sent, in terrupt is generated. (dpst is reset to "0") 10. set dpnq2 "70xxh". 11. write "1" to dpst (actr2). 12. after 1 digit of dial pulse is sent, interrupt is generated. (dpst is reset to "0", and finish sending) 22.4.4 wake up ringing interrupt system wake up function by the ringing signal from telephone line is realized by inputting afe_rdet signal, which is an input signal for ringing, to pint pin. section 23 usb pin multiplex controller rev. 3.00 jan. 18, 2008 page 755 of 1458 rej09b0033-0300 section 23 usb pin multiplex controller 23.1 features the usb multiplex controller controls the data path to usb transceiver from usb host controller port 1 or usb function controller. both usb host port 1 and usb function contro ller are connected to usb transceiver 1 via multiplexer that is controlled by utrctl register. the usb host controller port 2 and usb transceiver 2 are connected one-to-one. usb tr ansceiver 1 can be connected to usb host controller or usb function controller, while usb transceiver 2 can only be connected to the usb host controller. because these ports and transceivers are contro lled individually, usb transceiver 2 can be connected to either the usb host controller or the usb function controller regardless its status. the signals to usb transceiver are us ed as external pins usb1d _**** which are multiplexed with pins 113 to 123. figure 23.1 shows the connections between the on-chip usb host controller of this lsi, the usb function controller, and the on-chip 2-port usb transceiver. usb host usb function pwr_en usb2_pwr_en usb2_ovr_current usb2_p usb2_m usb1_pwr_en/usbf_uplup usb1_ovr_current / usbf_vbus usb1d_ **** usb1_p usb1_m pwr_en vbus pwr_en/ pull-up control pin multiplexer usb host/function transceiver signals multiplexer ovr_current / vbus multiplexer ovr_current ovr_current transceiver signal usb digital signal transceiver signal control port 1 port 2 usb transceiver 2 usb transceiver 1 power power control transceiver control transceiver port 1 power control transceiver selector selector figure 23.1 block diagra m of usb pin multiplexer section 23 usb pin multiplex controller rev. 3.00 jan. 18, 2008 page 756 of 1458 rej09b0033-0300 23.2 input/output pins usb pin multiplexer controller has pins that are shown in tables 23.1, 23.2, and 23.3 table 23.1 pin configuration (digital transceiver signal) name pin name i/o description rcv pin usb1d_rcv input input pin for re ceive data from differential receiver dpls pin usb1d_dpls input input pin for d + signal from receiver dmns pin usb1d_dmns input input pin for d ? signal from receiver txdpls pin usb1d_txdpls output d + transmit output pin txenl pin usb1d_txenl output driver output enable pin suspend pin usb1d_suspend output tran sceiver suspend state output pin speed pin usb1d_speed output transceiver speed control pin txse0 pin usb1d_txse0 output se0 state output pin note: the pins shown in table 23.1 are used for connecting an external usb transceiver, and cannot be used when the on-chip usb transceiver is connected. table 23.2 pin configuration (analog transceiver signal) name pin name i/o description 1p pin usb1_p i/o d+ port1 transceiver pin 1m pin usb1_m i/o d? port1 transceiver pin 2p pin usb2_p i/o d+ port2 transceiver pin 2m pin usb2_m i/o d? port2 transceiver pin note: the pins shown in table 23.2 can be used as two ports usb host controller pins, or one port usb host controller pins and one port usb function controller pins. make these pins open, when they are not used. section 23 usb pin multiplex controller rev. 3.00 jan. 18, 2008 page 757 of 1458 rej09b0033-0300 table 23.3 pin configurat ion (power control signal) name pin name i/o description usb1 power enable/pull-up control pin usb1_pwr_en/ usbf_uplup output usb port 1 power enable control * / pull- up control output usb2 power enable pin usb2_pwr_en output usb port 2 power enable control usb1 over current /monitor pin usb1_ovr_current / usbf_vbus input usb port 1 over-current detect/ usb cable connection monitor pin * usb2 over current pin usb2_ovr_current input usb port 2 over-current detect note: the pins shown in table 23.3 can be used fo r power control of usb. pins for port 1 (pins with * ) have the functions that are multiplexed f unctions of usb controller and usb function controller. table 23.4 pin configuration (clock signal) name pin name i/o description usb external clock extal_usb input conn ects a crystal resonator for usb. also used to input an external clock for usb (48 mhz input). usb crystal xtal_usb output connects a usb crystal resonator for usb. section 23 usb pin multiplex controller rev. 3.00 jan. 18, 2008 page 758 of 1458 rej09b0033-0300 23.3 register descriptions the usb pin multiplexer controller has the following register. ? usb transceiver control register (utrctl) 23.3.1 usb transceiver co ntrol register (utrctl) utrctl controls the selection of transceiver function and signal source related to the usb port 1. bit bit name initial value r/w description 15 to 9 ? all 0 r/w reserved these bits are always read as all 0s. the write values should always be all 0s. 8 drv 0 r/w see section 34, pi n function controller (pfc). 7 to 2 ? all 0 r/w reserved these bits are always read as all 0s. the write values should always be all 0s. 1 usb_trans 0 w usb port 1 transceiver select 0: usb transceiver is enabled 1: usb digital signals output is enabled 0 usb_sel 1 w usb port 1 signal source select 0: port 1 of usb host controller is used 1: port 1 of usb function controller is used section 23 usb pin multiplex controller rev. 3.00 jan. 18, 2008 page 759 of 1458 rej09b0033-0300 23.4 examples of external circuit 23.4.1 example of the connection between usb function controller and transceiver figures 23.2 and 23.3 show example connections of usb function controller and transceiver. figures 23.2 shows connections when using the on-chip usb transceiver. figures 23.3 shows connections when not using the on-chip usb transceiver. when using the usb function controller, the signals must be input to the cable connection monitor pin ujbf_vbus. the usbf_vbus pin is multiplexed with the usb1_ovr_current pin, and writing 1 to bit 0 (usb_sel) of utrctl selects the usbf_vbus pin functions. according to the status of the usbf_vbus pin, the usb function controller recognizes whether the cable is connected/disconnected. also, pin d+ must be pulled up in order to notify the usb host/hub that the connection is established. the sample circuits in figures 23.2 and 23.3 use the usb1_pwr_en pin for pull-up control. this lsi usb function usb connector ic allowing voltage application when system power is off usb1_pwr_en usbf_vbus usb1_p usb1_m vbus ic1 ic allowing voltage application when system power is off ic2 d + d ? gnd usb1d_speed usb1d_txenl usb1d_txdpls usb1d_txseo usb1d_rcv usb1d_dpls usb1d_dmns usb1d_suspend 3.3v 5v 1.5k ? 27 ? 27 ? figure 23.2 example 1 of transceiver connection for usb function controller (on-chip transceiver is used) section 23 usb pin multiplex controller rev. 3.00 jan. 18, 2008 page 760 of 1458 rej09b0033-0300 this lsi usb function usb connector usb1_pwr_en usbf_vbus vbus d + d ? gnd pdiusbp11a etc. speed d + d ? oe vpo vmo/fseo rcv vp vm suspend usb1d_speed usb1d_txenl usb1d_txdpls usb1d_txseo usb1d_rcv usb1d_dpls usb1d_dmns usb1d_suspend 3.3v 5v 1.5k ? ic1 ic allowing voltage application when system power is off ic2 ic allowing voltage application when system power is off figure 23.3 example 2 of transceiver connection for usb function controller (on-chip transceiver is not used) ? d+ pull-up control control d+ pull-up by using usb1_pwr_en pin in the system when the connection? notification (d+ pull-up) to usb host or hub is wished to be inhibited (i.e., during high- priority processing or initialization processing). the d+ pull-up control signal and usbf_vbus pin input signal should be controlled by using the usb1_pwr_en pin and the usb cable vbus (and circuit) as is shown in examples of figures 23.2 and 23.3 d+ pull-up is inhibited when the usb1_pwr_en pin is low in examples of figures 23.3 and 23.5. use an ic such that allows voltage appli cation when system power is off (for example, hd74lv1g126a) for the pull-up control ic (ic2 in figures 23.2 to 23.5). (the udc core in this lsi holds the powered state when usbf_vbus pin is low, regardless of the d + /d ? state.) section 23 usb pin multiplex controller rev. 3.00 jan. 18, 2008 page 761 of 1458 rej09b0033-0300 ? detection of usb cable connection/disconnection as usb function controller in this lsi manages the state by hardware, usb_vbus signal is necessary to recognize connection or disconnec tion of the usb cable. the power supply signal (vbus) in the usb cable is used for usbf_vbus. however, if the cable is connected to the usb host or hub when the power of usb function controller (this lsi?installed system) is off, a voltage of 5 v will be applied from the usb host or hub. therefore, use an ic such that allows voltage application wh en system power is off (for example, hd74lv1g08a) for the ic1 in figures 23.2 to 23.5. to recover from the standby state with the usb cable connected, the irq pin should be connected to the usb cable. (rec overy from the software standby state cannot be performed by a usb connection/disconnection interrupt.) 23.4.2 example of the connection between usb host controller and transceiver figures 23.4 and 23.5 show example connections of the usb host controller and transceiver. figure 23.4 shows an example connection using the built-in transceiver 1. by using the usb2_ovr_current , usb2_pwr_en, usb2_p, and usb2_m pins in an external circuit similar to that in figure 23.4, you can also use built-in usb transceiver 2. figure 23.5 shows an example connection when not using the built-in usb transceiver. when using the usb host controller, a separate lsi must be used for usb power bus co ntrol (equivalent to the usb power control lsis in figures 23.4 and 23.5). make sure the lsi has the power supply capacity to satisfy the usb standard, and select one that has an overcurrent protection function. configure the system so that the input to the usb1_ovr_current pin is low on detection of an overcurrent. section 23 usb pin multiplex controller rev. 3.00 jan. 18, 2008 page 762 of 1458 rej09b0033-0300 this lsi usb host usb connector usb1_pwr_en usb1_ovr_current gnd d + d ? usb power control lsi 15k ? 15k ? usb1_p usb1_m 5v 27 ? 27 ? figure 23.4 example 1 of transcei ver connection for usb host controller (on-chip transceiver is used) section 23 usb pin multiplex controller rev. 3.00 jan. 18, 2008 page 763 of 1458 rej09b0033-0300 this lsi usb host usb connector usb1_pwr_en usb1_ovr_current gnd d+ d- pdiusbp11a etc. speed usb power control lsi d + d ? 15k ? 15k ? oe vpo vmo/fseo rcv vp vm suspend usb1d_speed usb1d_txenl usb1d_txdpls usb1d_txseo usb1d_rcv usb1d_dpls usb1d_dmns usb1d_suspend 5v figure 23.5 example 2 of transceive r connection for usb host controller (on-chip transceiver is not used) 23.5 usage notes 23.5.1 about the usb transceiver usb transceiver is included in this lsi. it is also possible to connect an external transceiver according to the setting in expfc register (see figures 23.3 and 23.5). in this case, ask the manufacturer of the transceiver about the reco mmended circuit that is used between the usb transceiver and usb connectors. 23.5.2 about the examples of external circuit these examples of transceiver connection in this chapter are for reference only, therefore proper operation is not guaranteed with these circuit ex amples. if system countermeasures are required for external surges and esd nois e, use a protective diode, etc. section 23 usb pin multiplex controller rev. 3.00 jan. 18, 2008 page 764 of 1458 rej09b0033-0300 section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 765 of 1458 rej09b0033-0300 section 24 usb host controller (usbh) the usb host controller module incorporated in this lsi supports open host controller interface (open hci) specification for usb as we ll as the universal serial bus specification ver.1.1. the open hci specification for the usb is a regist er-level description of host controller for the usb, which in turn is described by the usb specification. it is necessary to refer open hci specification to develop drivers for this usb host controller and hardware. 24.1 features ? support open hci standard ver.1.0 register set ? support universal serial bus standard ver.1.1 ? root hub function ? support full speed (12 mbps) mode and low speed (1.5 mbps) mode ? support overcurrent detection ? support 127 endpoints control in maximum ? possible to use only the sdram area of area 3 as transmit data and descriptor. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 766 of 1458 rej09b0033-0300 24.2 input/output pins pin configuration of the usb host controller is shown in table 24.1. for the detailed method for setting each pin, s ee section 23, usb pin multiplex controller. table 24.1 pin configuration pin name pin name i/o function usb1 power enable/pull-up control pin usb1_pwr_en output usb port 1 power enable control usb2 power enable pin usb2_pwr_en output usb port 2 power enable control usb1 overcurrent/monitor pin usb1_ovr_current / usbf_vbus input usb port 1 over-current detect/ usb cable connection monitor pin usb2 overcurrent pin usb2_ovr_current input usb port 2 over-current detect 1p pin usb1_p i/o d + port 1 transceiver pin 1m pin usb1_m i/o d ? port 1 transceiver pin 2p pin usb2_p i/o d + port 2 transceiver pin 2m pin usb2_m i/o d ? port 2 transceiver pin speed pin usb1d_speed output transceiver speed control pin usb external clock extal_usb input c onnect a crystal resonator for usb. alternatively, an external clock may be input for usb (48 mhz). usb crystal xtal_usb output connect a crystal resonator for usb. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 767 of 1458 rej09b0033-0300 24.3 register descriptions the usbh has the fo llowing registers. ? hc revision register (usbhr) ? hc control register (usbhc) ? hc command status register (usbhcs) ? hc interrupt status register (usbhis) ? hc interrupt enable register (usbhie) ? hc interrupt disable register (usbhid) ? hc hcca register (usbhhcca) ? hc period current ed register (usbhpced) ? hc control head ed register (usbhched) ? hc control current ed register (usbhcced) ? hc bulk head ed register (usbhbhed) ? hc bulk current ed register (usbhbced) ? hc done head ed register (usbhdhed) ? hc fm interval register (usbhfi) ? hc fm remaining register (usbhfr) ? hc fm number register (usbhfn) ? hc periodic start register (usbhps) ? hc ls threshold register (usbhlst) ? hc rh descriptor a register (usbhrda) ? hc rh descriptor b register (usbhrdb) ? hc rh status register (usbhrs) ? hc rh port status 1 register (usbhrps1) ? hc rh port status 2 register (usbhrps2) section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 768 of 1458 rej09b0033-0300 24.3.1 hc revision register (usbhr) bit bit name initial value r/w description 31 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 5 4 3 2 1 0 rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 0 0 0 1 0 0 0 0 r r r r r r r r revision these read only bits include the bcd expression of the hci specification version implemented for the host controller. the value h'10 corresponds to version 1.0. all hci implementation complying with this specification have the value of h'10. 24.3.2 hc control register (usbhc) the hc control register defines the operation mode for the host controller. the bits of this register are amended only by the host controller driver (hcd) other than hcfs and rwc. bit bit name initial value r/w description 31 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 rwe 0 r/w remote wakeup enable this bit is set by hcd to enable/disable the remote wakeup function at the same time as the detection of an upstream resume signal. this function is not supported. be sure to write 0. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 769 of 1458 rej09b0033-0300 bit bit name initial value r/w description 9 rwc 0 r/w remote wakeup connected this bit indicates whether the host controller supports a remote wakeup signal or not. when the remote wakeup is supported and used in the system, the host controller must set this bit between post in the system firmware. the host controller clears the bit at the same time of the hardware reset, however, does not change at the same time as the software reset. this function is not supported. be sure to write 0. 8 ir 0 r/w interrupt routing this bit determines the routin g of interrupts generated by the event registered in usbhis. hcd clears this bit at the same time as the hardware reset, however, does not clear at the same time as the software reset. hcd uses this bit as a tag to indicate the owne rship of the host controller. 0: all interrupts are routed to normal host bus interrupt mechanism 1: interrupts are routed to smi 7 6 hcfs1 hcfs0 0 0 r/w r/w host controller functional state hcd determines whether the host controller has started to route sof after having read the sf bit of usbhis. this bit can be changed by the host controller only in the usbsuspend state. the host cont roller can move from the usbsuspend state to the us bresume state after having detected the resume signal from the downstream port. in the host controller, usbsus pend is entered after the software reset so that usbreset is entered after the hardware reset. the former resets the route hub. 00: usb reset 01: usb resume 10: usb operational 11: usb suspend section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 770 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 ble 0 r/w bulk list enable this bit is set to enable the processing of the bulk list in the next frame. when this bit is cleared by hcd, the processing of the bulk list is not carried out after next sof. the host controller checks this bit when processing this list. when disabling, hcd can correct the list. when usbhbced indicates ed to be deleted, hcd should hasten the pointer by updat ing usbhbced before re- enabling the list processing. 0: bulk list processing is not carried out 1: bulk list processing is carried out 4 cle 0 r/w control list enable this bit is set to enable the processing of the control list in the next frame. if cleared by hcd, the processing of the control list is not carried out after next sof. the host controller must check this bit whenever the list will be processed. when disabling, hcd can correct the list. when usbhcced indicates ed to be deleted, hcd should hasten the pointer by updating usbhcced before re-enabling the list processing. 0: control list processing is not carried out 1: control list processing is carried out 3 ie 0 r/w isochronous enable this bit is used by hcd to enable/disable the processing of isochronous ed. while processing the periodic list, hc will check the status of this bit when it finds an isochronous ed (f =1). if set (enabled), the host controller continues to process ed. if cleared (disabled), the host controller stops the proce ssing of the periodic list (currently includes only isochronous ed) and starts to process the bulk/control list. setting this bit is guaranteed to be valid in the next frame (not in the current frame). 0: processes isochronous ed 1: processes the bulk/control list section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 771 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 ple 0 r/w periodic list enable this bit is set to enable the processing of the periodic list. if cleared by hcd, no periodic list processing is carried out after next sof. hc must check this bit before hc starts to process the list. 0: the periodic list processing is not carried out after next sof 1: the periodic list processing is carried out after next sof 1 0 cbsr1 cbsr0 0 0 r/w r/w control bulk service ratio this bit specifies the service ration of the control and bulk ed. the host controller must compare the ratio specified by the internal calculatio n whether it has processed several non-vacant control ed in determining whether another control ed is continued to be supplied or switched to bulk ed before any a periodic list is processed. in case of reset, hcd is responsible for restoring this value. 00: 1:1 01: 2:1 10: 3:1 11: 4:1 24.3.3 hc command status register (usbhcs) the host controller uses usbhcs no t only for reflecting the current status of the host controller, but also for receiving a command issued by hcd. a write is for setting hcd. the host controller must guarantee that the bit to which 1 is written to be set and the bit to which 0 is written to is unchanged. hcd must distribute multiple clear commands to the host controller by a previously issued command. the host controller dr iver can read all bits normally. the soc bit indicates the number of the frame that has detected the scheduling overrun error by the host controller. this occurs when the periodic list has not completed before eof. when the scheduling overrun error is detect ed, the host controller increments the counter and sets so bit in the usbhis register. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 772 of 1458 rej09b0033-0300 bit bit name initial value r/w description 31 to 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 16 soc1 soc0 0 0 r/w r/w scheduling overrun count these bits are increment ed in each schedulingoverrun error. these bits are initially set to b'00 and returned to b'11. these bits are incremented when schedulingoverrun is detected even though the so bit in usbhis is set. these bits are used by hcd to monitor any continuous scheduling problem. 15 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 ocr 0 r/w ownership change request this bit is set by os hcd to request the change of the control of the host controller. when this bit is set, the host controller sets the oc bit in usbhis. after a change, this bit is cleared and remains until the next request from os hcd. 0: after a change, this bit is cleared and remains until the next request from os hcd 1: set the oc bit in usbhis 2 blf 0 r/w bulk list filled this bit is used to indicate that there are some tds in the list. this bit is set by hcd to the list when td is added to ed. when the host controller starts to process the head of the list, it checks this bit. as long as this bit is 0, the host controller does not start to process the list. when this bit is 1, the host controller starts to process the list to set bf to 0. when the host controller detects td in the list, the host controller sets this bit to 1. when td is never found in the list and hcd does not set this bit, the host controller completes the processing of the list. this bit is still 0 when the size list processing is stopped. 0: the list is not processed 1: the list is processed section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 773 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 clf 0 r/w control list filled this bit is used to indicate that there are some tds in the control list. this bit is set by hcd when td is added to ed in the control list. when the host controller starts to process the head of the control list, it checks this bit. as long as this bit is 0, the host controller does not start to process the control list. if this bit is 1, the host controller starts to process the control list and this bit is set to 0. when the host controller finds td in the list, the host controller sets this bit to 1. when td is never detected in the control list and hcd does not set this bit, the host controller completes the processing of the control list. this bit is still 0 when the control list processing is stopped. 0: the list is not processed 1: the list is processed 0 hcr 0 r/w host controller reset this bit is set by hcd to initiate the software reset of the host controller. the system is moved to the usbsuspend state in which most of the operational registers are reset except for the next state regard less of the functional state of the host controller. for example, an access to the ir bit in the usbhc register and without host bus is allowed. the host controller upon completion of the reset operation clears this bit. this bit does not cause any reset to the route hub and the next reset signal is not issued to the downstream port. 0: cleared by the host controll er at the completion of the reset control 1: usbsuspend state section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 774 of 1458 rej09b0033-0300 24.3.4 hc interrupt stat us register (usbhis) this register indicates the status in various even ts that cause hardware in terrupts. when an event occurs, the host controller sets the corresponding bit in this register. when the bit is set to 1, a hardware interrupt is generated while an interrupt is enabled and the mie bit is set in usbhie (section 24.3.5, hc interrupt enable register (usbhie)). hcd clears a specified bit in this register by writing 1 in the bit position to be cleared. the host controller driver cannot set any bit of these bits. the host controller never clears bits. bit bit name initial value r/w description 31 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30 oc 0 r/w ownership change this bit is set by the host controller when the ocr bit in usbhcs is set. this event generates a system management interrupt (smi) at once when not masked. when there is no smi pin, this bit is set to 0. 0: the ocr bit in usbhcs is not set 1: the ocr bit in usbhcs is set 29 to 7 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 6 rhsc 0 r/w root hub status change this bit is set when the content of usbhrs or the content of any usbhrps 1, 2 register has changed. 0: the content of usbhrs or usbhrps is not changed 1: the content of usbhrs or usbhrps is changed 5 fno 0 r/w frame number overflow this bit is set when msb (bit 15) in usbhfn changes value from 0 to 1 or from 1 to 0 or the hcca frame number bit is updated. 0: msb or the hcca frame number bit in usbhfn is not updated 1: msb or the hcca frame number bit in usbhfn is updated section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 775 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 ue 0 r/w unrecoverable error this bit is set when the host controller detects a system error that is not related to usb. hcd clears this bit after the host controller is reset. 0: system error is not generated 1: system error is detected 3 rd 0 r/w resume detected this bit is set when the host controller detects that a device of usb issues a resume signal. this bit is not set when hcd sets usb resume state. 0: the resume signal is not detected 1: the resume signal is detected 2 sf 0 r/w start of frame this bit is set by the host controller when each frame starts and after the hcca fr ame number is updated. the host controller simultaneously generates the sof token. 0: each frame has not initiated or hcca frame number is not updated 1: initiation of each frame and updating of hcca frame number 1 wdh 0 r/w write-back done head this bit is set immediately after the host controller has written hc done head to hcca done head. hcca done head is not updated until this bit is cleared. hcd should clear this bit only after the content of hcca done head has been stored. 0: when cleared after set to 1 1: when hc done head is written to hcca done head 0 so 0 r/w scheduling overrun this bit is set when the usb schedule has overrun after hcca frame number has updated. schedulingoverrun also increments the soc bit in usbhcs. 0: the usb schedule has not overrun 1: the usb schedule has overrun section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 776 of 1458 rej09b0033-0300 24.3.5 hc interrupt enable register (usbhie) each enable bit in usbhie corresponds to the rela ted interrupt bit in usbhis. usbhie is used to control an event to generate a hardware interrupt. a hardware interrupt is requested to the cpu when a bit in usbhie is set, a corresponding bit in usbhie is set, and the mie bit is set. as a result, the usbhi bit in the interrupt request regist er 9 (irr9) of the interrupt controller (intc) is set (the usbhi bit is used in common regardless of the content of the interrupt generation event). therefore, the usbhi bit can be used when an interrupt generation is detected by hcd. writing 1 in this register sets the corresponding bi t, while writing 0 leaves the bit. when read, the current value of this register is returned. bit bit name initial value r/w description 31 mie 0 r/w master interrupt enable setting this bit to 0 is ignored by the host controller. when this bit is set to 1, an interrupt generation by the event specified in another bit in this register is enabled. this is used by hdc that the master interrupt is enabled. when an interrupt is detected by h cd, use the usbih bit of the interrupt controller (intc). 0: ignored 1: interrupt generation due to the specified event enabled 30 oc 0 r/w ownership change enable 0: ignored 1: interrupt generation due to ownership change enabled 29 to 7 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 6 rhsc 0 r/w root hub status change enable 0: ignored 1: interrupt generation due to root hub status change enabled 5 fno 0 r/w frame number overflow enable 0: ignored 1: interrupt generation due to frame number overflow enabled section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 777 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 ue 0 r/w unrecoverable error enable 0: ignored 1: interrupt generation due to unrecoverable error enabled 3 rd 0 r/w resume detected enable 0: ignored 1: interrupt generation due to resume detected enabled 2 sf 0 r/w start of frame enable 0: ignored 1: interrupt generation due to start of frame enabled 1 wdh 0 r/w write-back done head enable 0: ignored 1: interrupt generation due to writebackdonehead enabled 0 so 0 r/w scheduling overrun enable 0: ignored 1: interrupt generation due to scheduling overrun enabled 24.3.6 hc interrupt di sable register (usbhid) each disable bit in usbhid corresponds to th e related interrupt bit in usbhis. usbhid is related to usbhie. therefore, writing a 1 to a bit in this register clears the corresponding bit in usbhie, while writing a 0 to a bit leaves the corresponding bit in usbhie. when read, the current value of usbhie is returned. bit bit name initial value r/w description 31 mie 0 r/w master interrupt enable 0: ignored 1: interrupt generation due to the specified event disabled 30 oc 0 r/w ownership change enable 0: ignored 1: interrupt generation due to ownershipchange disabled section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 778 of 1458 rej09b0033-0300 bit bit name initial value r/w description 29 to 7 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 6 rhsc 0 r/w root hub status change enable 0: ignored 1: interrupt generation due to roothubstatuschange disabled 5 fno 0 r/w frame number overflow enable 0: ignored 1: interrupt generation due to framenumberoverflow disabled 4 ue 0 r/w unrecoverable error enable 0: ignored 1: interrupt generation due to unrecoverableerror disabled 3 rd 0 r/w resume detected enable 0: ignored 1: interrupt generation due to resumedetected disabled 2 sf 0 r/w start of frame enable (sf) 0: ignored 1: interrupt generation due to startofframe disabled 1 wdh 0 r/w write-back done head enable (wdh) 0: ignored 1: interrupt generation due to writebackdonehead disabled 0 so 0 r/w scheduling overrun enable (so) 0: ignored 1: interrupt generation due to schedulingoverrun disabled section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 779 of 1458 rej09b0033-0300 24.3.7 hcca register (usbhhcca) usbhhcca includes physical addresses of the host controller communication area. the host controller driver determines the alignment limita tion by writing 1 to all bits in usbhhcca and by reading the content of usbhhcca. alignment is evaluated by checking the number of 0 in the lower bits. the minimum alignment is 256 bytes. consequently, bits 0 to 7 must be always returned to 0 when they are read. this area is used to retain the control structure and interrupt table that are accessed by the host contro ller and host controller driver. bit bit name initial value r/w description 31 to 8 hcca23 to hcca0 all 0 r/w hcca physical addresses of the host controller communication area 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 24.3.8 hc period current ed register (usbhpced) usbhpced includes a physical address of current isochronous ed or interrupt ed. bit bit name initial value r/w description 31 to 4 pced27 to pced0 all 0 r pced physical address of current isochronous ed or interrupt ed 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 780 of 1458 rej09b0033-0300 24.3.9 hc control head ed register (usbhched) usbhched includes a physical address of first ed in the control list. bit bit name initial value r/w description 31 to 4 ched27 to ched0 all 0 r/w ched physical address of first ed in the control list 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 24.3.10 hc control current ed register (usbhcced) usbhcced register includes a physical addr ess of current ed in the control list. bit bit name initial value r/w description 31 to 4 cced27 to cced0 all 0 r/w cced physical address of current ed in the control list 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 24.3.11 hc bulk head ed register (usbhbhed) usbhbhed includes a physical addre ss of first ed in the bulk list. bit bit name initial value r/w description 31 to 4 bhed27 to bhed0 all 0 r/w bhed physical address of first ed in the bulk list 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 781 of 1458 rej09b0033-0300 24.3.12 hc bulk current ed register (usbhbced) usbhbced includes a physical addr ess of current ed in the bulk list. when the bulk list is supplied by the round robin method , endpoints are ordered to the li st according to these insertions. bit bit name initial value r/w description 31 to 4 bced27 to bced0 all 0 r/w bced physical address of current ed in the bulk list 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 24.3.13 hc done head ed register (usbhdhed) usbhdhed includes a physical addr ess of finally completed td added to done queue. the host controller driver needs not read this register so th at the content is written to hcca periodically in normal operation. bit bit name initial value r/w description 31 to 4 dh27 to dh0 all 0 r dh physical address of finally completed td added to done queue 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 24.3.14 hc fm interval register (usbhfi) usbhfi includes a 14-bit value indicating the bi t time interval of the frame (i.e., between two serial sofs) and a 15-bit value indicating the maximum packet size at a full speed that is transmitted and received by the host controller without causing scheduling overrun. the host controller driver adjusts the frame interval minut ely by writing a new value over the current value in each sof. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 782 of 1458 rej09b0033-0300 bit bit name initial value r/w description 31 fit 0 r/w frame interval toggle this bit is toggled by hcd whenever it loads a new value into frameinterval. 30 to 16 fsmps14 to fsmps0 all 0 r/w fs largest data packet this field specifies a value, which is loaded into the largest data packet counter at the beginning of each frame. the counter value expresses the largest data amount of the bit that can be transmitted and received in one transaction by the host controller at any given time without causing scheduling overrun. t he field value is calculated by hcd. 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fi13 fi12 fi11 fi10 fi9 fi8 fi7 fi6 fi5 fi4 fi3 fi2 fi1 fi0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w frame interval these bits specify the interval between two serial sofs with bit times. the nominal value is set to 11999. hcd must store the current value of this field before resetting the host controller. with this procedure, this bit is reset to its nominal value by the host controller by setting the hcr bit in usbhcs. hcd can select to restore the stored value at the completion of the reset sequence. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 783 of 1458 rej09b0033-0300 24.3.15 hc frame remaining register (usbhfr) usbhfr is a 14-bit down counter indicating th e bit time remaining in the current frame. bit bit name initial value r/w description 31 frt 0 r/w frame remaining toggle this bit is always loaded from the fit bit in hc fm interval when fr reaches 0. this bit is used by hcd for the synchronization between fi and fr. 30 to 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 to 0 fr13 to fr0 all 0 r/w frame remaining this counter is decremented at each bit time. when this counter reaches 0, this counter is reset by loading the value of the fi bit specified in usbhfi at the next bit time boundary. when the host controller transits to the usboperational state, it read the fi bit in usbhfi again and uses the updated value from the next sof. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 784 of 1458 rej09b0033-0300 24.3.16 hc fm number b register (usbhfn) usbhfn is a 16-bit counter. it in dicates the reference of timing between events occurring in the host controller and host controller driver. the host controller driver uses a 16-bit value specified in this register and generates a 32-bit frame numbe r without necessity for a frequent access to the register. bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 to 0 fn15 to fn0 all 0 r/w frame number these bits are incremented when usbhfn is reloaded. the count will return to h'0 after h'ffff. when the host controller transits to the usbo perational state, these bits are automatically incremented. after the host controller increments the fn bit and sends sof in each frame boundary, the content is writ ten to hcca before the host controller reads first ed in the frame. after writing to hcca, the host controller sets the sf bit in usbhis. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 785 of 1458 rej09b0033-0300 24.3.17 hc periodic start register (usbhps) usbhps has a 14-bit programmable value, which determines the earliest time when the host controller should start to process the periodic list. bit bit name initial value r/w description 31 to 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 to 0 ps13 to ps0 all 0 r/w periodic start this field is cleared after the hardware has reset. then this field is set by hcd while the host controller performs initial settings. the value is roughly calculated as the value of the usbhfi minus 10%. when usbhfr reaches the specified value, the processi ng of the periodic list has a higher priority than the control/bulk processing. consequently, the host controller starts to process the interrupt list after the completi on of the current control/bulk transaction. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 786 of 1458 rej09b0033-0300 24.3.18 hc ls threshold register (usbhlst) usbhlst includes an 11-bit value that is used by the host controller to determine whether or not to authorize the transfer of the ls packed 8 bytes in maximum before eof. the host controller and host controller driver cannot change this value. bit bit name initial value r/w description 31 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 10 9 8 7 6 5 4 3 2 1 0 lst11 lst10 lst9 lst8 lst7 lst6 lst5 lst4 lst3 lst2 lst1 lst0 0 1 1 0 0 0 1 0 1 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ls threshold this field contains a value to be compared with the fr bit prior to the beginning of low-speed transaction. the transaction is started only when the fr bit value is beyond the value of the list. the value is calculated by hcd considering the transmission and set-up overhead. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 787 of 1458 rej09b0033-0300 24.3.19 hc rh descriptor a register (usbhrda) usbhrda is the first register of two registers describing the features of the root hub. the reset value is implementation specific. the descriptor le ngth (11), descriptor type (tbd), and the hub controller current bit (0) of class descriptor of the hub are emulated by hcd. all other bits are placed in usbhrda and usbhrdb. bit bit name initial value r/w description 31 30 29 28 27 26 25 24 potpgt7 potpgt6 potpgt5 potpgt4 potpgt3 potpgt2 potpgt1 potpgt0 0 0 0 0 0 0 1 0 r/w r/w r/w r/w r/w r/w r/w r/w power on to powe r good time these bits specify the time required for waiting before accessing the power-on port of the root hub. these bits are implementation specific. t he unit of time is 2 ms. the time is calculated as potpgt 2 ms. 23 to 13 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 12 nocp 1 r/w no over current protection this bit selects how the over-c urrent status of the root hub is reported. when this bit is cleared, the ocpm bit specifies global report or report at each port. 0: over-current status is collectively reported for all downstream ports 1: over-current protection is not supported 11 ocpm 0 r/w over current protection mode this bit selects how the over-cu rrent status in the root-hub port is reported. at reset, this bit reflects the same mode of powerswitchingmode. when the nocp bit is cleared, this bit is valid. 0: over-current status is collectively reported for all downstream ports 1: over-current protection is not supported 10 dt 0 r device type this bit indicates that the usb host controller is not a compound device. always set this bit to 0. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 788 of 1458 rej09b0033-0300 bit bit name initial value r/w description 9 nps 1 r/w no power switching this bit selects whether the power switching is supported or ports are always power-supplied. this bit is implementation specific. when this bit is cleared, the psm bit specifies the global/port switching. 0: ports can be power-switched 1: ports are always powered on when the host controller is powered on note: since the initial value is 1, first clear this bit (write 0 with the hcd) to enable power switching of the port. 8 psm 0 r/w power switching mode this bit specifies how the power switching of the root-hub port is controlled. this bit is implementation specific. this bit is valid only when the nps bit is cleared. 0: all ports are simultaneously power-supplied 1: each port is power-supplied individually. in this mode, the port power is controlled with either of global/port switching. when the ppcm bit in usbhrdb is set, the port is reacted only to the port-power command (set/clear port power). when the port mask is cleared, the port is controlled only by the global power-switch (set/clear global power). 7 6 5 4 3 2 1 0 ndp7 ndp6 ndp5 ndp4 ndp3 ndp2 ndp1 ndp0 0 0 0 0 0 0 1 0 r number down stream ports these bits specify the number of downstream ports supported by the root hub. t hese bits are implementation specific. in this lsi, their value is h'2. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 789 of 1458 rej09b0033-0300 24.3.20 hc rh descriptor b register (usbhrdb) usbhrdb is the second register of two registers describing the features of the root hub. these bits are written during the initial setting so as to correspond to the system implementation. the reset value is implementation specific. bit bit name initial value r/w description 31 to 16 ppcm15 to ppcm0 all 0 r/w port power control mask this bit indicates that the port is influenced by the global power-control command when the psm bit in the usbhrda register is set. when this bit is set, the power state of the port is affected by the power control at each port (set/clear port power). when this bit is cleared, the port is controlled by the global power switch (set/clear global power). if the device is placed in the global switching mode (psm = 0), this bit is not valid. bit 31: port#15 power mask : bit 18: port#2 power mask bit 17: port#1 power mask bit 16: reserved note: clear the nps of the usbhrda register so that the power to all ports is off (port power status = 0), then set this bit. 15 to 0 dr15 to dr0 all 0 r/w device removable these bits are dedicated to the ports of the root hub. when these bits are cleared, the set device becomes removable. when these bits are set, do not remove the set device. bit 15: device affixed to port#15 : bit 2: device affixed to port#2 bit 1: device affixed to port#1 bit 0: reserved section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 790 of 1458 rej09b0033-0300 24.3.21 hc rh status register (usbhrs) usbhrs is divided into two parts. the lower word of a long word indicates the hub status bits and the upper word indicates the hub status change bit. reserved bits should be set to 0. bit bit name initial value r/w description 31 crwe 0 w clear remote wakeup enable writing a 1 to this bit clea rs deviceremote wakeupenable. writing 0 to this bit has no effect. 30 to 18 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 17 ocic 0 r/w over current indicator change this bit is set when the oci bit changes. writing 1 clears this bit. writing 0 has no effect. (read) local power status change the root hub does not suppor t the local power status function. therefore, this bit is always read as 0. 16 lpsc 0 r/w (write) set global power this bit is written to 1 to power on (clears the pps bit in usbhrps) all ports in global power mode (psm bit in usbhrda = 0). this bit sets the pps bit only to the port in which the ppcm bit is not set in power mode at each port. when a 0 is written to, this bit is not cleared. (read) device remote wakeup enable this bit enables the csc bit as a resume event and generates the state transit ion from usbhsuspend1 to usbresume and resumedetected interrupt. 0: connectstatuschange is not the remote wakeup event 1: connectstatuschange is the remote wakeup event. 15 drwe 0 r/w (write) set remote wakeup enable writing a 1 sets deviceremotewakeupenable. writing a 0 has no effect. 14 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 791 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 oci 0 r over current indicator this bit reports the over-current condition. when this bit is set, an over-current condition exists. when this bit is cleared, all power operations are normal. this bit is always 0 when the over-current prot ection at each port is carried out. 0: all power operations are normal 1: an over-current condition exists (read) local power status the root hub does not suppor t the local power status function. therefore, the bit is always read 0. 0 lps 0 r/w (write) clear global power this bit is written to 1 to power on (the pps bit in usbhrps is cleared) all ports in global power mode (psm in usbhrda = 0). in the power mode at each port, the pps bit is cleared to the port in which the ppcm bit is not set. writing a 0 has no effect. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 792 of 1458 rej09b0033-0300 24.3.22 hc rh port status 1 and hc rh port status 2 registers (usbhrps1, usbhrps2) usbhrps 1 and usbhrps 2 registers are used for base-controlling each port and to report the port event. the lower word is used to reflect the port status while the upper word reflects the status change. some status bits have special writing (see below). if an attempt to write to a bit indicating a change in port status occurs when a transaction in which a token is passed via a handshake is in progress, the writing to the bit is delayed until th e transaction is completed. always write reserved bits to 0. bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 prsc 0 r/w port reset status change this bit is set when the 10 ms port reset signal has completed. writing a 1 clears this bit; writing a 0 has no effect. 0: port reset is not complete 1: port reset is complete 19 ocic 0 r/w port over current indicator change this bit is valid when an over-current condition is reported on the base of each port. this bit is set when the root hub changes the poci bit. writing a 1 clears this bit. writing a 0 has no effect. 0: portovercurrentindicator not changed 1: portovercurrentindicator changed 18 pssc 0 r/w port sus pend status change this bit is set when all resume sequences have completed. these sequences include 20 ms resume pulse, ls eop, and 3 ms resychronization delay. writing a 1 clears this bit. writing a 0 has no effect. this bit is cleared also when the prsc bit is set. 0: port resume not completed 1: port resume completed section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 793 of 1458 rej09b0033-0300 bit bit name initial value r/w description 17 pesc 0 r/w port enable status change this bit is set when the pes bit is cleared due to a hardware event. this bit is not set by the change of writing of hcd. writing a 1 clears this bit. writing a 0 has no effect. 0: portenablestatus not changed 1: portenablestatus changed 16 csc 0 r/w connect status change this bit is set whenever the connection or disconnection event occurs. writing a 1 clears this bit. writing a 0 has no effect. if the ccs bit is cleared when setportreset, setportenable, or setportsuspend is written to, writing when the power supply of the port is disconnected does not occur, so this bit is set to enforce the driver to re- evaluate the connection status. 0: currentconnectionstatus not changed 1: currentconnectionstatus changed note: if the dr bit in usbhrdb is set, this bit is set only after the root hub reset to inform that the system that a device can be attached. 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 794 of 1458 rej09b0033-0300 bit bit name initial value r/w description (read) low speed device attached this bit indicates the speed of the device attached to this port. when this bit is set, a low-seed device is attached to this port. when this bit is cleared, a full-speed device is attached to this port. this bit is valid only when the ccs bit is set. 0: a full-speed device is set 1: a low-speed device is set 9 lsda 0 r/w (write) clear port power writing a 1 clears the pps bit. writing a 0 has no effect. (read) port power status this bit reflects the power state of the port regardless of the power-switching mode to be executed. however, because the initial value of the nps bit of the usbhrda is 1, this bit is first fixed to 1. the nps bit must first be cleared before the power is switched, as shown below. when an over-current condition is detected, this bit is cleared. writing setportpower or setglovalpower sets this bit. writing clearportpower or clearglobalpower clears this bit. the psm bit in usbhrda and the ppcm bit in usbhrdb determine which power control switch can be used. only set/clearglobalpower controls this bit in global switching mode (psm= 0). if the ppcm bit of that port is set in power switching mode (psm = 1), only the set/clearportpower command is enabled. if the mask is not set, the set/clearglovalpowercommand is enabled. when the port power is disa bled, the ccs, pes, pss, and prs are reset. 0: port power is off 1: port power is on note: if power switching is not supported, this bit is always read as 1. 8 pps 1 r/w (write) set port power writing a 1 sets the pps bit. writing a 0 has no effect. 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 795 of 1458 rej09b0033-0300 bit bit name initial value r/w description (read) port reset status when this bit is set by writing to setportreset, the port reset signal is output. this bit is cleared when prsc is set upon completion of a reset. when the ccs is cleared, this bit is not set. 0: port reset signal is not active 1: port reset signal is active 4 prs 0 r/w (write) set port reset writing a 1 sets portreset signal. writing a 0 has no effect. when the ccs bit is cleared, this write does not set the prs bit, instead, sets the csc bit. this reports a reset of the power disconnection port to the driver. (read) port over current indicator this bit is valid only when a root hub is placed in such a way that an over-current cond ition is reported on the base of each port. if the over-current report at each port is not supported, this bit is cleared to 0. if this bit is cleared, all power controls are normal in this port. if this bit is set, an over-current status exists in this port. this bit always reflects an over-current input signal. 0: no over-current condition 1: over-current condition is detected 3 poci 0 r/w (write) clear suspend status writing a 1 initiates a resume. writing a 0 has no effect. if the pss bit is set, a resume is initiated. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 796 of 1458 rej09b0033-0300 bit bit name initial value r/w description (read) port suspend status this bit indicates that the port is suspended or during the resume sequence. writing setsuspendstate sets this bit and setting pssc clears this bit at the end of the resume interval. if the ccs bit is cleared, this bit cannot be set. when the prsc bit is set upon completion of the port reset or hc is placed in the usbresume state, this bit is cleared. if an upstream resume is in progress, it is transmitted to the host controller. 0: port is not suspended 1: port is selectively suspended 2 pss 0 r/w (write) set port suspend writing a 1 sets portsuspendstatus. writing a 0 has no effect. in addition, when the ccs bit is cleared, the pss bit is not set by this writing. instead, the csc bit is set. this reports the suspended state of the power disconnection to the driver. (read) port enable status this bit indicates whether the port is enabled or disabled. the root hub clears this bit when the over-current condition and an operational bus error such as disconnect event, power-off switch, or babble is detected. the pesc is set by this change. this bit is set by writing setportenable and cleared by writing clearportenable. this bit cannot be set when the ccs bit is cleared. in addition, this bit is set upon completion of the port reset by which the prsctatuschange is set, or uponcompletion of the port suspend by which the pssc is set. 0: port disabled 1: port enabled 1 pes 0 r/w (write) set port enable writing a 1 sets the pes bit. writing a 0 has no effect. if the ccs bit is cleared, this writing does not set the pes bit, instead, sets the cs. this reports the driver that the power disconnection port has been tried to be enabled. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 797 of 1458 rej09b0033-0300 bit bit name initial value r/w description (read) current connect status this bit indicates the status of the downstream port. 0: no device connected 1: device connected note: if deviceremoveable is se t (not removable) this bit is always read as 1. 0 ccs 0 r/w (write) clear port enable writing a 1 clears the pes bit. writing a 0 has no effect. the ccs bit is not affected by any writing. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 798 of 1458 rej09b0033-0300 24.4 data storage format which re quired by usb host controller 24.4.1 storage format of the transferred data usb host controller expects that data is compiled from lower address to upper address regardless endian setting of the cpu. below figure shows data read operation, which is done by usb host controller. program memory (area 3) usb host data.l h'11223344 data.l h'55667788 data.l h'00000099 lw read h'11223344 lw read h'55667788 lw read h'00000099 +3 11 +7 55 +11 00 +2 22 +6 66 +10 00 +1 33 +5 77 +9 00 +0 44 +4 88 8 99 the correspondence between data in memory and data read by usb host controller must be equal. when usb host controller reads data from external memory, usb host controller reads data by long word read operation every time regardless of endian. usb host controller uses data in byte from lower address in long word which it reads regardless the endian mode. even endian mode is set as big or little, set th e data from down addresses. below program flow is the example of failure. ? in program, set transfer address a to register r0 at big endian in program, "mov.b #h'12,@r0" ? in program, set transfer start address a to usb host controller, and set 1byte as transfer size. memory data expected to be transferred actually transferred data lw read h'12000000 +3 12 +2 00 +1 00 +0 00 this example shows abov e operation transfers ex pected data #h'12. data is filled from the lower bits of the memory in writing so that the data is read/written in bi- direction consistently regardless of the endian type. that is, the data is always aligned with the little endian specification. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 799 of 1458 rej09b0033-0300 24.4.2 storage format of the descriptor ed (endpoint descriptor) and td (transfer descriptor) that define each transfer transaction of usb host controller must be aligned so that each dword corresponds to the long-word boundary (addresses 4n to 4n + 3) of the memory. 24.5 data alignment restriction of usb host controller 24.5.1 restriction on the line boundary of the synchronous dram the transferred data is stored in shared system memory with cpu. the data alignment in system memory are restricted depends on sdram speci fication which is used as system memory. n n+1 n+2 dram row address memory area row address row address (1) (2) (3) in above figure, transfer data 1 and 3 are able to be read or written by usb host controller. but transfer data 2 are possibly unable to be read or written by usb host controller. any data, which have possibility to be accessed by usb host contro ller, must be aligned in sdram not to cross row address alignment. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 800 of 1458 rej09b0033-0300 24.5.2 restriction on the memory access address mps in ed, cbp in general td, and bp0 and offset0 to 7 in ischoronous td must be set in multiples of 4 (4n). in the openhci standard, 1 packet is transferred by itd in general td and 1 packet by 1 offset in ischronous td during in transfer. in addition, when the amount of the data specified by td during out tr ansfer exceeds maxpacketsize (m ps), a packet transmission is carried out in maxpacketsize. therefore, the setting value can be made as above. this restriction is due to the difference between the specifications of the hci interface which is the standard of the ip bus interface of usb and of the bus interface of this lsi. data might be correctly written to if data is transferred from ad dresses other than 4n address. for example, when a two-byte transfer is carried out from the address that terminates at 1, a lo ng-word transfer is carried out and an unexpected data is written to starting address 0. 24.6 accessing external address from the usb host accessing the external address from th e usb host is carried out as follows: ? when reading, 4, 8, 12, or 16-byte transfer in longword units. ? when writing, 1 to 16-byte transfer. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 801 of 1458 rej09b0033-0300 24.7 usage notes 1. when using the usb host controller, the bus clock (b ) must be set to 32 mhz or higher. the peripheral clock (p ) must also be set to a higher frequency than 13 mhz. 2. usage notes on resume operation (1) phenomenon while the usb host is providing an output of a resume (*1) signal, suppose that (a) portpower is turned off or that (b) overcurrent is produced. in this ca se, the resume signal should ordinarily be stopped so that the idle (*2) state will be established. actually, however, the result is that an idle signal is output. *1: in fullspeed, d+ = low and d- = high. in lowspeed, d+ = high and d- = low. *2: in fullspeed, d+ = high and d- = low. in lowspeed, d+ = low and d- = high. (2) conditions when the above phenomenon occurs while a resume (*1) signal is being output, (a ) portpower is turned off or (b) overcurrent is produced. (3) conditions when the above phenomenon does not occur the above phenomenon will not occur if there is no resume operation, that is, suspend operation has not been done. (4) problem avoidance by software if the above phenomenon occurs, resume is interrupted and then an idle signal is output. however, turning on portpower enables device recognition. the above phenomenon is removed by the subsequent port reset for the device. normal operation is thus recovered. note, however, the above phenomenon will not be removed by usb reset, which is generated by the hcfs1 and hcfs0 bits in the hc control (usbhc) register. for this reason, if you are usin g software that issues usb reset by the hcfs1 and hcfs0 bits in the hc control (usbhc) register, modify the software so that it issues usb reset (port reset) by setting the prs bit in the hc rh port status 1 or hc rh port status 2 (usbhrps1 or usbhrps2) register. however, there is no need to take corrective action if port rest has already been issued by the prs bit before the recognition of usb device connection. section 24 usb host controller (usbh) rev. 3.00 jan. 18, 2008 page 802 of 1458 rej09b0033-0300 section 25 usb function controller (usbf) ifusb00b_000020020700 rev. 3.00 jan. 18, 2008 page 803 of 1458 rej09b0033-0300 section 25 usb function controller (usbf) this lsi incorporates an us b function controller (usbf). 25.1 features ? udc (usb device controller) conforming to usb1.1 processes incorporated usb protocol automatically. automatic processing of usb standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) ? transfer speed : full-speed ? endpoint configuration: an arbitrary endpoint configuration can be set the arbitrary endpoint can be configured by setting the correspondence between the endpoint (the endpoint number used by the usb host) and the ep fifo number that is provided by this usb function controller (the transfer method and direction are fixed). ep fifo number abbreviation transfer type maximum packet size fifo buffer capacity (byte) dma transfer ep0s setup 8 8 ? ep0i control-in 8 8 ? endpoint 0 ep0o control-out 8 8 ? endpoint 1 ep1 bulk-out 64 128 possible endpoint 2 ep2 bulk-in 64 128 possible endpoint 3 ep3 interrupt 8 8 ? endpoint 4 ep4 isochronous-out 64 128 ? endpoint 5 ep5 isochronous-in 64 128 ? ? interrupt requests: generates various interrupt signals necessary for usb transmission/reception ? clock: external input (48 mhz) section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 804 of 1458 rej09b0033-0300 ? power-down mode power consumption can be reduced by stopping udc internal clock when usb cable is disconnected automatic transition to/rec overy from suspend state ? can be connected to a philips pdiusbp11 series transceiver or compatible product (when using a compatible product, carry out evaluation and investigation with the manufacturer supplying the transceiver beforehand) figure 25.1 shows the block diagram of usbf. peripheral bus interrupt requests dma transfer requests status and control registers fifo udc transceiver usb function controller usb1_p usb1_m clock (48 mhz) udc: usb device controller [legend] figure 25.1 block diagram of usbf section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 805 of 1458 rej09b0033-0300 25.2 input/output pins table 25.1 lists the pin configuration of usbf. table 25.1 pin configuration and functions name pin name i/o function rcv pin usb1d_rcv input input pin for receive data from differential receiver dpls pin usb1d_dpls input input pin to driver for d+ signal from receiver dmns pin usb1d_dmns input input pin to driver for d? signal from receiver txdpls pin usb1d_txdpls output d+ transmit output pin to driver txse0 pin usb1d_txse0 output se0 output pin txenl pin usb1d_txenl output driver output enable pin usb1 overcurrent/monitor pin usb1_ovr_current / usbf_vbus input usb port 1 over-current detection/ usb cable connection monitor pin suspend pin usb1d_suspnd output tr ansceiver suspend state output pin usb external clock extal_usb input connect a crystal resonator for usb. alternatively, an external clock may be input for usb (48 mhz). usb crystal xtal_usb output connect a crystal resonator for usb. usb1 power enable/pull-up control pin usb1_pwr_en/usbf_uplup output usb port 1 power enable control/ pull-up control output pin 1p pin usb1_p i/o d + 1m pin usb1_m i/o d ? section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 806 of 1458 rej09b0033-0300 25.3 register descriptions usb has following registers. refer to section 37, list of registers, for more details on the addresses and states of these registers in each operating mode. ? interrupt flag register 0 (ifr0) ? interrupt flag register 1 (ifr1) ? interrupt flag register 2 (ifr2) ? interrupt flag register 3 (ifr3) ? interrupt flag register 4 (ifr4) ? interrupt select register 0 (isr0) ? interrupt select register 1 (isr1) ? interrupt select register 2 (isr2) ? interrupt select register 3 (isr3) ? interrupt select register 4 (isr4) ? interrupt enable register 0 (ier0) ? interrupt enable register 1 (ier1) ? interrupt enable register 2 (ier2) ? interrupt enable register 3 (ier3) ? interrupt enable register 4 (ier4) ? ep0i data register (epdr0i) ? ep0o data register (epdr0o) ? ep0s data register (epdr0s) ? ep1 data register (epdr1) ? ep2 data register (epdr2) ? ep3 data register (epdr3) ? ep4 data register (epdr4) ? ep5 data register (epdr5) ? ep0o receive data size register (epsz0o) ? ep1 receive data si ze register (epsz1) ? ep4 receive data si ze register (epsz4) ? trigger register (trg) ? data status register (dasts) ? fifo clear register 0 (fclr0) ? fifo clear register 1 (fclr1) section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 807 of 1458 rej09b0033-0300 ? dma transfer setting register (dma) ? endpoint stall register 0 (epstl0) ? endpoint stall register 1 (epstl1) ? configuration value register (cvr) ? time stamp register h (tsrh) ? time stamp register l (tsrl) ? control register 0 (ctlr0) ? control register 1 (ctlr1) ? endpoint information register (epir) ? timer register h (tmrh) ? timer register l (tmrl) ? set time out register h (stoh) ? set time out register l (stol) section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 808 of 1458 rej09b0033-0300 25.3.1 interrupt flag register 0 (ifr0) ifr0 is an interrupt flag register for ep0i, ep0o, ep1, ep2, bus reset, and setup command reception. when each flag is set to 1 and the interrupt is enabled in the corresponding bit of ier0, an interrupt request is generated as specified by the corresponding bit in isr0. clearing is performed by writing 0 to the bit to be cleared. writing 1 is not valid and nothing is changed. ep2 empty and ep1 full are status bits that indicate the fifo stat es of ep1 and ep2, respectively. therefore, ep2 empt y and ep1 full cannot be cleared. bit bit name initial value r/w description 7 brst 0 r/w bus reset [setting condition] when a bus reset signal is detected on the usb bus. [clearing conditions] ? when reset ? when 0 is written to by cpu 6 ep1 full 0 r ep1 (bulk-out) fifo full [setting condition] the fifo buffer of ep1 has a dual-buffer configuration, and this bit is set when at least one of the fifo buffer is full. [setting conditions] ? when reset ? when both fifo buffers are empty. note: ep1 full is a status bit, and cannot be cleared. 5 ep2 tr 0 r/w ep2 (bulk-in) transfer request [setting condition] when an in token is received from the host to ep2 and both of fifo buffers are empty. [clearing conditions] ? when reset ? when 0 is written to by cpu section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 809 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 ep2 empty 1 r ep2 (bulk-in) fifo empty [setting conditions] ? when reset ? the fifo buffer of ep2 has a dual-buffer configuration, and this bit is set when at least one of the fifo buffer is empty. [clearing condition] when both of fifo buffers are not empty. note: ep2 empty is a status bit, and cannot be cleared. 3 setup ts 0 r/w setup command receive complete [setting condition] when 8-byte data that decodes the command by the function is normally received from the host to ep0s and an ack handshake is returned to the host from the function. [clearing conditions] ? when reset ? when 0 is written to by cpu 2 ep0o ts 0 r/w ep0o receive complete [setting condition] when data is normally received from the host to ep0o and an ack handshake is returned from the function to the host. [clearing conditions] ? when reset ? when 0 is written to by cpu 1 ep0i tr 0 r/w ep0i transfer request [setting condition] when in token is issued from the host to ep0i and the fifo buffer is empty. [clearing conditions] ? when reset ? when 0 is written to by cpu section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 810 of 1458 rej09b0033-0300 bit bit name initial value r/w description 0 ep0i ts 0 r/w ep0i transmit complete [setting condition] when data to be transmitted to the host is written to ep0i, then data is normally transferred from the function to the host, and an ack handshake is returned. [clearing conditions] ? when reset ? when 0 is written to by cpu 25.3.2 interrupt flag register 1 (ifr1) ifr1 is an interrupt flag register for vbus and ep 3. when each flag is set to 1 and the interrupt is enabled in the corresponding bit of ier1, an inte rrupt request is generated as specified by the corresponding bit in isr1. clearing is performed by writing 0 to the bit to be cleared. writing 1 is not valid and nothing is changed. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 vbus mn 0 r usb connection status status bit to monitor the usbf_vbus pin state. reflects the state of the usbf_vbus pin. 0: disconnected 1: connected 2 ep3 tr 0 r/w ep3 (interrupt) transfer request [setting condition] when an in token is issued from the host to ep3 and the fifo buffer is empty. [clearing conditions] ? when reset ? when 0 is written to by cpu section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 811 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 ep3 ts 0 r/w ep3 (interrupt) transmit complete [setting condition] when data to be transmitted to the host is written to ep3, then data is normally transferred from the host to the function, and an ack handshake is returned. [clearing conditions] ? when reset ? when 0 is written to by cpu 0 vbusf 0 r/w usb disconnection detection the usbf_vbus pin of this module is used for detecting connection/disconnection. [setting condition] when the function is connected to the usb bus or disconnected from it. [clearing conditions] ? when reset ? when 0 is written to by cpu. 25.3.3 interrupt flag register 2 (ifr2) ifr2 is an interrupt flag register for surss, sursf, cfdn, sof, setc, and seti. when each flag is set to 1 and an interrupt is enabled in the corresponding bit of ier2, an interrupt occurs as specified by the corresponding bit in isr2. clearing is performed by writing 0 to the bit to be cleared. writing 1 is not valid and nothing is changed. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 surss 0 r suspend/resume status status bit indicating the state of the bus 0: normal state 1: suspend state section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 812 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 sursf 0 r/w suspend/resume detection [setting condition] when the bus transits from the normal state to the suspend state or from the suspend state to the normal state. [clearing conditions] ? when reset ? when 0 is written to by cpu 3 cfdn 0 r/w end point information load complete [setting condition] when the end point information written in epir is completed to be set (loaded) in this controller. note: this controller operates normally as usb after the setting of the end point information is completed. [clearing conditions] ? when reset ? when 0 is written to by cpu 2 sof 0 r/w sof packet [setting condition] when the valid sof packet is detected. [clearing conditions] ? when reset ? when 0 is written to by cpu 1 setc 0 r/w set configuration command detection [setting condition] when the valid set configuration command is detected. [clearing conditions] ? when reset ? when 0 is written to by cpu section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 813 of 1458 rej09b0033-0300 bit bit name initial value r/w description 0 seti 0 r/w set interface command detection [setting condition] when the valid set interface command is detected. [clearing conditions] ? when reset ? when 0 is written to by cpu 25.3.4 interrupt flag register 3 (ifr3) ifr1 is an interrupt flag register for ep4 ts, ep4 tf, ep5 ts, and ep5 tr. when each flag is set to 1 and the interrupt is enabled in the corresponding bit of ier3, an interrupt request is generated as specified by the corresponding bit in isr3. clearing is performed by writing 0 to the bit to be cleared. writing 1 is not valid and nothing is changed. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 ep5 tr 0 r/w ep5 (isochronous-in) transmit request flag indicating the fifo state of ep5. after the sof packet is received, the fifo buffer is switched automatically. t he fifo buffer which has transmitted data to the host in the previous frame (before sof reception) can be written to by the cpu. this bit indicates the transmit state in the previous frame. [setting condition] the fifo buffer to be transmitted is empty when an in token is issued from the host to ep5. [clearing conditions] ? when reset ? when 0 is written to by cpu section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 814 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 ep5 ts 0 r/w ep5 (isochronous-in) normal transmission flag indicating the fifo state of ep5. after the sof packet is received, the fifo buffer is switched automatically. t he fifo buffer which has transmitted data to the host in the previous frame (before sof reception) can be written to by the cpu. this bit indicates the transmit state in the previous frame. [setting condition] when a transmission was carried out normally in the previous frame. [clearing conditions] ? when reset ? when 0 is written to by cpu 1 ep4 tf 0 r/w ep4 (isochronous-out) abnormal reception flag indicating the fifo st ate of ep4. indicates the state of the fifo buffer t hat was readable after the data reception is completed and the next sof packet is received. [setting condition] when the transfer data from the host is abnormally received (packet error) by ep4. [clearing conditions] ? when reset ? when 0 is written to by cpu 0 ep4 ts 0 r/w ep4 (isochronous-out) normal reception flag indicating the fifo st ate of ep4. indicates the state of the fifo buffer t hat was readable after the data reception is completed and the next sof packet is received. [setting condition] when the transfer data from the host is normally received by ep4. [clearing conditions] ? when reset ? when 0 is written to by cpu section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 815 of 1458 rej09b0033-0300 25.3.5 interrupt flag register 4 (ifr4) ifr4 is an interrupt flag register for tmout. wh en each flag is set to 1 and the interrupt is enabled in the corres ponding bit of ier4, an interrupt request is generated as specified by the corresponding bit in isr4. clearing is performed by writing 0 to the bit to be cleared. writing 1 is not valid and nothing is changed. bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 tmout 0 r/w time out [setting condition] when the value of the timer register (tmr) is reached to that of the set time out register (sto). [clearing conditions] ? when reset ? when 0 is written to by cpu section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 816 of 1458 rej09b0033-0300 25.3.6 interrupt sele ct register 0 (isr0) isr0 selects the interrupt requests to the intc to be indicated in interrupt flag register 0. when a bit in isr0 is cleared to 0, the corresponding inte rrupt is requested as a us bfi0 interrupt. when a bit is set to 1, the corresponding interrupt is requested as a usbfi1 interrupt. with the initial value, each of the interrupt source flags in the interrupt flag regi ster 0 is selected as a usbfi0 interrupt. bit bit name initial value r/w description 7 brst is 0 r/w brst interrupt select 6 ep1 full is 0 r/w ep1 full interrupt select 5 ep2 tr is 0 r/w ep2 tr interrupt select 4 ep2 empty is 0 r/w ep2 empty interrupt select 3 setup ts is 0 r/w setup interrupt select 2 ep0o ts is 0 r/w ep0o ts interrupt select 1 ep0i tr is 0 r/w ep0i tr interrupt select 0 ep0i ts is 0 r/w ep0i ts interrupt select 25.3.7 interrupt sele ct register 1 (isr1) isr1 selects the interrupt requests to the intc to be indicated in interrupt flag register 1. when a bit in isr1 is cleared to 0, the corresponding inte rrupt is requested as a us bfi0 interrupt. when a bit is set to 1, the corresponding interrupt is requested as a usbfi1 interrupt. with the initial value, each of the interrupt source flags in the interrupt flag regi ster 1 is selected as a usbfi0 interrupt. bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 ep3 tr is 1 r/w ep3 tr interrupt select 1 ep3 ts is 1 r/w ep3 ts interrupt select 0 vbusf is 1 r/w vbusf interrupt select section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 817 of 1458 rej09b0033-0300 25.3.8 interrupt sele ct register 2 (isr2) isr2 selects the interrupt requests to the intc to be indicated in interrupt flag register 2. when a bit in isr2 is cleared to 0, the corresponding inte rrupt is requested as a us bfi0 interrupt. when a bit is set to 1, the corresponding interrupt is requested as a usbfi1 interrupt. with the initial value, each of the interrupt source flags in the interrupt flag regi ster 2 is selected as a usbfi0 interrupt. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 surse is 1 r/w surse interrupt select 3 cfdn is 1 r/w cfdn interrupt select 2 sofe is 1 r/w sofe interrupt select 1 setce is 1 r/w setce interrupt select 0 setie is 1 r/w setie interrupt select 25.3.9 interrupt sele ct register 3 (isr3) isr3 selects the interrupt requests to the intc to be indicated in interrupt flag register 3. when a bit in isr3 is cleared to 0, the corresponding inte rrupt is requested as a us bfi0 interrupt. when a bit is set to 1, the corresponding interrupt is requested as a usbfi1 interrupt. with the initial value, each of the interrupt source flags in the interrupt flag regi ster 3 is selected as a usbfi0 interrupt. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 ep5 tr is 0 r/w ep5 tr interrupt select 2 ep5 ts is 0 r/w ep5 ts interrupt select 1 ep4 tf is 0 r/w ep4 tf interrupt select 0 ep4 ts is 0 r/w ep4 ts interrupt select section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 818 of 1458 rej09b0033-0300 25.3.10 interrupt select register 4 (isr4) isr4 selects the interrupt requests to the intc to be indicated in interrupt flag register 4. when a bit in isr4 is cleared to 0, the corresponding inte rrupt is requested as a us bfi0 interrupt. when a bit is set to 1, the corresponding interrupt is requested as a usbfi1 interrupt. with the initial value, each of the interrupt source flags in the interrupt flag regi ster 4 is selected as a usbfi0 interrupt. bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 tmout is 0 r/w tmout interrupt select 25.3.11 interrupt enab le register 0 (ier0) ier0 enables the interrupt requests of the interrupt fl ag register 0. when an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, the inte rrupt request set in the interrupt select register 0 is issued. when an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, the intn pin set in the interrupt select register 0 is asserted low and an interrupt request is issued. bit bit name initial value r/w description 7 brst ie 0 r/w brst interrupt enable 6 ep1 full ie 0 r/w ep1 full interrupt enable 5 ep2 tr ie 0 r/w ep2 tr interrupt enable 4 ep2 empty ie 0 r/w ep2 empty interrupt enable 3 setup ts ie 0 r/w setup ts interrupt enable 2 ep0o ts ie 0 r/w ep0o ts interrupt enable 1 ep0i tr ie 0 r/w ep0i tr interrupt enable 0 ep0i ts ie 0 r/w ep0i ts interrupt enable section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 819 of 1458 rej09b0033-0300 25.3.12 interrupt enab le register 1 (ier1) ier1 enables the interrupt requests of the interrupt fl ag register 1. when an interrupt flag is set to 1 while the corresponding bit of each interrupt is se t to 1, the interrupt requ est set in the interrupt select register 1 is issued. bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 ep3 tr ie 0 r/w ep3 tr interrupt enable 1 ep3 ts ie 0 r/w ep3 ts interrupt enable 0 vbusf ie 0 r/w vbusf interrupt enable 25.3.13 interrupt enab le register 2 (ier2) ier2 enables the interrupt requests of the interrupt fl ag register 2. when an interrupt flag is set to 1 while the corresponding bit of each interrupt is se t to 1, the interrupt requ est set in the interrupt select register 2 is issued. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 surse ie 0 r/w surse interrupt enable 3 cfdn ie 0 r/w cfdn interrupt enable 2 sofe ie 0 r/w sofe interrupt enable 1 setce ie 0 r/w setce interrupt enable 0 setie ie 0 r/w setie interrupt enable section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 820 of 1458 rej09b0033-0300 25.3.14 interrupt enab le register 3 (ier3) ier3 enables the interrupt requests of the interrupt fl ag register 3. when an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, the inte rrupt request set in the interrupt select register 3 is issued. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 ep5 tr ie 0 r/w ep5 tr interrupt enable 2 ep5 ts ie 0 r/w ep5 ts interrupt enable 1 ep4 tf ie 0 r/w ep4 tf interrupt enable 0 ep4 ts ie 0 r/w ep4 ts interrupt enable 25.3.15 interrupt enab le register 4 (ier4) ier4 enables the interrupt requests of the interrupt fl ag register 4. when an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, the inte rrupt request set in the interrupt select register 4 is issued. bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 tmout ie 0 r/w tmout interrupt enable section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 821 of 1458 rej09b0033-0300 25.3.16 ep0i data register (epdr0i) epdr0i is an 8-byte transmit fifo buffer for endpoint 0. epdr0i holds one packet of transmit data for control-in. transmit data is fixed by wr iting one packet of data and setting ep0ipkte in the trigger register. when an ack handshake is returned from the host after the data has been transmitted, ep0its in interrupt flag register 0 is set. this fifo buffer can be initialized by means of ep0iclr in the fclr0 register. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w data register for control-in transfer 25.3.17 ep0o data register (epdr0o) epdr0o is an 8-byte receive fi fo buffer for endpoint 0. epdr0o holds endpoint 0 receive data other than setup commands. when data is received no rmally, ep0ots in interr upt flag register 0 is set, and the number of receive bytes is indicated in the ep0o receive data size register. after the data has been read, setting ep0ordfn in the trigger register enables the next packet to be received. this fifo bu ffer can be initialized by means of bp0oclr in the fclr0 register. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined r data register for control-out transfer 25.3.18 ep0s data register (epdr0s) epdr0s is a data register specifically for endpoint 0 setup command. epdr0s holds 8-byte command data sent in the setup stage. however, only the command to be processed by a microprocessor (firmw are) is received. the command data to be processed automatically by this module is not stored. since the setup command mast be received, previous data in the buffer is over written with new data. in other words, when the reception of data in the setup stage starts during read, reception has priority and read data is invalid. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined r data regist er for storing the setup command at the control-out transfer note: the epdr0s register should be read in 8-byte units. if reading is stopped before it completes, data received in the subsequent setup stage is not read successfully. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 822 of 1458 rej09b0033-0300 25.3.19 ep1 data register (epdr1) epdr1 is a 128-byte receive fifo buffer for endpoint 1. epdr1 ha s a dual-buffer configuration, and has a capacity of twice the maximum packet si ze. the number of receive byte is displayed in the ep1 receive data size register. the buffer on read side can be received again by writing ep1rdfn in the trigger register to 1 after data is read. the receive data of this fifo buffer can be transferred by dma. this fifo buffer can be initialized by means of ep1clr in the fclr0 register. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined r data register for interrupt transfer 25.3.20 ep2 data register (epdr2) epdr2 is a 128-byte transmit fifo buffer for end point 2. epdr2 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. when transmit data is written to this fifo buffer and ep2pkte in the trigger register is set, one packet of transmit data is fixed, and the dual-fifo buffer is switched over. transmit data for this fifo buffer can be transferred by dma. this fifo buffer can be initialized by means of ep2clr in the fclr0 register. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w data register for endpoint 2 transfer 25.3.21 ep3 data register (epdr3) epdr3 is an 8-byte transmit fifo buffer for endpoint 3. epdr4 holds one packet of transmit data for the interrupt transfer of endpoint 3. transmit data is fixed by writing one packet of data and setting ep3pkte in the trigger register. when an ack handshake is returned from the host after the data has been transmitted, ep3ts in interrupt fl ag register 1 is set. this fifo buffer can be initialized by means of ep3clr in the fclr0 register. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w data register for endpoint 3 transfer section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 823 of 1458 rej09b0033-0300 25.3.22 ep4 data register (epdr4) epdr4 is a 128-byte receive fifo buffer for endpoint 4. epdr4 ha s a dual-buffer configuration, and has a capacity of twice the maximum packet si ze. the number of receive byte is displayed in the ep4 receive data size register. the receive da ta is fixed when an sof packet is received. accordingly, all receive data must be read until the next sof pack et is received. when the next sof packet is received, the fifo side is automati cally switched over, and the previous data will not be possible to be read. this fifo buffer can be initialized by means of ep4clr in the fclr1 register. bit bit name initial value r/w description 7 to 0 d7 to d0 undefined r data register for endpoint 4 transfer 25.3.23 ep5 data register (epdr5) epdr5 is a 128-byte transmit fifo buffer for end point 5. epdr5 has a dual-buffer configuration, and has a capacity of twice the maximum packet si ze. when transmit data is written to this fifo buffer and an sof packet is received, one packet of transmit data is fixed, and the dual-fifo buffer is switched over. this fi fo buffer can be initialized by means of ep5clr and ep5cclr in the fclr1 register. (ep5clr initializes both fifos and ep5cclr initializes one fifo which is connected to the cpu.) bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w data register for endpoint 5 transfer 25.3.24 ep0o receive data size register (epsz0o) epsz0o is a receive data size resister for end point 0o. epsz0o indicates the number of bytes received from the host. bit bit name initial value r/w description 7 to 0 ? all 0 r number of receive data for endpoint 0 section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 824 of 1458 rej09b0033-0300 25.3.25 ep1 receive data size register (epsz1) epsz1 is a receive data size resister for endpoint 1. epsz1 indicates the number of bytes received from the host. fifo of endpoint 1 has a dual-buff er configuration. the size of the received data indicated by this register is the size of the currently selected side (can be read by cpu). bit bit name initial value r/w description 7 to 0 ? all 0 r number of received bytes for endpoint 1 25.3.26 ep4 receive data size register (epsz4) epsz4 is a receive data size resister for endpoint 4. epsz4 indicates the number of bytes received from the host. fifo of endpoint 4 has a dual-buff er configuration. the size of the received data indicated by this register is the size of the currently selected side (can be read by cpu). bit bit name initial value r/w description 7 to 0 ? all 0 r number of received bytes for endpoint 4 25.3.27 trigger register (trg) trg generates one-shot triggers fifo for each endpoint of ep0s, ep0i, ep0o, ep1, ep2, and ep3. the packet enable trigger for the in fifo register and read complete trigger for the out fifo register are triggers to be given. bit bit name initial value r/w description 7 ? 0 w reserved the write value should always be 0. 6 ep3 pkte 0 w ep3 packet enable 5 ep1 rdfn 0 w ep1 read complete 4 ep2 pkte 0 w ep2 packet enable 3 ? 0 w reserved the write value should always be 0. 2 ep0s rdfn 0 w ep0s read complete 1 ep0o rdfn 0 w ep0o read complete 0 ep0i pkte 0 w ep0i packet enable section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 825 of 1458 rej09b0033-0300 25.3.28 data status register (dasts) dasts indicates whether the in fifo data register contains valid data. dasts is set to 1 when data written to in fifo is enabled by writing pkte in trg to 1, and cleared when all data has been transmitted to the host. in case of a dual-configuration fifo for endpoint 2, this bit is cleared to 0 when both sides are empty. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. 5 ep3 de 0 r ep3 data enable 4 ep2 de 0 r ep2 data enable 3 to 1 ? all 0 r reserved these bits are already read as 0. 0 ep0ide 0 r ep0i data enable 25.3.29 fifo clear register 0 (fclr0) fclr is a one shot register to clear the fifo buffers for endpoints 0 to 3. writing 1 to a bit clears the data in the corresponding fifo buffer. in case of reception fifo, by writing data in the fifo buffer, the data by which pkte in trg is not written to 1 and the data enabled by writing 1 can be cleared. in case of out fifo, the data of which reception has not been completed can be cleared. both sides of the dual-configuration fifo buffers (ep1 or ep3) can be cleared. the corresponding interrupt flag is not cleared by this clear instruc tion. do not clear a fifo buffer during transmission and reception. bit bit name initial value r/w description 7 ? ? w reserved the write value should always be 0. 6 ep3 clr ? w ep3 clear 5 ep1 clr ? w ep1 clear 4 ep2 clr ? w ep2 clear section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 826 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3, 2 ? ? w reserved the write value should always be 0. 1 ep0o clr ? w ep0o clear 0 ep0i clr ? w ep0i clear 25.3.30 fifo clear register 1 (fclr1) fclr is a one shot register to clear the fifo buffers for endpoints 4 and 5. writing 1 to a bit clears the data in the corresponding fifo buffer. the corresponding interrupt flag is not cleared by this clear instruct ion. do not clear a fifo buffer during transmission and reception. bit bit name initial value r/w description 7 to 5 ? ? w reserved the write value should always be 0. 4 ep5 cclr ? w ep5 cpu clear 3, 2 ? ? w reserved the write value should always be 0. 1 ep5 clr ? w ep5 clear 0 ep4 clr ? w ep4 clear 25.3.31 dma transfer setting register (dma) dma is set when the dual address transfer is used to the data register for endpoints 1 and 2 to which transfer is possible by dma. the usb1_pwr_en pin level can be controlled by the bit 2. bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 pullup e 0 r/w pull-up enable controls connection notif ication to usb host/hub. 0: usb1_pwr_en pin goes high 1: usb1_pwr_en pin goes low section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 827 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 ep2 dmae 0 r/w ep2dma enable enables dma transfer for ep2. 0 ep1 dmae 0 r/w ep1dmae enable enables dma transfer for ep1. 25.3.32 endpoint stall register 0 (epstl0) epstl stalls each endpoint. the endpoint in which th e stall bit is set to 1 returns a stall handshake to the host from the next transfer when 1 is written to. the stall bit for endpoint 0 is cleared automatically on reception of 8 byte command data for which decoding is performed by the function and the ep0 stl bit is cleared. when the se tupts flag bit in the ifr0 register is set to 1, a write of the ep0 stl bit to 1 is ignored. for detailed operation, see section 25.8, stall operations. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved this bit is always read as 0. the write value should always be 0. 3 ep3 stl 0 r/w ep3 stall sets ep3 stall 2 ep2 stl 0 r/w ep2 stall sets ep2 stall 1 ep1 stl 0 r/w ep1 stall sets ep1 stall 0 ep0 stl 0 r/w ep0 stall sets ep0 stall section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 828 of 1458 rej09b0033-0300 25.3.33 endpoint stall register 1 (epstl1) epstl stalls each endpoint. the endpoint in which th e stall bit is set to 1 returns a stall handshake to the host from the next transfer when 1 is written to. for detailed operation, see section 25.8, stall operations. bit bit name initial value r/w description 7 to 2 ? all 0 r reserved this bit is always read as 0. the write value should always be 0. 1 ep5 stl 0 r/w ep5 stall sets ep5 stall 0 ep4 stl 0 r/w ep4 stall sets ep4 stall 25.3.34 configuration value register (cvr) cvr is a register to store the configuration/interface/ va lue to be set when the set configuration/set interface co mmand is normally received. bit bit name initial value r/w description 7 6 cnfv1 cnfv0 0 0 r r configuration value the configuration setting valu e is stored when the set configuration command has been received. cnfv is updated when the setc bit in the interrupt flag register is set to 1. 5 4 intv1 intv0 0 0 r r interface value the interface setting value is stored when the set interface command has been received. intv is updated when the seti bit in the interrupt flag register is set to 1. 3 ? 0 r reserved this bit is always read as 0. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 829 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 1 0 altv2 altv1 altv0 0 0 0 r r r alternate value the alternate setting value is stored when the set interface command has been received. altv is updated when the seti bit in the interrupt flag register is set to 1. 25.3.35 time stamp register (tsrh/tsrl) tsr is a register to store the current time stamp value. the time stamp is updated when the sof bit in ifr0 is set to 1. the value of the time stamp when the sof mark function is enabled and the sof packet is broken remains as previous one. bit bit name initial value r/w description 15 to 11 ? all 0 r reserved. this bit is always read as 0. 10 9 8 7 6 5 4 3 2 1 0 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r time stamp data note: the time stamp register is used as a 16-bi t register which consists of upper byte tsrh and lower tsrl in usbf. tsrh can be read directly , but tsrl is read via an 8-bit temporary register. therefore, the regi sters should be accessed in the order, tsrh and tsrl, in byte units. tsrl cannot be read singly. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 830 of 1458 rej09b0033-0300 25.3.36 control register 0 (ctlr0) ctlr0 sets functions of asce, pwmd, rsme, and rwup. bit bit name initial value r/w description 7 to 5 c all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 rwups 0 r remote wakeup status status bit to indicate that the remote wakeup from the host is enabled/disabled. indicates 0 when the remote wakeup is disabled with device remote wakeup by the set feature/clear feature re quest and indicates 1 when it is enabled. 3 rsme 0 r/w resume enable bit to clear the suspend state (performs the remote wakeup) when this bit is written to 1, a resume register is set. when this bit will be used, be sure to hold to 1 for one clock or more at 12 mhz in minimum and then clear to 0 again. 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 1 asce 0 r/w automatic stall clear enable when this bit is set to 1, the stall handshake is returned to the host and the stall se tting bit (epstlr/epxstl) of the returned endpoint is autom atically cleared. control in a unit of endpoint is disabled as this bit is common for all endpoints. when this bit is set to 0, be sure to clear the stall setting bit of each endpoint by using software. this bit should be set to 1 before each stall bit in epstl is set to 1. 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 831 of 1458 rej09b0033-0300 25.3.37 control register 1 (ctlr1) ctlr1 makes settings of internal timer which is used in the isochronous transfer. bit bit name initial value r/w description 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 tmr aclr 1 r/w timer auto clear selects method to clear tmr (timer register). 0: not cleared. when clearing tmr, write 0 to tmr by cpu. 1: automatically cleared every time when sof is received. 0 tmr en 0 r/w timer enable tmr en is tmr (timer register) enable bit. 0: timer operation is disabled 1: timer operation is enabled 25.3.38 endpoint information register (epir) epir is a register to set the configuration information for each endpoint. 5 bytes of the information are required for one endpoint and the fo rmats are listed in tabl es 25.3 and 25.4. write the data in order from endpoint 0. do not write more than 5 (bytes) 10 (endpoints) = 50 bytes. write this information once at power-on reset. do not write it again afterwards. write data of one endpoint is described below. ep ir writes data in the same address in order. therefore though there is only one epir register, write data for registration number n (n is from 0 to 9) is listed as epirn0 to epirn4 (epir [registration number] [write order]) for the purpose of explaining. write data in order from epir00. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 832 of 1458 rej09b0033-0300 ? epirn0: bit bit name initial value r/w description 7 to 4 d7 to d4 undefined w endpoint number settable range: 0 to 5 3 2 d3 d2 undefined w configuration number to which endpoint belongs settable range: 0 or 1 1 0 d1 d0 undefined w interface number to which endpoint belongs settable range: 0 to 3 ? epirn1: bit bit name initial value r/w description 7 6 d7 d6 undefined w alternate number to which endpoint belongs settable range: 0 or 1 5 4 d5 d4 undefined w transfer method of endpoint settable range: 0: control 1: isochronous 2: bulk 3: interrupt 3 d3 undefined w transfer direction of endpoint settable range: 0: out 1: in 2 to 0 d2 to d0 undefined w reserved the write value should always be 0. ? epirn2: bit bit name initial value r/w description 7 to 1 d7 to d1 undefined w ma ximum packet size of endpoint settable range: 0 to 64 0 d0 undefined w reserved the write value should always be 0. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 833 of 1458 rej09b0033-0300 ? epirn3: bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w reserved the write value should always be 0. ? epirn4: bit bit name initial value r/w description 7 to 0 d7 to d0 undefined w endpoint fifo number settable range: 0 to 5 an endpoint number is an endpoint number used by the usb host. the endpoint fifo number corresponds to the endpoint nu mber which is described in th is manual. when each endpoint number and endpoint fifo number corresponds to each other, transfer can be performed between the usb host and the endpoint fifo. note that the setting values are limited as described below. ? since each endpoint fifo is optimized by a dedi cated hardware correspon ding to each transfer method, transfer direction, and maximum packet size, set the endpoint fifo with a transfer method, transfer direction, and maximum packet size shown in the table below. example: endpoint fifo number 1 cannot be set as other than bulk transfer, out, and maximum packet size (64 bytes). although endpoint fifo number 4 cannot be set as other than isochronous transfer and out, maximum packet size can be set in the range of 0 to 64 bytes. ? endpoint 0 and endpoint fifo number 0 must correspond. ? the maximum packet size of endpoint fifo number 0 can be set to 8 bytes only. ? the setting value of endpoint fifo number 0 can be set to the maximum packet size only and the rest data is all 0. ? the maximum packet size of endpoint fifo numbers 1 and 2 can be set to 64 only. ? the maximum packet size of endpoint fifo numbers 3 can be set to 8 only. ? the maximum packet size of endpoint fifo numbers 4 and 5 can be set in the range of 0 to 64. ? when the isochronous transfer is set, alternate can be used in the range of 0 and 1 for the same endpoint. be sure to allocate the altern ate to the same endpoint fifo number. ? endpoint information can be set up to 10 in maximum. ? endpoint information of 10 pieces must be written. ? all information of endpoints which are not used must be written as 0. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 834 of 1458 rej09b0033-0300 a list of restrictions of settable transfer method, transfer direction, and maximum packet size is described in table 25.2. table 25.2 restrictions of settable values endpoint fifo no. maximum packet size transfer method transfer direction 0 8 bytes control ? 1 64 bytes bulk out 2 64 bytes bulk in 3 8 bytes interrupt in 4 0 to 64 bytes isochronous out 5 0 to 64 bytes isochronous in ? example of setting this is an example when endpoint 4 and 5 used for the isochronous transf er are allocated with alternate value. table 25.3 example of endpoint configuration ep no. conf. int. alt. transfer method transfer direction maximum packet size ep fifo no. 0 ? ? ? control in/out 8 bytes 0 1 1 0 0 bulk out 64 bytes 1 2 1 0 0 bulk in 64 bytes 2 3 1 0 0 interrupt in 8 bytes 3 ? 1 1 0 ? ? ? ? ? 1 1 1 ? ? ? ? 4 1 2 0 isochronous out 0 bytes 4 4 1 2 1 isochronous out 64 bytes 4 5 1 3 0 isochronous in 0 bytes 5 5 1 3 1 isochronous in 64 bytes 5 section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 835 of 1458 rej09b0033-0300 table 25.4 example of setting of endpoint configuration information n epir[n]0 epir[n]1 epir[ n]2 epir[n]3 epir[n]4 0 00 00 10 00 00 1 14 20 80 00 01 2 24 28 80 00 02 3 34 38 10 00 03 4 00 00 00 00 00 5 00 00 00 00 00 6 46 10 00 00 04 7 46 50 80 00 04 8 67 18 00 00 05 9 57 58 80 00 05 config. - 1 int. - 0 1 2 3 alt. - 0 0 1 0 1 0 1 ep no. 0 1 2 3 4 4 5 5 ep fifo no. 0 1 2 3 4 5 attribute control bulkout bulkin interruptin isoout isoin figure 25.2 example of endpoint configuration section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 836 of 1458 rej09b0033-0300 25.3.39 timer register (tmrh/tmrl) tmrhwmrl is a 16-bit timer which is operated with a peripheral clock . measuring the sof packet reception interval enables th e sof packet break to be detected. the timer is operated, stopped, and cleared accord ing to the settings of the control register 1 (ctlr1). bit bit name initial value r/w description 15 to 0 d15 to d0 0 r/w count value note: the timer register is used as a 16-bit regi ster which consists of upper byte tmrh and lower tmrl in usbf. tmrh can be read directly, but tmrl is read via an 8-bit temporary register. therefore, the r egisters should be read in the order, tmrh and tmrl, in byte units. tmrl cannot be read singly. 25.3.40 set time out register (stoh/stol) stoh/stol specifies the time out value of the tim er register. when the co unt value of the timer register reaches the specified time out value, the time out interrupt flag in th e interrupt flag register 4 is set. bit bit name initial value r/w description 15 to 0 d15 to d0 0 r/w specified time out value note: the timer register is used as a 16-bit regi ster which consists of upper byte stoh and lower stol in usbf. stoh can be read directly, but stol is read via an 8-bit temporary register. therefore, the regi sters should be read in the order, stoh and stol, in byte units. tmrl cannot be read singly. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 837 of 1458 rej09b0033-0300 25.4 operation 25.4.1 cable connection no yes usb function application cable disconnected vbus pin = 0 v udc core reset usb cable connection usb1_pwr_en = 1? ifr0/vbusf = 1,vbusmn= 1 usb bus connection or disconnection detection interrupt udc core reset release bus reset reception ifr0/brst = 1 bus reset interrupt wait for setup command reception complete interrupt ifr0/cfdn = 1 endpoint information load complete interrupt usb module interrupt setting as soon as preparations are completed, enable d+ pull-up by usb1_pwr_en pin clear vbus flag (ifr0/vbusf) firmware preparations for start of usb communication clear bus reset flag (ifr0/brst) clear fifos wait for setup command reception complete interrupt interrupt request interrupt request initial settings enable vbus pin by pin function controller set usb operation clock usb module stop release write 50-byte endpoint information to epir figure 25.3 cable connection operation section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 838 of 1458 rej09b0033-0300 in applications that do not re quire usb cable connection to be detected, processing by the usb connection or disconnection detection interrupt is not necessary. preparations should be made with the bus reset interrupt. also, in applications that require connection detection regardless of d+ pull-up control, detection should be carried out using irq or a general input port. 25.4.2 cable disconnection usb function cable connected vbusmn pin = 1 usb cable disconnection vbusmn pin = 0 udc core reset end application ifr0/vbusf = 1, vbusmn = 0 usb connection or disconnection detection interrupt figure 25.4 cable di sconnection operation in applications that require connection/disconnection detection regardless of d+ pull-up control, detection should be carried out using irq or a general input port. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 839 of 1458 rej09b0033-0300 25.4.3 control transfer control transfer consists of three stages: setup, data (not always included), and status (figure 25.6). the data stage comprises several bus transactions . operation flowcharts for each stage are shown below. control-in setup stage data stage status stage control-out no data setup(0) data0 setup(0) data0 setup(0) data0 in(1) data1 out(1) data1 in(0) data0 out(0) . . . . . . data0 in(0/1) data0/1 out(0/1) data0/1 out(1) data1 in(1) data1 in(1) data1 figure 25.5 transfer st ages in control transfer section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 840 of 1458 rej09b0033-0300 ? setup stage usb function application setup token reception receive 8-byte command data in ep0s to data stage set setup command reception complete flag (ifr0/setup ts = 1) automatic processing by this module clear setup ts flag (ifr0/setup ts = 0) clear ep0i fifo (fclr/ep0iclr = 1) clear ep0o fifo (fclr/ep0oclr = 1) read 8-byte data from ep0s decode command data determine data stage direction * 1 write 1 to ep0s read complete bit (trg/ep0s rdfn = 1) to control-in data stage to control-out data stage command to be processed by application? interrupt request yes no notes: 1 in the setup stage, the application analyzes command data from the host requiring processing by the application, and determines the subsequent processing (for example, data stage direction, etc.). 2 when the transfer direction is control-out, the ep0i transfer request interrupt required in the status stage should be enabled here. when the transfer direction is control-in, this interrupt is not required and should be disabled. * 2 figure 25.6 setup stage operation section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 841 of 1458 rej09b0033-0300 ? data stage (control-in) usb function application in token reception data transmission to host set ep0i transmission complete flag (ifr0/ep0i ts = 1) from setup stage write data to ep0i data register (epdr0i) write 1 to ep0i packet enable bit (trg/ep0i pkte = 1) clear ep0i transmission complete flag (ifr0/ep0i ts = 0) write 1 to ep0i packet enable bit (trg/ep0i pkte = 1) write data to ep0i data register (epdr0i) 1 written to trg/ep0s rdfn? valid data in ep0i fifo? nak nak no no yes yes ack interrupt request figure 25.7 data stag e (control-in) operation the application first analyzes comm and data from the host in the setup stage, and determines the subsequent data stage direction. if the result of co mmand data analysis is that the data stage is in- transfer, one pack et of data to be sent to the host is written to the fifo. if there is more data to be sent, this data is written to the fifo after the data written first has been sent to the host (ifr0/ep0i ts = 1). the end of the data stage is identified when the host transmits an out token and the status stage is entered. note: if the size of the data transmitted by the function is smaller than the data size requested by the host, the function indicates the end of the da ta stage by returning to the host a packet shorter than the maximum packet size. if the si ze of the data transmitted by the function is an integral multiple of the maximum packet si ze, the function indicates the end of the data stage by transmitting a zero-length packet. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 842 of 1458 rej09b0033-0300 ? data stage (control-out) usb function application out token reception data reception from host out token reception set ep0o reception complete flag (ifr0/ep0o ts = 1) clear ep0o reception complete flag (ifr0/ep0o ts = 0) read data from ep0o receive data size register (epsz0o) write 1 to ep0o read complete bit (trg/ep0o rdfn = 1) read data from ep0o data register (epdr0o) 1 written to trg/ep0s rdfn? 1 written to trg/ep0o rdfn? nak nak ack no yes no yes interrupt request figure 25.8 data stag e (control-out) operation the application first analyzes comm and data from the host in the setup stage, and determines the subsequent data stage direction. if the result of co mmand data analysis is that the data stage is out- transfer, the application waits for data from the host, and after data is received (ifr0/ep0o ts = 1), reads data from the fifo. next, the application writes 1 to the ep0o read complete bit, empties the receive fifo, and waits for reception of the next data. the end of the data stage is identified when the ho st transmits an in token and the status stage is entered. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 843 of 1458 rej09b0033-0300 ? status stage (control-in) usb function application out token reception 0-byte reception from host end of control transfer set ep0o reception complete flag (ifr0/ep0o ts = 1) clear ep0o reception complete flag (ifr0/ep0o ts = 0) write 1 to ep0o read complete bit (trg/ep0o rdfn = 1) end of control transfer ack interrupt request figure 25.9 status stag e (control-in) operation the control-in status stage star ts with an out token from the host. the application receives 0- byte data from the host, and ends control transfer. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 844 of 1458 rej09b0033-0300 ? status stage (control-out) usb function application in token reception 0-byte transmission to host end of control transfer set ep0i transmission complete flag (ifr0/ep0i ts = 1) clear ep0i transfer request flag (ifr0/ep0i tr = 0) write 1 to ep0i packet enable bit (trg/ep0i pkte = 1) clear ep0i transmission complete flag (ifr0/ep0i ts = 0) end of control transfer valid data in ep0i fifo? ack yes no nak interrupt request interrupt request figure 25.10 status stage (control-out) operation the control-out status stage starts with an in token from the host. when an in-token is received at the start of the status stage, there is not yet any data in the ep0i fifo, and so an ep0i transfer request interrupt is generated. the application rec ognizes from this interrupt that the status stage has started. next, in order to transmit 0-byte data to the host, 1 is written to the ep0i packet enable bit but no data is written to the ep0i fifo. as a result, the next in token causes 0-byte data to be transmitted to the host, and control transfer ends. after the application has finished all processing relating to the data stage, 1 should be written to the ep0i packet enable bit. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 845 of 1458 rej09b0033-0300 25.4.4 ep1 bulk-out transfer (dual fifos) usb function application out token reception data reception from host set ep1 fifo full status (ifr0/ep1 full = 1) clear ep1 fifo full status (ifr0/ep1 full = 0) read ep1 receive data size register (epsz1) read data from ep1 data register (epdr1) write 1 to ep1 read complete bit (trg/ep1 rdfn = 1) space in ep1 fifo? no yes both ep1 fifos empty? no yes nak ack interrupt request interrupt request figure 25.11 ep1 bulk-out transfer operation ep1 has two 64-byte fifos, but the user can perform data reception and receive data reads without being aware of this dual-fifo configuration. when one fifo is full after recep tion is completed, the ifr0/ep1 full bit is set. after the first receive operation into on e of the fifos when both fifos are em pty, the other fifo is empty, and so the next packet can be receiv ed immediately. when both fifos are full, nack is returned to the host automatically. wh en reading of the receive data is co mpleted following data reception, 1 is written to the trg/ep1 rdfn bit. this operation empties the fifo that has just been read, and makes it ready to receive the next packet. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 846 of 1458 rej09b0033-0300 25.4.5 ep2 bulk-in tr ansfer (dual fifos) usb function application in token reception data transmission to host clear ep2 transfer request flag (ifr0/ep2 tr = 0) enable ep2 fifo empty interrupt (ier0/ep2 empty = 1) ifr0/ep2 empty interrupt write one packet of data to ep2 data register (epdr2) write 1 to ep2 packet enable bit (trg/ep2 pkte = 1) set ep2 empty status (ifr0/ep2 empty = 1) valid data in ep2 fifo? nak ack interrupt request yes no clear ep2 empty status (ifr0/ep2 empty = 0) space in ep2 fifo? no yes interrupt request figure 25.12 ep2 bulk-in transfer operation ep2 has two 64-byte fifos, but the user can perform data transmission and transmit data writes without being aware of this dual-fifo configuration. however, one data write is performed for one fifo. for example, even if both fifos are empty, it is not possible to perform ep2/pkte at one time after consecutively writing 128 bytes of data. ep2/pkte must be performed for each 64- byte write. when performing bulk-in transfer, as there is no valid data in the fifos on reception of the first in token, an ifr0/ep2 tr interr upt is requested. with this interrupt, 1 is written to the ier0/ep2 empty bit, and the ep2 fifo empty interrupt is enabled. at first, both ep2 fifos are empty, and so an ep2 fifo empty interrupt is generated immediately. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 847 of 1458 rej09b0033-0300 the data to be transmitted is written to the data re gister using this interrupt. after the first transmit data write for one fifo, the other fifo is empty, and so the next transmit data can be written to the other fifo immediately. when both fifos are fu ll, ep2 empty is cleared to 0. if at least one fifo is empty, ifr0/ep2 empty is set to 1. wh en ack is returned from the host after data transmission is completed, the fifo used in the data transmission becomes empty. if the other fifo contains valid transmit data at th is time, transmission can be continued. when transmission of all data has been completed, write 0 to ier0/ep2 empty and disable interrupt requests. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 848 of 1458 rej09b0033-0300 25.4.6 ep3 interrupt-in transfer usb function application in token reception data transmission to host set ep3 transmission complete flag (ifr0/ep3 ts = 1) write data to ep3 data register (epdr3) write 1 to ep3 packet enable bit (trg/ep3 pkte = 1) clear ep3 transmission complete flag (ifr1/ep3 ts = 0) write data to ep3 data register (epdr3) write 1 to ep3 packet enable bit (trg/ep3 pkte = 1) valid data in ep3 fifo? is there data for transmission to host? is there data for transmission to host? no yes no yes no yes nak ack note: this flowchart shows just one example of interrupt transfer processing. other possibilities include an operation flow in which, if there is data to be transferred, the ep3 de bit in the usb data status register is referenced to confirm that the fifo is empty, and then data is written to the fifo. interrupt request figure 25.13 ep3 interrupt-in transfer operation section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 849 of 1458 rej09b0033-0300 25.5 ep4 isochronous-out transfer sof reception fifo buffer switch over yes yes yes yes no no no out-token reception fifo a side fifo b side fifo b side no errorin receive data? time stamps match? data reception from host set ep4 abnormal reception flag to 1 (ifr3/ep4 tf = 1) set ep4 normal reception flag to 1 (ifr3/ep4 ts = 1) no clear sof packet detection flag (ifr2/sof = 0) read time stamp register h, l(tsrh,tsrl) a read ep4 receive data size register (epsz4) read ep4 flag (ifr3/ep4 ts, ep4 tf) read data from ep4 data register (epdr4) read ep4 receive data size register (epsz4) read ep4 flag (ifr3/ep4 ts, ep4 tf) read data from ep4 data register (epdr4) interrupt request (sof) interrupt request (sof) usb function firmware to figure 25.15 to figure 25.15 sof reception fifo buffer switch over out-token reception no errorin receive data? data reception from host set ep4 abnormal reception flag to 1 (ifr3/ep4 tf = 1) set ep4 normal reception flag to 1 (ifr3/ep4 ts = 1) fifo a side time stamps match? clear sof packet detection flag (ifr2/sof = 0) read time stamp register h, l(tsrh,tsrl) a figure 25.14 ep4 isochronous-out transfer operation (sof is normal) section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 850 of 1458 rej09b0033-0300 sof is broken sof reception yes out-token reception from figure 25.14 fifo a side fifo a side fifo b side fifo b side data transmitted from host is broken fifo buffer switch over no out-token reception no error in receive data? data reception from host set ep4 abnormal reception flag to 1 (ifr3/ep4 tf = 1) set ep4 normal reception flag to 1 (ifr3/ep4 ts = 1) clear time out flag (ifr4/tmout = 0) interrupt end interrupt end read time stamp register h, l (tsrh,tsrl) clear sof packet detection flag (ifr2/sof = 0) interrupt request (time out) interrupt request (sof) usb function firmware time stamps do not match a figure 25.15 ep4 isochronous-out transfer operation (sof is broken) section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 851 of 1458 rej09b0033-0300 figure 25.14 shows the normal operation of the usb function and firmware in isochronous-out transfer. ep4 has two up to 64-byte fifos, but the user can perform data transmission and read receive data without being aware of this dual-fifo configuration. in isochronous transfer, tr ansfer occurs only once per one frame (1 ms). so, when sof is received, the fifo buffer is switched automatically with hardware. fifo buffers ar e switched over by the sof reception. ther efore, the fifo buffer in which the usb function receives the data fr om the host and the fifo buffer in which the firmware reads the receive data have different buffers, and a read and write of fifo bu ffer are not competed. accordingly, the data read by the firmware is the data received in one frame before. the buffers of fifos are switched over automatically by the sof reception, so reading of data must be completed within the frame. the usb function receives data from the host after an out-token is received. if there is an error in the data, set the internal tf flag to 1. if there is no error in the data, set the internal ts flag to 1. in firmware, first, the processing routine of the isochronous transfer is called by sof interrupt to check the time stamp. then data is read from the fifo buffer. the flag information (ts, tf) is read and decided if the data has an error. the flag inform ation at this time represents the status of the currently readab le fifo buffer. sof happens to be broken because of external cau se during transmission from the host. in this case, an operation flow is different from that in figure 25.14. as an example, figure 25.14 shows the operation flow of a broken frame and a subsequent frame when sof is broken once. when sof is broken, the fifo buffer is not switched in current frame, and a ti me out interrupt occurs after time set by user has been elapsed. the usb function controller discards the data which has been transmitted to the frame from the host. the firmware detects the sof break by the time out interrupt. in this case, the fifo buffer connected to the cpu does not read data since da ta has already been read. when the sof interrupt occurs in the subsequent frame, the processing routine of the isoc hronous transfer is called and the time stamps are compared. the time stamps do not much since the sof break occurred in the previous frame. data is not read since the data in fifo is not current one. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 852 of 1458 rej09b0033-0300 25.6 ep5 isochronous-in transfer sof reception sof reception set ep5 transmit flag (ifr3/ep5 tr = 1) fifo buffer switch over yes yes yes yes no no in-token reception fifo a side fifo b side data transmission to host set ep5 transmit request flag (ifr3/ep5 tr = 1) clear sof packet detection flag (ifr2/sof = 0) write one packet of data to ep5 data register (epdr5) fifo a side interrupt request (sof) interrupt request (sof) usb function firmware valid data in ep5 fifo? data in fifo b side has been transmitted? no data in fifo a side has been transmitted? yes no fifo b side 0-byte data transmission read time stamp register h, l (tsrh, tsrl) no time stamps match? yes no to figure 25.17 to figure 25.17 clear sof packet detection flag (ifr2/sof = 0) read time stamp register h, l (tsrh, tsrl) time stamps match? set ep5 transmit flag (ifr3/ep5 tr = 1) fifo buffer switch over in-token reception data transmission to host set ep5 transmit request flag (ifr3/ep5 tr = 1) valid data in ep5 fifo? 0-byte data transmission write one packet of data to ep5 data register (epdr5) b b figure 25.16 ep5 isochronous-in transfer operation (sof is normal) section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 853 of 1458 rej09b0033-0300 sof reception in-token reception fifo a side fifo b side set ep5 transmit request flag (ifr3/ep5 tr = 1) clear time out flag (ifr4/tmout = 0) clear sof packet detection flag (ifr2/sof = 0) write 1 to ep5 cpu clear (fclr1/ep5cclr) fifo a side interrupt request (time out) interrupt request (fifo) usb function firmware no valid data in ep5 fifo 0-byte data transmission to host fifo b side 0-byte data transmission read time stamp register h, l (tsrh, tsrl) time stamps do not match write one packet of data to ep5 data register (epdr5) from figure 25.16 b in-token reception set ep5 transmit request flag (ifr3/ep5 tr = 1) no valid data in ep5 fifo 0-byte data transmission to host 0-byte data transmission fifo buffer switch over sof reception figure 25.17 ep5 isochronous-in transfer operation (sof in broken) section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 854 of 1458 rej09b0033-0300 figure 25.16 shows the normal operation of the usb function and firmware in isochronous-in transfer. ep5 has two up to 64-byte fifos, but the user can perform data transmission and write transmit data without being aware of this dual-fifo configuration. in isochronous transfer, tr ansfer occurs only once per one frame (1 ms). so, when sof is received, the fifo buffer is switched automatically with hardware. fifo buffers ar e switched over by the sof reception. ther efore, the fifo buffer in which the usb function transmits the data and the fifo buffer in which the firmware writes the transmit data have different buffers, and a read and write of fifo buffer are not competed. accordingly, the data written by the firmware is the data tr ansmitted in one frame afte r. the buffers of fifos are switched over automatically by the sof reception, so writing of data must be completed within the frame. the usb function transmits data to the host, and the internal tr flag is set to 1, when data to be transmitted to the host exists in fifo after an in-tok en is received. if there is no data in the fifo buffer, set the internal tr flag to 1 and transmit 0-byte data to the host. in firmware, first, the processing routine of the isochronous transfer is called by sof interrupt to check the time stamp. then one packet data is writte n to fifo. this written data is transmitted to the host in the next frame. sof happens to be broken because of external cau se during transmission from the host. in this case, an operation flow is different from that in figure 25.16. as an example, figure 25.17 shows the operation flow of a broken frame and a subsequent frame when sof is broken once. when sof is broken, the fifo buffer is not switched in corresponding frame, and a time out interrupt occurs after time set by user has been elapsed. the firmware detects the sof br eak by the time out interrupt. in this case, the fifo buffer connected to the cpu has the data to be transmitted in the current frame. if this data is transmitted in the next frame, the data which is not current on e is transmitted. therefor e, the firmware writes the ep5 cpu clear (fclr1/ep5 cclr) to 1. when the sof interrupt occurs in the subsequent frame, the processing routine of the isochronous transfer is called and the time stamps are compared. the time stamps do not much since the sof break occurre d in the previous frame. one packet of data is written by the firmware according to the transmitted time stamp. in the frame in which the sof is broken, the fifo buffer is not switched and there in no data to be transmitted to the host. therefore, usb function cont roller transmits 0-byte data to the host. since the data to be transmitted is cleared by firmware, 0-byte data is transmitted to the host. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 855 of 1458 rej09b0033-0300 25.7 processing of usb standard commands and class/vendor commands 25.7.1 processing of commands transmitted by control transfer a command transmitted from the host by control tr ansfer may require decoding and execution of command processing on the application side. whether command decoding is required on the application side is indicated in table 25.5 below. table 25.5 command decoding on application side decoding not necessary on application si de decoding necessary on application side clear feature get configuration get interface get status set address set configuration set feature set interface get descriptor class/vendor command synch frame set descriptor if decoding is not necessary on the application side, command decoding and data stage and status stage processing are performed auto matically. no processing is necessary by the user. an interrupt is not generated in this case. if decoding is necessary on the application side, this module stores the command in the ep0s fifo. after normal reception is completed, the ifr0/setup ts flag is set and an interrupt request is generated. in the interrupt routine, 8 bytes of data must be read from the ep0s data register (epdr0s) and decoded by firmware. the n ecessary data stage and st atus stage processing should then be carried out according to the result of the decoding operation. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 856 of 1458 rej09b0033-0300 25.8 stall operations 25.8.1 overview this section describes stall operations in this module. there are two cases in which the usb function controller stall function is used: ? when the application forcibly sta lls an endpoint for some reason ? when a stall is performed automatically within the usb function controller due to a usb specification violation the usb function controller has internal status bits that hold the status (stall or non-stall) of each endpoint. when a transaction is sent from the host, the module refere nces these internal status bits and determines whether to return a stall to the host. these bits cannot be cleared by the application; they must be cleared with a clear feature command from the host. however, the internal status bit to ep0 is auto matically cleared only when the setup command is received. 25.8.2 forcible stall by application the application uses the epstl register to issue a stall request for the usb function controller. when the application wishes to st all a specific endpoint, it sets th e corresponding bit in epstl (1- 1 in figure 25.16). the internal status bits are no t changed at this time. when a transaction is sent from the host for the endpoint for which the epstl bit was set, the usb function controller references the internal status bit, and if this is not set, references the corresponding bit in epstl (1-2 in figure 25.16). if the corresponding bit in usbepstl is set, the usb function controller sets the internal status bit and returns a stall handshake to the host (1-3 in figure 25.16). in this time, if the ctlr/asce bit is set to 1, the corres ponding bit in epstl is automatically cleared to 0 and a stall handshake is returned to the host (1-4 in figure 25.16). if the corresponding bit in epstl is not set, the internal status bit is not changed and the transaction is accepted. once an internal status bit is set, it remains set until cleared by a clear feature command from the host, without regard to the epstl register. even after a bit is cleared by the clear feature command (3-1 in figure 25.16), the usb function controller continues to return a stall handshake while the bit in epstl is set, sin ce the internal status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figure 25.16) . to clear a stall, theref ore, it is necessary for the corresponding bit in epstl to be cleared automa tically when a stall is returned from the usb controller while the ctlr/asce bit is set to 1, or to be cleared by the application, and also for section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 857 of 1458 rej09b0033-0300 the internal status bit to be cleared with a cl ear feature command (2-1, 2-2, and 2-3 in figure 25.16). (1) transition from normal operation to stall (1-1) transaction request usb reference (1-2) stall handshake stall to 2 of (2-1) to (2-1) or (3-1) normal status restored (1-3) (2) when clear feature is sent after epstl is cleared (2-1) stall handshake transaction request (2-2) clear feature command clear feature command (2-3) (3) when clear feature is sent before epstl is cleared to 0 (3-1) 1. 1 written to epnstl by application 1. in/out token received from host 2. epnstl referenced 1. transmission of stall handshake 1. internal status bit cleared to 0 1. internal status bit cleared to 0 2. epnstl not changed 1. epnstl cleared to 0 by application 2. in/out token received from host 3. internal status bit already set to 1 4. epnstl not referenced 5. internal status bit not changed to (1-2) internal status bit 0 epnstl 0 1 internal status bit 0 epnstl 1 internal status bit 0 1 epnstl 1 internal status bit 1 epnstl 1 0 internal status bit 1 epnstl 0 internal status bit 1 0 epnstl 0 internal status bit 1 0 epnstl 1 stall handshake stall (1-4) internal status bit 0 1 epnstl 1 1. 1 set in ctlr/asce 2. 1 set in epnstl 3. epnstl cleared to 0 automatically 4. internal status bit set to 1 5. transmission of stall handshake note: the ctlr/asce bit should be set to 1 before the epnstl bit (each stall bit) in epstl is set to 1. 1. 0 set in ctlr/asce 2. 1 set in epnstl 3. internal status bit set to 1 4. transmission of stall handshake figure 25.18 forcible stall by application section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 858 of 1458 rej09b0033-0300 25.8.3 automatic stall by usb function controller when a stall setting is made with the set featur e command, or in the event of a usb specification violation, the usb function controller automatically sets the internal status bit for the relevant endpoint without regard to the corresponding bit in epstl, and returns a stall handshake (1-1 in figure 25.19). once an internal status bit is set, it remains set until cleared by a clear feature command from the host, without regard to the corresponding bit in e pstl. after a bit is cleared by the clear feature command, the corresponding bit in epstl is referenced (3-1 in figure 25.19). the usb function controller continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 25.19). to clear a st all, therefore, the internal status bi t must be cleared with a clear feature command (3-1 in figure 25.19). in this time, if set by the application, the corresponding bit in epstl should also be cleared (2-1 in figure 25.19). (1) transition from normal operation to stall (1-1) (2) when transaction is performed when internal status bit is set, and clear feature is sent (2-1) stall handshake transaction request stall handshake (2-2) clear feature command (3) when clear feature is sent before transaction is performed (3-1) 1. in case of usb specification violation, etc., usb function module stalls endpoint automatically 1. transmission of stall handshake 1. internal status bit cleared to 0 2. epnstl not changed 1. epnstl cleared to 0 by application 2. in/out token received from host 3. internal status bit already set to 1 4. epnstl not referenced 5. internal status bit not changed normal status restored internal status bit 0 1 epnstl 0 internal status bit 1 epnstl 0 internal status bit 1 epnstl 0 internal status bit 1 0 epnstl 0 stall status maintained to (2-1) or (3-1) figure 25.19 automatic stal l by usb function controller section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 859 of 1458 rej09b0033-0300 25.9 usage notes 25.9.1 setup da ta reception the following points should be noted on the ep0s data register (epdr0s) in which reception of 8- byte setup data is performed. 1. since the setup command must be received in th e usb, writing from the usb bus side is prior to reading from the cpu side. while the cpu reads data after completion of reception and reception of the next setup command is started, reading from the cpu side is forcibly invalid. therefore a value to be read after starting reception is undefined. 2. epdr0s must be read in 8-byte units. if reading is suspended while it is in progress, data received in the next setup ca nnot be read successfully. 25.9.2 fifo clear when the usb cable is disconnected during co mmunication, data which is receiving or transmitting may remain in the fifo. therefore the fifo must be cleared immediately after connecting the usb cable again. note that the fifo in which data is receiving from the host or transm itting to the host must not be cleared. 25.9.3 overreading/overwrit ing of data register the following points should be noted when the data register of the usbf is read from or written to. (1) receive data register the receive data register must not read data which is more than valid receiv e data bytes. that is, data which is more than bytes indicated in the r eceive data size register must not be read. in case of the receive data register which has the dual fifo buffer, the maximum number of data which can be read in a single time is maximum packet size. write 1 to trg after data in the current valid buffer is read. this writing switches the fifo buffer. then, the new number of bytes is reflected in the receive data size and the next data can be read. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 860 of 1458 rej09b0033-0300 (2) transmit data register the transmit data register must not write data wh ich is more than maximum packet size. in case of the transmit data register which has the dual fifo buffer, the maximum number of data which can be written in a single time is maximum packet size. write 1 to trg/pkte after data is written. this writing switches the fifo buffer. then, the next data can be written to another buffer. therefore data must not be written in both buffers in a single time. 25.9.4 assigning ep0 interrupt sources the ep0 interrupt sources assigned to ifr0 (bits 0, 1, and 2) must be assigned to the same interrupt pins by isr0. the other interrupt sources have no restrictions. 25.9.5 fifo clear when dma transfer is set when the dma transfer is enabled in endpoint 1, the data register cannot be cleared. cancel the dma transfer before clearing the data register. 25.9.6 note on using tr interrupt the bulk-in transfer has a transfer request interrupt (tr interrupt). the following points should be noted when using a tr interrupt. when the in token is sent from the usb host and there is no data in the corresponding ep fifo, the tr interrupt flag is set. however, the tr inte rrupt is generated continuously at the timing as shown in figure 20.18. in this case, note that erroneous operation should not occur. note: when the in token is received and there is no data in the corresponding ep fifo, an nak is determined. however, the tr interrupt flag is set after an nak handshake is transmitted. therefore when the next in t oken is received before trg/pkte is written, the tr interrupt flag is set again. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 861 of 1458 rej09b0033-0300 cpu tr flag clearing in token in token in token nak determination nak determination tr flag setting tr flag setting (tr flag is set again) nak nak ack data transmission transmit data writing trg/ pkte host usb tr interrupt routine tr interrupt routine figure 25.20 set timing of tr interrupt flag 25.9.7 note on clock frequency when using the usbf, be sure to set the peripheral clock (p ) at a frequency higher than 13 mhz. section 25 usb function controller (usbf) rev. 3.00 jan. 18, 2008 page 862 of 1458 rej09b0033-0300 section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 863 of 1458 rej09b0033-0300 section 26 lcd controller (lcdc) a unified memory architecture is adopted for the lcd controller (lcdc) so that the image data for display is stored in system memory. the lcdc module reads data from system memory, uses the palette memory to determine the colors, then puts the display on the lcd panel. it is possible to connect the lcdc to the lcd module* othe r than microcomputer bus interface types and ntsc/pal types and those that apply the lvds interface. note: * lcd module can be connected to the lvds interface by using the lsi with lvds conversion lsi. 26.1 features the lcdc has the following features. ? panel interface ? serial interface method ? supports data formats for stn/dual-stn/tft panels (8/12/16/18-bit bus width)* 1 ? supports 4/8/15/16-bpp (bits per pixel) color modes ? supports 1/2/4/6-bpp grayscale modes ? supports lcd-panel sizes from 16 1 to 1024 1024* 2 ? 24-bit color palette memory (16 of the 24 bits are valid; r:5/g:6/b:5) ? stn/dstn panels are prone to flicker and shadowing. the controller applies 65536-color control by 24-bit space-modulation frc (frame rate controller) with 8-bit rgb values for reduced flicker. ? dedicated display memory is unnecessary using part of the synchronous dram (area 3) as the vram to store display data of the lcdc. ? the display is stable because of the large 2.4-kby te line buffer ? supports the inversion of the output signal to suit the lcd panel's signal polarity ? supports the selection of data formats (the endian setting for bytes, packed pixel method) by register settings ? an interrupt can be generated at the user specified position (controlling the timing of vram update start prevents flicker) ? a hardware-rotation mode is included to support the use of landscape-format lcd panels as portrait-format lcd panels (the horizontal width of the panel before rotation must be within 320 pixels (see table 26.4.) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 864 of 1458 rej09b0033-0300 notes: 1. when connecting the lcdc to a tft panel with an unwired 18-bit bus, the lower bit lines should be connected to gnd or to the lowest bit from which data is output. 2. for details, see section 26.4.1, lcd module sizes which can be displayed in this lcdc. figure 26.1 shows a block diagram of lcdc. clock generator pallet ram lcdc power control register lcd_clk bus clock (b ) peripheral clock (p ) bus interface bus interface bsc external memory (vram) line buffer 2.4 kbytes 4 bytes 256 entries lcd_cl1 lcd_cl2 lcd_flm lcd_data 15 to 0 lcd_don lcd_vcpwc lcd_vepwc lcd_m_disp peripheral bus dotclk figure 26.1 lcdc block diagram section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 865 of 1458 rej09b0033-0300 26.2 input/output pins table 26.1 summarizes the lcdc's pin configuration. table 26.1 pin configuration pin name i/o function lcd_data15 to 0 output data for lcd panel lcd_don output display-on signal (don) lcd_cl1 output shift-clock 1 (stn/dstn) /horizontal sync signal (hsync) (tft) lcd_cl2 output shift-clock 2 (stn /dstn)/dot clock (dotclk) (tft) lcd_m_disp output lcd current -alternating signal/disp signal lcd_flm output first line marker/v ertical sync signal (vsync) (tft) lcd_vcpwc output lcd-module power control (vcc) lcd_vepwc output lcd-module power control (vee) lcd_clk input lcd clock-source input note: check the lcd module specifications carefully in section 26.5, clock and lcd data signal examples, before deciding on the wir ing specifications for the lcd module. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 866 of 1458 rej09b0033-0300 26.3 register configuration the lcdc includes the following registers. refer to section 37, list of registers, for more details on the addresses and states of th ese registers in each operating mode. ? lcdc input clock register (ldickr) ? lcdc module type register (ldmtr) ? lcdc data format register (lddfr) ? lcdc scan mode register (ldsmr) ? lcdc data fetch start address register for upper display panel (ldsaru) ? lcdc data fetch start address register for lower display panel (ldsarl) ? lcdc fetch data line address offset register for display panel (ldlaor) ? lcdc palette control register (ldpalcr) ? lcdc palette data register 00 to ff (ldpr00 to ldprff) ? lcdc horizontal character number register (ldhcnr) ? lcdc horizontal synchronization signal register (ldhsynr) ? lcdc vertical displayed line number register (ldvdlnr) ? lcdc vertical total line number register (ldvtlnr) ? lcdc vertical synchronization signal register (ldvsynr) ? lcdc ac modulation signal toggle line number register (ldaclnr) ? lcdc interrupt control register (ldintr) ? lcdc power management mode register (ldpmmr) ? lcdc power supply sequence period register (ldpspr) ? lcdc control register (ldcntr) ? lcdc user specified interrupt control register (lduintr) ? lcdc user specified interrupt lin e number register (lduintlnr) ? lcdc memory access interval number register (ldlirnr) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 867 of 1458 rej09b0033-0300 26.3.1 lcdc input clock register (ldickr) this lcdc can select the bus clock (b ), the peripheral clock (p ), or the external clock (lcd_clk) as its operation clock source. the selected clock source can be divided using an internal divider into a clock of 1/1 to 1/32 and be used as the lcdc operating clock (dotclk). the clock output from the lcdc is used to generate the synchronous clock output (lcd_cl2) for the lcd panel from the operating clock selected in this register. for a tft panel, lcd_cl2 = dotclk, and for an stn or dstn panel, lcd_cl2 = a clock with a frequency of (dotclk/data bus width of output to lcd panel). the ldickr must be set so that the clock input to the lcdc is 66 mhz or less regardless of the lcd_cl2. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 icksel1 icksel0 0 0 r/w r/w input clock select set the clock source for dotclk. 00: bus clock is selected (b ) 01: peripheral clock is selected (p ) 10: external clock is selected (lcd_clk) 11: setting prohibited 11 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 4 3 2 1 0 dcdr5 dcdr4 dcdr3 dcdr2 dcdr1 dcdr0 0 0 0 0 0 1 r/w r/w r/w r/w r/w r/w clock division ratio set the input clock division ratio. for details on the setting, refer to table 26.2. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 868 of 1458 rej09b0033-0300 table 26.2 i/o clock frequency and clock division ratio i/o clock frequency (mhz) dcdr[5:0] clock division ratio 50.000 60.000 66.000 000001 1/1 50.000 60.000 66.000 000010 1/2 25.000 30.000 33.000 000011 1/3 16.667 20.000 22.000 000100 1/4 12.500 15.000 16.500 000110 1/6 8.333 10.000 11.000 001000 1/8 6.250 7.500 8.250 001100 1/12 4.167 5.000 5.500 010000 1/16 3.125 3.750 4.125 011000 1/24 2.083 2.500 2.750 100000 1/32 1.563 1.875 2.063 note: any setting other than above is handled as a clock division ratio of 1/1 (initial value). 26.3.2 lcdc module type register (ldmtr) ldmtr sets the control signals output from this lcdc and the polarity of the data signals, according to the polarity of the signals for the lcd module connected to the lcdc. bit bit name initial value r/w description 15 flmpol 0 r/w flm (vertical sync signal) polarity select selects the polarity of the lcd_flm (vertical sync signal, first line marke r) for the lcd module. 0: lcd_flm pulse is high active 1: lcd_flm pulse is low active 14 cl1pol 0 r/w cl1 (horizontal sync signal) polarity select selects the polarity of the lcd_cl1 (horizontal sync signal) for the lcd module. 0: lcd_cl1 pulse is high active 1: lcd_cl1 pulse is low active section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 869 of 1458 rej09b0033-0300 bit bit name initial value r/w description 13 disppol 0 r/w disp (display enable) polarity select selects the polarity of the lcd_m_disp (display enable) for the lcd module. 0: lcd_m_disp is high active 1: lcd_m_disp is low active 12 dpol 0 r/w display data polarity select selects the polarity of the lcd_data (display data) for the lcd module. this bit supports inversion of the lcd module. 0: lcd_data is high active, transparent-type lcd panel 1: lcd_data is low active, reflective-type lcd panel 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 mcnt 0 r/w m signal control sets whether or not to output the lcd's current- alternating signal of the lcd module. 0: m (ac line modulation) signal is output 1: m signal is not output 9 cl1cnt 0 r/w cl1 (horizontal sync signal) control sets whether or not to enable cl1 output during the vertical retrace period. 0: cl1 is output during vertical retrace period 1: cl1 is not output during vertical retrace period 8 cl2cnt 1 r/w cl2 (dot cl ock of lcd module) control sets whether or not to enable cl2 output during the vertical and horizontal retrace period. 0: cl2 is output during vertical and horizontal retrace period 1: cl2 is not output duri ng vertical and horizontal retrace period 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 870 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 4 3 2 1 0 miftyp5 miftyp4 miftyp3 miftyp2 miftyp1 miftyp0 0 0 1 0 0 1 r/w r/w r/w r/w r/w r/w module interface type select set the lcd panel type and data bus width to be output to the lcd panel. there are three lcd panel types: stn, dstn, and tft. there are four data bus widths for output to the lcd panel: 4, 8, 12, and 16 bits. when the required data bus width for a tft panel is 16 bits or more, connect the lcdc and lcd panel according to the data bus size of the lcd panel. unlike in a tft panel, in an stn or dstn panel, the data bus width setting does not have a 1:1 correspondence with the number of display colors and display resolution, e.g., an 8-bit data bus can be used for 16 bpp, and a 12-bit data bus can be used for 4 bpp. this is because the number of display colors in an stn or dstn panel is determined by how data is placed on the bus, and not by the number of bits. for data specifications for an stn or dstn panel, see the specific ations of the lcd panel used. the output data bus width should be set according to the mechanical interface specifications of the lcd panel. if an stn or dstn panel is selected, display control is performed using a 24-bit space-modulation frc (frame rate controller) consisting of the 8-bit r, g, and b included in the lcdc, regardless of the color and gradation settings. accordingly, the color and gradation specified by dspcolor is selected from 16 million colors in an stn or dstn panel. if a palette is used, the color specified in the palette is displayed. 000000: stn monochrome 4-bit data bus module 000001: stn monochrome 8-bit data bus module 001000: stn color 4-bit data bus module 001001: stn color 8-bit data bus module 001010: stn color 12-bit data bus module 001011: stn color 16-bit data bus module 010001: dstn monochrome 8-bit data bus module 010011: dstn monochrome 16-bit data bus module 011001: dstn color 8-bit data bus module 011010: dstn color 12-bit data bus module 011011: dstn color 16-bit data bus module 101011: tft color 16-bit data bus module settings other than above: setting prohibited section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 871 of 1458 rej09b0033-0300 26.3.3 lcdc data format register (lddfr) lddfr sets the bit alignment for pixel data in one byte and selects the data type and number of colors used for display so as to match the display driver software specifications. bit bit name initial value r/w description 15 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 pabd 0 r/w byte data pixel alignment sets the pixel data alignment type in one byte of data. the contents of alig ned data per pixel are the same regardless of this bit's setting. for example, data h'05 should be expressed as b'0101 which is the normal style handled by a mov instruction of the this cpu, and should not be selected between b'0101 and b'1010. 0: big endian for byte data 1: little endian for byte data 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 872 of 1458 rej09b0033-0300 bit bit name initial value r/w description 6 5 4 3 2 1 0 dspcolor6 dspcolor5 dspcolor4 dspcolor3 dspcolor2 dspcolor1 dspcolor0 0 0 0 1 1 0 0 r/w r/w r/w r/w r/w r/w r/w display color select set the number of display colors for the display (0 is written to upper bits of 4 to 6 bpp). for display colors to which the description (via palette) is added below, the color set by the color palette is actually selected by the display data and displayed. the number of colors that can be selected in rotation mode is restricted by the display resolution. for details, see table 26.4. 0000000: monochrome, 2 gr ayscales, 1 bpp (via palette) 0000001: monochrome, 4 gr ayscales, 2 bpp (via palette) 0000010: monochrome, 16 grayscales, 4 bpp (via palette) 0000100: monochrome, 64 grayscales, 6 bpp (via palette) 0001010: color, 16 colors, 4 bpp (via palette) 0001100: color, 256 colors, 8 bpp (via palette) 0011101: color, 32k colors (rgb: 555), 15 bpp 0101101: color, 64k colors (rgb: 565), 16 bpp settings other than above: setting prohibited section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 873 of 1458 rej09b0033-0300 26.3.4 lcdc scan mode register (ldsmr) ldsmr selects whether or not to enable the hardware rotation function that is used to rotate the lcd panel, and sets the burst length for the vram (synchronous dram in area 3) used for display. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 rot 0 r/w rotation module select selects whether or not to rotate the display by hardware. note that the following restrictions are applied to rotation. ? an stn or tft panel must be used. a dstn panel is not allowed. ? the maximum horizontal (internal scan direction of the lcd panel) width of the lcd panel is 320. ? set a binary exponential that exceeds the display size in ldlaor. (for example, 256 must be selected when a 320 240 panel is rotated to be used as a 240 320 panel and the horizontal width of the image is 240 bytes.) 0: not rotated 1: rotated 90 degrees rightwards (left side of image is displayed on the upper side of the lcd module) 12 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 874 of 1458 rej09b0033-0300 bit bit name initial value r/w description 9 8 au1 au0 0 0 r/w r/w access unit select select access unit of vram. this bit is enabled when rot = 1 (rotate the display). when rot = 0, 16-burst memory read operation is carried out whatever the au setting is. 00: 4-burst 01: 8-burst 10: 16-burst 11: 32-burst notes: 1. above burst lengths are used for 32-bit bus. for 16-bit bus, the burst lengths are twice the lengths of 32-bit bus. 2. when displaying a rotated image, the burst length is limited depending on the number of column address bits and bus width of connected sdram. for details, see tables 26.3 and 26.4. 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 875 of 1458 rej09b0033-0300 26.3.5 lcdc start address register for upper display data fetch (ldsaru) ldsaru sets the start address from which data is fetched by the lcdc for display of the lcdc panel. when a dstn panel is used, this register specifies the fetch start address for the upper side of the panel. bit bit name initial value r/w description 31 to 28 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 27, 26 ? all 1 r reserved these bits are always read as 1. the write value should always be 1. 25 to 4 sau25 to sau4 all 0 r/w start address for upper display data fetch the start address for data fe tch of the display data must be set within the synchronous dram area of area 3. 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. notes: 1. the minimum alignment unit of ld saru is 512 bytes when the hardware rotation function is not used. write 0 to the lower nine bits. when using the hardware rotation function, set the ldsaru value so that the upper-left address of the image is aligned with the 512-byte boundary. 2. when the hardware rotation function is us ed (rot = 1), set the upper-left address of the image, which can be calculated from the display image size in this register. the equation below shows how to calculate the ldsaru value when the image size is 240 340 and ldlaor = 256. the ldsaru value is obtained not from the panel size but from the memory size of the image to be displayed. note that ldlaor must be a binary exponential at least as large as t he horizontal width of the image. calculate backwards using the ldsaru value (ldsaru ? 256 (ldlaor value) (320 ? 1)) to ensure that the upper-left address of the im age is aligned with the 512-byte boundary. ldsaru = (upper-left address of image) + 256 (ldlaor value) 319 (line) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 876 of 1458 rej09b0033-0300 26.3.6 lcdc start address register fo r lower display data fetch (ldsarl) when a dstn panel is used, ldsarl specifies th e fetch start address for the lower side of the panel. bit bit name initial value r/w description 31 to 28 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 27, 26 ? all 1 r reserved these bits are always read as 1. the write value should always be 1. 25 to 4 sal25 to sal4 all 0 r/w start address for lower panel display data fetch the start address for data fe tch of the display data must be set within the synchronous dram area of area 3. stn and tft: cannot be used dstn: start address for fetching display data corresponding to the lower panel 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 877 of 1458 rej09b0033-0300 26.3.7 lcdc line address offset register for display data fetch (ldlaor) ldlaor sets the address width of the y-coordina tes increment used for lcdc to read the image recognized by the graphi cs driver. this register specifies how many bytes the address from which data is to be read should be moved when the y coordinates have been incremented by 1. this register does not have to be equal to the horizontal width of the lcd panel. when the memory address of a point (x, y) in the two-dimensional im age is calculated by ax + by+ c, this register becomes equal to b in this equation. bit bit name initial value r/w description 15 to 10 lao15 to lao10 all 0 r/w 9 lao9 1 r/w 8 lao8 0 r/w 7 lao7 1 r/w 6 to 0 lao6 to lao0 all 0 r/w line address offset the minimum alignment unit of ldlaor is 16 bytes. because the lcdc handles these values as 16-byte data, the values written to the lower four bits of the register are always treated as 0. the lower four bits of the register are always read as 0. the initial values ( resolution = 640) will continuously and accurately place the vga (640 480 dots) display data without skipping an address between lines. for details, see tables 26.3 and 26.4. a binary exponential at least as large as the horizontal width of the image is recommended for the ldlaor value while taking into consideration the software operation speed. when the hardware rotation function is used, the ldlaor value should be a binary exponential (in this example, 256) at least as large as the horizontal width of the image (after rotation, it becomes 240 in a 240 320 panel) instead of the horizontal width of the lcd panel (320 in a 320 240 panel). section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 878 of 1458 rej09b0033-0300 26.3.8 lcdc palette control register (ldpalcr) ldpalcr selects whether the cpu or lcdc acce sses the palette memory. when the palette memory is being used for display operation, display mode should be selected. when the palette memory is being written to, color-palette setting mode should be selected. bit bit name initial value r/w description 15 to 5 ? all 0 r reserved these bits always read as 0. the write value should always be 0. 4 pals 0 r palette state indicates the access right state of the palette. 0: display mode: lcdc uses the palette 1: color-palette setting mode: the host (cpu) uses the palette 3 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 palen 0 r/w palette read/write enable requests the access right to the palette. 0: request for transition to normal display mode 1: request for transition to color palette setting mode section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 879 of 1458 rej09b0033-0300 26.3.9 palette data registers 00 to ff (ldpr00 to ldprff) ldpr registers are for accessing palette data directly allocated (4 bytes x 256 addresses) to the memory space. to access the palette memory, acce ss the corresponding re gister among this register group (ldpr00 to ldprff). each palette register is a 32-bit register including three 8-bit areas for r, g, and b. for details on the colo r palette specifications, see section 26.4.3, color palette specification. bit bit name initial value r/w description 31 to 24 ? ? r reserved 23 to 0 paldnn23 to paldnn0 ? r/w palette data bits 18 to 16, 9, 8, and 2 to 0 are reserved within each rgb palette and cannot be set. however, these bits can be extended according to the upper bits. note: nn = h'00 to h'ff section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 880 of 1458 rej09b0033-0300 26.3.10 lcdc horizontal character number register (ldhcnr) ldhcnr specifies the lcd module's horizontal size (in the scan direction) and the entire scan width including the horizontal retrace period. bit bit name initial value r/w description 15 14 13 12 11 10 9 8 hdcn7 hdcn6 hdcn5 hdcn4 hdcn3 hdcn2 hdcn1 hdcn0 0 1 0 0 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w horizontal display character number set the number of horizontal display characters (unit: character = 8 dots). specify to the value of (the number of display characters) -1. example: for a lcd module with a width of 640 pixels. hdcn = (640/8) -1 = 79 = h'4f 7 6 5 4 3 2 1 0 htcn7 htcn6 htcn5 htcn4 htcn3 htcn2 htcn1 htcn0 0 1 0 1 0 0 1 0 r/w r/w r/w r/w r/w r/w r/w r/w horizontal total character number set the number of total horizontal characters (unit: character = 8 dots). specify to the value of (the number of total characters) - 1. however, the minimum horizontal retrace period is three characters (24 dots). example: for a lcd module with a width of 640 pixels. htcn = [(640/8)-1] +3 = 82 = h'52 in this case, the number of total horizontal dots is 664 dots and the horizontal retrace period is 24 dots. notes: 1. the values set in hdcn and htcn must satisfy the relationship of htcn hdcn. 2. set hdcn according to the display resolution as follows: 1 bpp: (multiplex of 16) ? 1 [1 line is multiplex of 128 pixel] 2 bpp: (multiplex of 8) ? 1 [1 line is multiplex of 64 pixel] 4 bpp: (multiplex of 4) ? 1 [1 line is multiplex of 32 pixel] 6 bpp/8 bpp: (multiplex of 2) ? 1 [1 line is multiplex of 16 pixel] section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 881 of 1458 rej09b0033-0300 26.3.11 lcdc horizontal sync signal register (ldhsynr) ldhsynr specifies the timing of the generation of the horizontal (scan direction) sync signals for the lcd module. bit bit name initial value r/w description 15 14 13 12 hsynw3 hsynw2 hsynw1 hsynw0 0 0 0 0 r/w r/w r/w r/w horizontal sync signal width set the width of the horizontal sync signals (cl1 and hsync) (unit: character = 8 dots). specify to the value of (t he number of horizontal sync signal width) -1. example: for a horizontal sync signal width of 8 dots. hsynw = (8 dots/8 dots/character) -1 = 0 = h'0 11 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 5 4 3 2 1 0 hsynp7 hsynp6 hsynp5 hsynp4 hsynp3 hsynp2 hsynp1 hsynp0 0 1 0 1 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w horizontal sync signal output position set the output position of the horizontal sync signals (unit: character = 8 dots). specify to the value of (t he number of horizontal sync signal output position) -1. example: for a lcd module with a width of 640 pixels. hsynp = [(640/8) +1] -1 = 80 = h'50 in this case, the horizontal sync signal is active from the 648th through the 655th dot. note: the following conditions must be satisfied: htcn hsynp+hsynw+1 hsynp hdcn+1 section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 882 of 1458 rej09b0033-0300 26.3.12 lcdc vertical display line number register (ldvdlnr) ldvdlnr specifies the lcd modul e's vertical size (for both s can direction and vertical direction). for a dstn panel, specify an even numb er at least as large as the lcd panel's vertical size regardless of the size of the upper and lower panels, e.g. 480 for a 640 x 480 panel. bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 7 6 5 4 3 2 1 0 vdln10 vdln9 vdln8 vdln7 vdln6 vdln5 vdln4 vdln3 vdln2 vdln1 vdln0 0 0 1 1 1 0 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w vertical display line number set the number of vertical display lines (unit: line). specify to the value of (the number of display line) - 1. example: for an 480-line lcd module vdln = 480-1 = 479 = h'1df section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 883 of 1458 rej09b0033-0300 26.3.13 lcdc vertical total line number register (ldvtlnr) ldvtlnr specifies the lcd panel's entire vertical size including the vertical retrace period. bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 9 8 7 6 5 4 3 2 1 0 vtln10 vtln9 vtln8 vtln7 vtln6 vtln5 vtln4 vtln3 vtln2 vtln1 vtln0 0 0 1 1 1 0 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w vertical total line number set the total number of vertical display lines (unit: line). specify to the value of (the number of total line) -1. the minimum for the total number of vertical lines is 2 lines. the following conditions must be satisfied: vtln>=vdln, vtln>=1. example: for an 480-line lcd module and a vertical period of 0 lines. vtln = (480+0) ?1 = 479 = h'1df section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 884 of 1458 rej09b0033-0300 26.3.14 lcdc vertical sync signal register (ldvsynr) ldvsynr specifies the vertical (scan direction and vertical direction) sync signal timing of the lcd module. bit bit name initial value r/w description 15 14 13 12 vsynw3 vsynw2 vsynw1 vsynw0 0 0 0 0 r/w r/w r/w r/w vertical sync signal width set the width of the vertical sync signals (flm and vsync) (unit: line). specify to the value of (the vertical sync signal width) -1. example: for a vertical sync signal width of 1 line. vsynw = (1-1) = 0 = h'0 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 10 9 8 7 6 5 4 3 2 1 0 vsynp10 vsynp9 vsynp8 vsynp7 vsynp6 vsynp5 vsynp4 vsynp3 vsynp2 vsynp1 vsynp0 0 0 1 1 1 0 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w vertical sync signal output position set the output position of the vertical sync signals (flm and vsync) (unit: line). specify to the value of (t he number of vertical sync signal output position) -2. dstn should be set to an odd number value. it is handled as (setting value+1)/2. example: for an 480-line lcd module and a vertical retrace period of 0 lines (in other words, vtln=479 and the vertical sync signal is active for the first line): ? single display vsynp = [(1-1)+vtln]mod(vtln+1) = [(1-1)+479]mod(479+1) = 479mod480 = 479 =h'1df ? dual displays vsynp = [(1-1) 2+vtln]mod(vtln+1) = [(1-1) 2+479]mod(479+1) = 479mod480 = 479 =h'1df section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 885 of 1458 rej09b0033-0300 26.3.15 lcdc ac modulation signal toggle line number register (ldaclnr) ldaclnr specifies the timing to toggle the ac modulation signal (lcd current-alternating signal) of the lcd module. bit bit name initial value r/w description 15 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 3 2 1 0 acln4 acln3 acln2 acln1 acln0 0 1 1 0 0 r/w r/w r/w r/w r/w ac line number set the number of lines where the lcd current- alternating signal of the lcd module is toggled (unit: line). specify to the value of (t he number of toggle line) - 1. example: for toggling every 13 lines. acln = 13-1 = 12= h'0c note: when the total line number of the lcd panel is even, set an even number so that toggling is performed at an odd line. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 886 of 1458 rej09b0033-0300 26.3.16 lcdc interrupt control register (ldintr) ldintr specifies where to control the vsync in terrupt of the lcd modul e. see also 26.3.20, lcdc user specified interrupt control register (lduintr) and 26.3.21, lcdc user specified interrupt line number register (lduintlnr) for in terrupts. note that operations by this register setting and lcdc user specified interrupt control register (lduintr) setting are independent. bit bit name initial value r/w description 15 minten 0 r/w memory access interrupt enable enables or disables an interrupt generation at the start point of each vertical retrace line period for vram access by lcdc. 0: disables an interrupt gener ation at the start point of each vertical retrace line period for vram access 1: enables an interrupt gener ation at the start point of each vertical retrace line period for vram access 14 finten 0 r/w frame end interrupt enable enables or disables the generation of an interrupt after the last pixel of a frame is output to ldc panel. 0: disables an interrupt generation when the last pixel of the frame is output 1: enables an interrupt generation when the last pixel of the frame is output 13 vsinten 0 r/w vsync starting point interrupt enable enables or disables the generation of an interrupt at the start point of lcdc's vsync. 0: interrupt at the start point of the vsyncl is disabled 1: interrupt at the start point of the vsync is enabled 12 veinten 0 r/w vsync ending point interrupt enable enables or disables the generation of an interrupt at the end point of lcdc's vsync. 0: interrupt at the end point of the vsync signal is disabled 1: interrupt at the end point of the vsync signal is enabled section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 887 of 1458 rej09b0033-0300 bit bit name initial value r/w description 11 mints 0 r/w memory access interrupt state indicates the memory access interrupt handling state. this bit indicates 1 when the lcdc memory access interrupt is generated (set state). during the memory access interrupt handling routine, this bit should be cleared by writing 0. 0: lcdc did not generate a memory access interrupt or has been informed that the generated memory access interrupt has completed 1: lcdc has generated a memory access end interrupt and not yet been informed that the generated memory access interrupt has completed 10 fints 0 r/w flame end interrupt state indicates the flame end interrupt handling state. this bit indicates 1 at the time when the lcdc flame end interrupt is generated (set state). during the flame end interrupt handling routine, this bit should be cleared by writing 0. 0: lcdc did not generate a flame end interrupt or has been informed that the generated flame end interrupt has completed 1: lcdc has generated a flame end interrupt and not yet been informed that the generated flame end interrupt has completed 9 vsints 0 r/w vsync st art interrupt state indicates the lcdc's vsync start interrupt handling state. this bit is set to 1 at the time a vsync start interrupt is generated. during the vsync start interrupt handling routine, this bit should be cleared by writing 0 to it. 0: lcdc did not generate a vsync start interrupt or has been informed that the generated vsync start interrupt has completed 1: lcdc has generated a vsync start interrupt and has not yet been informed that the generated vsync start interrupt has completed section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 888 of 1458 rej09b0033-0300 bit bit name initial value r/w description 8 veints 0 r/w vsync end interrupt state indicates the lcdc's vsync end interrupt handling state. this bit is set to 1 at the time a vsync end interrupt is generated. during the vsync end interrupt handling routine, this bit should be cleared by writing 0. 0: lcdc did not generate a vsync end interrupt or has been informed that the generated vsync end interrupt has completed 1: lcdc has generated a vsync end interrupt and has not yet been informed that the generated vsync interrupt has completed 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 889 of 1458 rej09b0033-0300 26.3.17 lcdc power management mode register (ldpmmr) ldpmmr controls the power supply circuit that provides power to the lcd module. the usage of two types of power-supply control pins, lcd_vcpwc and lcd_vepwc, and turning on or off the power supply fu nction are selected. bit bit name initial value r/w description 15 14 13 12 onc3 onc2 onc1 onc0 0 0 0 0 r/w r/w r/w r/w lcdc power-on sequence period set the period from lcd_vepwc assertion to lcd_don assertion in the power-on sequence of the lcd module in frame units. specify to the value of (the period) -1. this period is the (c) period in figures 26.4 to 26.7, power-supply control sequence and states of the lcd module. for details on setting this register, see table 26.5, available power-supply control- sequence periods at typical frame rates. (the setting method is common for ona, onb, offd, offe, and offf.) 11 10 9 8 offd3 offd2 offd1 offd0 0 0 0 0 r/w r/w r/w r/w lcdc power-off sequence period set the period from lcd_don negation to lcd_vepwc negation in the power-off sequence of the lcd module in frame units. specify to the value of (the period) -1. this period is the (d) period in figures 26.4 to 26.7, power-supply control sequence and states of the lcd module. 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 vcpe 0 r/w lcd_vcpwc pin enable sets whether or not to enable a power-supply control sequence using the lcd_vcpwc pin. 0: disabled: lcd_vcpwc pin is masked and fixed low 1: enabled: lcd_vcpwc pin output is asserted and negated according to the power-on or power-off sequence section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 890 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 vepe 0 r/w lcd_vepwc pin enable sets whether or not to enable a power-supply control sequence usin g the lcd_vepwc pin. 0: disabled: lcd_vepwc pin is masked and fixed low 1: enabled: lcd_vepwc pin output is asserted and negated according to the power-on or power-off sequence 4 done 1 r/w lcd_don pin enable sets whether or not to enable a power-supply control sequence using the lcd_don pin. 0: disabled: lcd_don pin is masked and fixed low 1: enabled: lcd_don pin output is asserted and negated according to the power-on or power-off sequence 3, 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 lps1 lps0 0 0 r r lcd module power-supply input state indicates the power-supply input state of the lcd module when using the power-supply control function. 0: lcd module power off 1: lcd module power on section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 891 of 1458 rej09b0033-0300 26.3.18 lcdc power-supply sequence period register (ldpspr) ldpspr controls the power supply circuit that provides power to the lcd module. the timing to start outputting the timing signals to the lc d_vepwc and lcd_vcpwc pins is specified. bit bit name initial value r/w description 15 14 13 12 ona3 ona2 ona1 ona0 1 1 1 1 r/w r/w r/w r/w lcdc power-on sequence period set the period from lcd_vcpwc assertion to starting output of the display data (lcd_data) and timing signals (lcd_flm, lcd_cl1, lcd_cl2, and lcd_m_disp) in the power-on sequence of the lcd module in frame units. specify to the value of (the period)-1. this period is the (a) period in figures 26.4 to 26.7, power-supply control sequence and states of the lcd module. 11 10 9 8 onb3 onb2 onb1 onb0 0 1 1 0 r/w r/w r/w r/w lcdc power-on sequence period set the period from starti ng output of the display data (lcd_data) and timing signals (lcd_flm, lcd_cl1, lcd_cl2, and lcd_m_disp) to the lcd_vepwc assertion in the power-on sequence of the lcd module in frame units. specify to the value of (the period)-1. this period is the (b) period in figures 26.4 to 26.7, power-supply control sequence and states of the lcd module. 7 6 5 4 offe3 offe2 offe1 offe0 0 0 0 0 r/w r/w r/w r/w lcdc power-off sequence period set the period from lcd_vepwc negation to stopping output of the display data (lcd_data) and timing signals (lcd_flm, lcd_cl1, lcd_cl2, and lcd_m_disp) in the power-off sequence of the lcd module in frame units. specify to the value of (the period)-1. this period is the (e) period in figures 26.4 to 26.7, power-supply control sequence and states of the lcd module. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 892 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 2 1 0 offf3 offf2 offf1 offf0 1 1 1 1 r/w r/w r/w r/w lcdc power-off sequence period set the period from stopping output of the display data (lcd_data) and timing signals (lcd_flm, lcd_cl1, lcd_cl2, and lcd_m_disp) to lcd_vcpwc negation to in the power-off sequence of the lcd module in frame units. specify to the value of (the period)-1. this period is the (f) period in figures 26.4 to 26.7, power-supply control sequence and states of the lcd module. 26.3.19 lcdc control register (ldcntr) ldcntr specifies start and stop of display by the lcdc. when 1s are written to the don2 bit and the don b it, the lcdc starts display. turn on the lcd module following the sequence set in the ldp mmr and ldcntr. the sequence ends when the lps[1:0] value changes from b'00 to b'11. do not make any action to the don bit until the sequence ends. when 0 is written to the don bit, the lcdc stops display. turn off the lcd module following the sequence set in the ldpmmr and ldcntr. the sequence ends when the lps[1:0] value changes from b'11 to b'00. do not make any action to the don bit until the sequence ends. bit bit name initial value r/w description 15 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 don2 0 r/w display on 2 specifies the start of the lcdc display operation. 0: lcdc is being operated or stopped 1: lcdc starts operation when this bit is read, always read as 0. write 1 to this bit only when starting display. if a value other than 0 is written when starting display, the operation is not guaranteed. when 1 is written to, it resumes automatically to 0. accordingly, this bit does not need to be cleared by writing 0. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 893 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 to 1 ? all 0 r reserved. these bits are always read as 0. the write value should always be 0. 0 don 0 r/w display on specifies the start and st op of the lcdc display operation. the control sequence state can be checked by referencing the lps[1:0] of ldpmmr. 0: display-off mode: lcdc is stopped 1: display-on mode: lcdc operates notes: 1. write h'0011 to ldcnt r when starting display and h'0000 when completing display. data other than h'0011 and h' 0000 must not be written to. 2. setting bit don2 to 1 makes the contents of the palette ram undefined. before writing to the palette ram, set bit don2 to 1. 26.3.20 lcdc user specified inte rrupt control register (lduintr) lduintr sets whether the user specified interrupt is generated, and indicates its processing state. this interrupt is generated at the time when image data which is set by the line number register (lduintlnr) in lcdc is read from vram. this lcdc issues the interrupts (lcdci): user specified interrupt by this register, memory access interrupt by the lcdc interrupt control register (ldintr), and or of vsync interrupt output. this register and lcdc interrupt control register (ldintr) settings affect the interrupt operation independently. bit bit name initial value r/w description 15 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 uinten 0 r/w user spec ified interrupt enable sets whether generate an lcdc user specified interrupt. 0: lcdc user specified in terrupt is not generated 1: lcdc user specified interrupt is generated section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 894 of 1458 rej09b0033-0300 bit bit name initial value r/w description 7 to 1 ? all 0 r reserved. these bits are always read as 0. the write value should always be 0. 0 uints 0 r/w user spec ified interrupt state this bit is set to 1 at the time an lcdc user specified interrupt is gener ated (set state). during the user specified interrupt handling routine, this bit should be cleared by writing 0 to it. 0: lcdc did not generate a user specified interrupt or has been informed that the generated user specified interrupt has completed 1: lcdc has generated a user specified interrupt and has not yet been notified that the generated user specified interrupt has completed note: interrupt processing flow: 1. interrupt signal is input 2. ldintr is read 3. if mints, fints, vsints, or veints is 1, a generated interrupt is memory access interrupt, flame end interrupt, vsync risi ng edge interrupt, or vsync falling edge interrupt. processing for each interrupt is performed. 4. if mints, fints, vsints, or veints is 0, a generated inte rrupt is not memory access interrupt, flame end interrupt, vsync risi ng edge interrupt, or vsync falling edge interrupt. 5. uints is read. 6. if uints is 1, a generated interrupt is a user specified interrupt. process for user specified interrupt is carried out. 7. if uints is 0, a generated inte rrupt is not a user specified interrupt. other processing is performed. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 895 of 1458 rej09b0033-0300 26.3.21 lcdc user specified interrupt line number register (lduintlnr) lduintlnr sets the point where the user specified interrupt is generated. setting is done in horizontal line units. bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 uintln10 0 r/w 9 uintln9 0 r/w 8 uintln8 0 r/w 7 uintln7 0 r/w 6 uintln6 1 r/w 5 uintln5 0 r/w 4 uintln4 0 r/w 3 uintln3 1 r/w 2 uintln2 1 r/w 1 uintln1 1 r/w 0 uintln0 1 r/w user specified interrupt generation line number specifies the line in which the user specified interrupt is generated (line units). set (the number of lines in which interrupts are generated) ? 1 example: generate the user specified interrupt in the 80th line. uintln = 160/2 ? 1 = 79 = h'04f notes: 1. when using th e lcd module with stn/tft display, t he setting value of this register should be equal to lower than the vertical display line number (vdln) in ldvdlnr. 2. when using the lcd module with dstn display, the setting value of this register should be equal to or lower than half the vertical display line number (vdln) in ldvdlnr. the user specified interrupt is generated at the point when the lcdc read the specified piece of image data in lower display from vram. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 896 of 1458 rej09b0033-0300 26.3.22 lcdc memory access inte rval number register (ldlirnr) ldlirnr controls the bu s cycle interval when the lcdc reads vram. when ldlirnr is set to other than h 00, the lcdc does not access vram until the specified number of bus cycles (accessing the external memory or on-chi p registers) has been performed by the cpu/dmac/usbh. when ldlirnr is set to h'00 (initial value), the lcdc accesses the vram, the cpu/dmac/usbh performs one bus cycle, and then the lcdc accessed vram. 16 bursts (when displaying routated image, 4/8/16/32 can be selected.) the number of bus cycles other than lcdc is set to lirn7 to lirn0. (1 to 255 bus cycles) ckio lcdc1 lcdc2 ... ... ... lcdc3 lcdc16 cpu cpu cpu lcdc1 bus cycle bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 to 0 lirn7 to lirn0 all 0 r/w vram read bus cycle interval specifies the number of the cpu/dmac/usbh bus cycles which can be performed during burst bus cycles to read vram by lcdc. h'00: one bus cycle h'01: one bus cycle : h'ff: 255 bus cycles section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 897 of 1458 rej09b0033-0300 26.4 operation 26.4.1 lcd module sizes which can be displayed in this lcdc this lcdc is capable of controlling displays with up to 1024 1024 dots and 16 bpp (bits per pixel). the image data for display is stored in vram, which is shared with the cpu. this lcdc should read the data from vram before display. this lsi has a maximum 32-burst memory read operation and a 2.4-kbyte line buffer, so although a complete breakdown of the display is unlikely, there may be some problems with the display depending on the combination. a recommended size at the frame rate of 60 hz is 320 240 dots in 16 bpp or 640 480 dots in 8 bpp. as a rough standard, the bus occupation ratio shown below should not exceed 40%. bus occupation ratio (%) = overhead coefficient x total number of display pixels ((hdcn + 1) x 8 x (vdln + 1)) x frame rate (hz) x number of colors (bpp) x 100 ckio (hz) x bus width (bit) the overhead coefficient become s 1.375 when the cl2 sdram is connected to a 32-bit data bus and 1.188 when connected to a 16-bit data bus. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 898 of 1458 rej09b0033-0300 figure 26.2 shows the valid display and the retrace period. left border h addressablevideo right border front porch vsync time top border v addressable video bottom border front porch h total time v total time back porch back porch hsync signal vsync signal active video =top/left border + addressable video + bottom/right border total h blank = hsync time + back porch + front porch total v blank = vsync time + back porch + front porch htcn = h total time hdcn = h addressable video hsynp = h addressable video + right border + front porch hsynw = hsync time vtln = v total time cdln = v addressable video vsynp = v addressable video + bottom border + front porch vsynw = vsync time hsync time figure 26.2 valid display and the retrace period 26.4.2 limits on the resolution of rotated displays, burst length, and connected memory (sdram) this lcdc is capable of displaying a landsc ape-format image on a lcd module by rotating a portrait format image for display by 90 degrees. only the numbers of colors for each resolution are supported as shown in tables 26.3 and 26.4. the size of the sdram (the number of column address bits) and its burst length are limited to read the sdram continuously. the number of colors for display, sdram column addresses, and lcdc burst length are shown table 26.3 and 26.4. a monochromatic lcd module is necessary for the display of images in the above monochromatic formats. a color lcd module is n ecessary for the display of images in the above color formats. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 899 of 1458 rej09b0033-0300 table 26.3 limits on the resolution of rotated displays, burst length, and connected memory (32-bit sdram) image for display in memory (x-resolution y- resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 240 320 320 240 8 bits not more than 8 bursts 9 bits not more than 16 bursts 4 bpp (packed) 10 bits ? 8 bits 4 bursts 9 bits not more than 8 bursts 4 bpp (unpacked) 10 bits not more than 16 bursts 8 bits 4 bursts 9 bits not more than 8 bursts monochrome 6 bpp 10 bits not more than 16 bursts 8 bits 4 bursts 9 bits not more than 8 bursts 8 bpp 10 bits not more than 16 bursts 8 bits unusable 9 bits 4 bursts color 16 bpp 10 bits not more than 8 bursts 234 320 320 234 8 bits 4 bursts 9 bits not more than 8 bursts monochrome 6 bpp 10 bits not more than 16 bursts 8 bits unusable 9 bits 4 bursts color 16 bpp 10 bits not more than 8 bursts section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 900 of 1458 rej09b0033-0300 image for display in memory (x-resolution y- resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 80 160 160 80 monochrome 8 bits ? 9 bits ? 2 bpp 10 bits ? 8 bits not more than 16 bursts 9 bits ? 4 bpp (packed) 10 bits ? 8 bits not more than 8 bursts 9 bits not more than 16 bursts 4 bpp (unpacked) 10 bits ? 8 bits not more than 8 bursts 9 bits not more than 16 bursts 6 bpp 10 bits ? color 8 bits not more than 16 bursts 9 bits ? 4 bpp (packed) 10 bits ? 8 bits not more than 8 bursts 9 bits not more than 16 bursts 4 bpp (unpacked) 10 bits ? 8 bits not more than 8 bursts 9 bits not more than 16 bursts 8 bpp 10 bits ? 8 bits 4 bursts 9 bits not more than 8 bursts 16 bpp 10 bits not more than 16 bursts section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 901 of 1458 rej09b0033-0300 image for display in memory (x-resolution y- resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 64 128 128 64 monochrome 1 bpp 8 bits ? 9 bits ? 10 bits ? 2 bpp 8 bits ? 9 bits ? 10 bits ? 8 bits ? 9 bits ? 4 bpp (packed) 10 bits ? 8 bits not more than 16 bursts 9 bits ? 4 bpp (unpacked) 10 bits ? 6 bpp 8 bits not more than 16 bursts 9 bits ? 10 bits ? color 4 bpp 8 bits ? (packed) 9 bits ? 10 bits ? 4 bpp 8 bits not more than 16 bursts (unpacked) 9 bits ? 10 bits ? 8 bpp 8 bits not more than 16 bursts 9 bits ? 10 bits ? note: * specify the data of the number of line specified as burst l ength that can be stored in address of sdram same as that of row. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 902 of 1458 rej09b0033-0300 table 26.4 limits on the resolution of rotated displays, burst length, and connected memory (16-bit sdram) image for display in memory (x-resolution y- resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 240 320 320 240 8 bits not more than 4 bursts 9 bits not more than 8 bursts 4 bpp (packed) 10 bits not more than 16 bursts 8 bits unusable 9 bits 4 bursts monochrome 4 bpp (unpacked) 10 bits not more than 8 bursts 8 bits unusable 9 bits 4 bursts 6 bpp 10 bits not more than 8 bursts 8 bits unusable 9 bits 4 bursts 8 bpp 10 bits not more than 8 bursts 8 bits unusable 9 bits unusable color 16 bpp 10 bits 4 bursts 234 320 320 234 8 bits unusable 9 bits 4 bursts monochrome 6 bpp 10 bits not more than 8 bursts 8 bits unusable color 16 bpp 9 bits unusable 10 bits 4 bursts section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 903 of 1458 rej09b0033-0300 image for display in memory (x-resolution y- resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 80 160 160 80 monochrome 8 bits not more than 16 bursts 9 bits ? 2 bpp 10 bits ? 4 bpp (packed) 8 bits not more than 8 bursts 9 bits not more than 16 bursts 10 bits ? 8 bits 4 bursts 4 bpp (unpacked) 9 bits not more than 8 bursts 10 bits not more than 16 bursts 8 bits 4 bursts 9 bits not more than 8 bursts 6 bpp 10 bits not more than 16 bursts color 8 bits not more than 8 bursts 9 bits not more than 16 bursts 4 bpp (packed) 10 bits ? 8 bits 4 bursts 9 bits not more than 8 bursts 4 bpp (unpacked) 10 bits not more than 16 bursts 8 bits 4 bursts 9 bits not more than 8 bursts 8 bpp 10 bits not more than 16 bursts 8 bits unusable 9 bits 4 bursts 16 bpp 10 bits not more than 8 bursts section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 904 of 1458 rej09b0033-0300 image for display in memory (x-resolution y- resolution) lcd module (x-resolution y-resolution) number of colors for display number of column address bits of sdram burst length of lcdc (ldsmr * ) 64 128 128 64 monochrome 1 bpp 8 bits ? 9 bits ? 10 bits ? 2 bpp 8 bits ? 9 bits ? 10 bits ? 8 bits not more than 16 bursts 9 bits ? 4 bpp (packed) 10 bits ? 8 bits not more than 8 bursts 9 bits not more than 16 bursts 4 bpp (unpacked) 10 bits ? 6 bpp 8 bits not more than 8 bursts 9 bits not more than 16 bursts 10 bits ? color 4 bpp 8 bits not more than 16 bursts (packed) 9 bits ? 10 bits ? 4 bpp 8 bits not more than 8 bursts (unpacked) 9 bits not more than 16 bursts 10 bits ? 8 bpp 8 bits not more than 8 bursts 9 bits not more than 16 bursts 10 bits ? note: * set the data of the number of line specif ied as burst length that can be stored in address of sdram same as that of row. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 905 of 1458 rej09b0033-0300 26.4.3 color palette specification (1) color palette register this lcdc has a color palette which outputs 24 bits of data per entry and is able to simultaneously hold 256 entries. the color palette thus allows the simultaneous display of 256 colors chosen from among 16-m colors. the procedure below may be used to set up color palettes at any time. 1. the palen bit in the ldpalcr is 0 (initial value); normal display operation 2. access ldpalcr and set the palen bit to 1; enter color-palette setting mode after three cycles of peripheral clock. 3. access ldpalcr and confirm that the pals bit is 1. 4. access ldpr00 to ldprff and write the required values to the pald00 to paldff bits. 5. access ldpalcr and clear the palen bit to 0; return to normal display mode after a cycle of peripheral clock. a 0 is output on the lcdc display data output (lcd_data) while the pals bit in ldpalcr is set to 1. 0 7 15 23 31 color monochrome b0 b1 b2 b3 b4 b5 b6 b7 g0 g1 g2 g3 g4 g5 g6 g7 r0 r1 r2 r3 r4 r5 r6 r7 m0 m1 m2 m3 m4 m5 m6 m7 figure 26.3 color-palette data format paldnn color and gradation data should be set as above. for a color display, paldnn[23:16], paldnn[15:8], and paldnn[7:0] respectively hold the r, g, and b data. although the bits paldnn[18:16], paldnn[9:8], and paldnn[2:0] exist, no memory is associated with these bits. paldnn[18:16], paldnn[9:8], and paldnn[2:0] are thus not available for storing palette data. the numbers of valid bits are thus r: 5, g: 6, and b: 5. a 24- bit (r: 8 bits, g: 8 bits, and b: 8 bits) data should, however, be written to the palette-data registers. when the values for paldnn[23:19], paldnn[15:10], or paldnn[7:3] are not 0, 1 or 0 should be written to paldnn[18:16], paldnn[9:8], or paldnn[2:0], respectively. when the values of paldnn[23:19], paldnn[15:10], or paldnn[7:3] are 0, 0s should be written to paldnn[18:16], paldnn[9:8], or paldnn[2:0], respectively. then 24 bits are extended. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 906 of 1458 rej09b0033-0300 grayscale data for a monochromatic display should be set in paldnn[7:3]. paldnn[23:8] are all "don't care". when the value in paldnn[7:3] is not 0, 1s should be written to paldnn[2:0]. when the value in paldnn[7:3] is 0, 0s should be written to paldnn[2:0]. then 8 bits are extended. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 907 of 1458 rej09b0033-0300 26.4.4 data format 1. packed 1bpp (pixel alignment in byte is big endian) [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) msb lsb top left pixel p00 p08 p01 p02 p03 p04 p05 p06 p07 p10 p18 p11 p12 p13 p14 p15 p16 p17 76 5 4 3 2 10 p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display memory 4. packed 1bpp (pixel alignment in byte is little endian) address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) msb lsb p07 p08 p06 p05 p04 p03 p02 p01 p00 p17 p18 p16 p15 p14 p13 p12 p11 p10 76 5 4 3 2 10 display memory 2. packed 2bpp (pixel alignment in byte is big endian) [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) msb lsb p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 76 5 4 3 2 10 display memory 3. packed 4bpp (pixel alignment in byte is big endian) [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) (byte2) msb lsb p00 p01 p02 p03 p10 p11 p12 p13 p04 p05 p14 p15 76 5 4 3 2 10 display memory display pn: put 1-bit data lao: line address offset ?unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn: put 1-bit data lao: line address offset ?unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn=pn[1:0]: put 2-bit data lao: line address offset ?unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn=pn[3:0]: put 4-bit data lao: line address offset ?unused bits should be 0 section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 908 of 1458 rej09b0033-0300 5. packed 2bpp (pixel alignment in byte is little endian) address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) msb lsb p03 p02 p01 p00 p07 p06 p05 p04 p13 p12 p11 p10 p17 p16 p15 p14 76543210 display memory 6. packed 4bpp (pixel alignment in byte is little endian) address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) (byte2) msb lsb p01 p00 p03 p02 p11 p10 p13 p12 p05 p04 p15 p14 76543210 display memory 7. unpacked 4bpp [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) (byte2) msb lsb p00 p01 p10 p11 p02 p12 76543210 display memory 8. unpacked 5bpp [windows ce recommended format] address +00 +01 +02 +03 +lao+00 +lao+01 +lao+02 +lao+03 [bit] (byte0) (byte1) (byte2) msb lsb p00 p01 p10 p11 p02 p12 76543210 display memory top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn = pn[1:0]: put 2-bit data lao: line address offset ?unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn = pn[3:0]: put 4-bit data lao: line address offset ?unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn = pn[3:0]: put 4-bit data lao: line address offset ?unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 display pn = pn[4:0]: put 5-bit data lao: line address offset ?unused bits should be 0 section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 909 of 1458 rej09b0033-0300 9. unpacked 6bpp [windows ce recommended format] address +00 +01 +02 +03 ... +lao+00 +lao+01 +lao+02 +lao+03 ... [bit] (byte0) (byte1) (byte2) msb lsb p00 p01 p10 p11 p02 p12 76543210 ... ... display memory 10. packed 8bpp [windows ce recommended format] address +00 +01 +02 +03 ... +lao+00 +lao+01 +lao+02 +lao+03 ... [bit] (byte0) (byte1) (byte2) msb lsb p00 p01 p10 p11 p02 p12 76543210 ... ... display memory 11. unpacked color 15bpp (rgb 555) [windows ce recommended format] address +00 +02 +04 +06 ... +lao+00 +lao+02 +lao+04 +lao+06 ... [bit] (word0) (word2) (word4) msb lsb p00r p01r p10r p11r p02r p12r p00g p01g p10g p11g p02g p12g p00b p01b p10b p11b p02b p12b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ... ... display memory 12. packed color 16bpp (rgb 565) [windows ce recommended format] address +00 +02 +04 +06 ... +lao+00 +lao+02 +lao+04 +lao+06 ... [bit] (word0) (word2) (word4) msb lsb p00r p01r p10r p11r p02r p12r p00g p01g p10g p11g p02g p12g p00b p01b p10b p11b p02b p12b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ... ... display memory top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 ... ... ... ... display pn = pn[5:0]: put 6-bit data lao: line address offset ?unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 ... ... ... ... display pn = pn[7:0]: put 8-bit data lao: line address offset ?unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 ... ... ... display prr = prr[4.0]. pr 5-bit red data prg = prg[4.0]. pr 5-bit green data prb = prb[4.0]. pr 5-bit blue data pr = (prr, prg, prb). pr 15-bit data lao: line address offset ?unused bits should be 0 top left pixel p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 ... ... ... display prr = prr[4.0]. pr 5-bit red data prg = prg[5.0]. pr 6-bit green data prb = prb[4.0]. pr 5-bit blue data pr = (prr, prg, prb). pr 16-bit data lao: line address offset ?unused bits should be 0 section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 910 of 1458 rej09b0033-0300 26.4.5 setting the display resolution the display resolution is set up in ldhcnr, ldhsynr, ldvdlnr, ldvtlnr, and ldvsynr. the lcd current-alternating period for an stn or dstn display is set by using the ldaclnr. the initial values in these registers are typical settings for vga (640 480 dots) on an stn or dstn display. the clock to be used is set with the ldickr. the lcd module frame rate is determined by the display interval + retrace line inte rval (non-display inte rval) for one screen set in a size related register and the frequency of the clock used. this lcdc has a vsync interrupt function so that it is possible to issue an interrupt at the beginning of each vertical retrace line period (to be exact, at the beginning of the line after the last line of the display). this function is set up by using the ldintr. 26.4.6 power management registers an lcd module normally requires a specific sequen ce for processing to do with the cutoff of the input power supply. settings in ldpmmr, ldpspr, and ldcntr, in conjunction with the lcd power-supply control pins (lcd_vcpwc, lcd_vepwc, and lcd_don), are used to provide processing of power-supply control sequences that suits the requirements of the lcd module. figures 26.4 to 26.7 are summary timing charts for power-supply control sequences and table 26.5 is a summary of available power-supply control sequence periods. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 911 of 1458 rej09b0033-0300 start power supply start power cutoff arbitrary undefined undefined 00b 00b 11b 00b, 11b 00b, 11b (a) 0 frame (b) 1 frame (c) 1 frame (e) 1 frame (d) 1 frame (f) 0 frame lcd module active lcd module stopped lcd module stopped vcpe = on (1) stn, dstn power-supply control vepe = on done = on (in) don register (out) vcpwc pin (out) display data, timing signal (out) lps register (out) vepwc pin (out) lcd_don pin register control sequence figure 26.4 power-supply control se quence and states of the lcd module 00b 00b 11b (a) 0 frame (b) 0 frame (c) 1 frame (d) 1 frame (f) 0 frame (e) 0 frame vcpe = off vepe = off done = on start power supply start power cutoff arbitrary undefined undefined lcd module active lcd module stopped lcd module stopped (internal signal) (internal signal) (2) power-supply control for lcd panels other than stn or dstn (in) don register (out) vcpwc pin (out) display data, timing signal (out) lps register (out) vepwc pin (out) lcd_don pin register control sequence 00b, 11b 00b, 11b figure 26.5 power-supply control se quence and states of the lcd module section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 912 of 1458 rej09b0033-0300 vcpe = on (3) power-supply control for tft panels vepe = on done = off 00b 00b 11b (b) 6 frame (c) 0 frame (d) 0 frame (internal signal) undefined start power supply start power cutoff arbitrary undefined (in) don register (out) vcpwc pin (out) display data, timing signal (out) lps register (out) vepwc pin (out) lcd_ don pin register control sequence lcd module active lcd module stopped lcd module stopped (e) 1 frame (f) 1 frame (a) 1 frame 00b, 11b 00b, 11b figure 26.6 power-supply control se quence and states of the lcd module 00b 00b 11b (a) 0 frame (b) 0 frame (c) 0 frame (d) 0 frame (e) 0 frame (f) 0 frame vcpe = off (4) power supply control for lcd panels other than tft vepe = off done = off (internal signal) (internal signal) (internal signal) start power supply start power cutoff arbitrary undefined undefined (in) don register (out) vcpwc pin (out) display data, timing signal (out) lps register (out) vepwc pin (out) lcd_don pin register control sequence lcd module active lcd module stopped lcd module stopped figure 26.7 power-supply control se quence and states of the lcd module section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 913 of 1458 rej09b0033-0300 table 26.5 available power-supply control- sequence periods at typical frame rates frame rate onx, offx register value 120 hz 60 hz h'f ( ? 1+1)/120 = 0.00 (ms) ( ? 1+1)/60 = 0.00 (ms) h'0 (0+1)/120 = 8.33 (ms) (0+1)/60 = 16.67 (ms) h'1 (1+1)/120 = 16.67 (ms) (1+1)/60 = 33.33 (ms) h'2 (2+1)/120 = 25.00 (ms) (2+1)/60 = 50.00 (ms) h'3 (3+1)/120 = 33.33 (ms) (3+1)/60 = 66.67 (ms) h'4 (4+1)/120 = 41.67 (ms) (4+1)/60 = 83.33 (ms) h'5 (5+1)/120 = 50.00 (ms) (5+1)/60 = 100.00 (ms) h'6 (6+1)/120 = 58.33 (ms) (6+1)/60 = 116.67 (ms) h'7 (7+1)/120 = 66.67 (ms) (7+1)/60 = 133.33 (ms) h'8 (8+1)/120 = 75.00 (ms) (8+1)/60 = 150.00 (ms) h'9 (9+1)/120 = 83.33 (ms) (9+1)/60 = 166.67 (ms) h'a (10+1)/120 = 91.67 (ms ) (10+1)/60 = 183.33 (ms) h'b (11+1)/120 = 100.00 (ms ) (11+1)/60 = 200.00 (ms) h'c (12+1)/120 = 108.33 (ms ) (12+1)/60 = 216.67 (ms) h'd (13+1)/120 = 116.67 (ms ) (13+1)/60 = 233.33 (ms) h'e (14+1)/120 = 125.00 (ms ) (14+1)/60 = 250.00 (ms) ona, onb, onc, offd, offe, and offf are used to set the power-supply control-sequence periods, in units of frames, from 0 to 15. 1 is su btracted from each regist er. h'0 to h'e settings select from 1 to15 frames. th e setting h'f selects 0 frames. actual sequence periods depend on the register values and the frame frequency of the display. the following table gives power-supply control-sequence periods for display frame frequencies used by typical lcd modules. ? when onb is set to h'6 and display's frame frequency is 120 hz the display's frame frequency is 120 hz. 1 frame period is thus 8.33 (ms) = 1/120 (sec). the power-supply input sequence period is 7 frame s because onb setting is subtracted by 1. as a result, the sequence period is 58.33 (ms) = 8.33 (ms) 7. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 914 of 1458 rej09b0033-0300 table 26.6 lcdc operating modes mode function display on (lcdc active) register setting: don = 1 fixed resolution, the format of the data for display is determined by the number of colors, and timing signals are output to the lcd module. display off (lcdc stopped) register setting: don = 0 register access is enabled. fixed resolution, the format of the data for display is determined by the number of colors, and timing signals are not output to the lcd module. table 26.7 lcd module power-supply states (stn, dstn module) state power supply for logic display data, timing signal power supply for high-voltage systems don signal control pin lcd_vcpwc lcd_cl2, lcd_cl1, lcd_flm, lcd_m_disp, lcd_data lcd_vepwc lcd_don operating state supply supply supply supply supply supply supply supply supply (transitional state) supply stopped state section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 915 of 1458 rej09b0033-0300 (tft module) state power supply for logic display data, timing signal power supply for high-voltage systems control pin lcd_vcpwc lcd_cl2, lcd_cl1, lcd_flm, lcd_m_disp, lcd_data lcd_vepwc operating state supply supply supply supply supply (transitional state) supply stopped state the table above shows the states of the power supply, display data, and timing signals for the typical lcd module in its active and stopped states. some of the supply voltages described may not be necessary, because some modules internally generate the power supply required for high- voltage systems from the logic-level power-supply voltage. notes on display-off mode (lcdc stopped): if lcd module power-supply control-sequence processing is in use by the lcdc or the supply of power is cut off while the lcdc is in its display- on mode, normal operatio n is not guaranteed. in the worst case, the connected lcd module may be damaged. 26.4.7 operation fo r hardware rotation operation in hardware-rotation mode is describe d below. hardware-rotation mode can be thought of as using a landscape-format lcd panel instead of a portrait-format lcd panel by placing the landscape-format lcd panel as if it were a portrait-format panel. whether the panel is intended for use in landscape or portrait format is thus no problem. the panel must, however, be within 320 pixels wide. when making settings for hardware rotation, the following five differences from the setting for no hardware rotation must be noted. (the following example is for a display at 8 bpp. at 16 bpp, the amount of memory per dot will be doubled. the image size and register values used for rotation will thus be different.) 1. the image data must be prepared for display in the rotated panel. (if 240 320 pixels will be required after rotation, 240 320 pixel image data must be prepared.) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 916 of 1458 rej09b0033-0300 2. the register settings for the address of the image data must be changed (ldsaru and ldlaor). 3. ldlaor should be power of 2 (when the horizontal width after rotation is 240 pixels, ldlaor should be set to 256). 4. graphics software should be set up for the number 3 setting. 5. ldsaru should be changed to represent the address of the data for the lower-left pixel of the image rather than of the data for the upper-left pixel of the image. picture image ldsaru (start point) ldsaru + ldlaor ? 1 scanning starts from ldsaru. scanning is done from small address to large address of x coordination. ldsaru + ldlaor ldvdlnr ? 1(end point) picture image picture image lcd panel start point end point 1) normal mode figure 26.8 operation for ha rdware rotation (normal mode) for example, the registers have been set up for the display of image data in landscape format (320 240), which starts from ldsaru = 0x0c001000, on a 320 240 lcd panel. the graphics driver software is complete. some changes are required to apply hardware rotation and use the panel as a 240 320 display. if ldlaor is 512, the graphics driver software uses this power of 2 as the offset for the calculation of the addresses of y coordinates in the image data. before setting rot to 1, the image data must be redrawn to suit the 240 320 lcd panel. ldlaor will then be 256 because the size has changed and the graphics driver software must be altered accordingly. section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 917 of 1458 rej09b0033-0300 the point that corresponds to ldsaru moves from the upper left to the lower left of the display, so ldsaru should be changed to 0x0c001000 + 256 * 319. note: hardware rotation allows the use of an lcd panel that has been rotated by 90 degrees. the settings in relation to the lcd panel should match the settings for the lcd panel before rotation. rotation is possible regardle ss of the drawing processing carried out by the graphics driver software. however, the sizes in the image data and address offset values which are managed by the graphics driver software must be altered. picture image ldsaru (start point) ldsaru ? ldlaor (hdcn 8 ? 2) ? 1(end point) scanning starts from ldsaru. scanning is done from large address to small address of y coordination. lcd panel start point end point 2) rotation mode figure 26.9 operation for ha rdware rotation (rotation mode) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 918 of 1458 rej09b0033-0300 26.5 clock and lcd data signal examples dotclk 1) stn monochrome 4-bit data bus module lcd_cl2 lcd_data0 lcd_data1 lcd_data2 lcd_data3 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 lcd_data4 to 15 low figure 26.10 clock and lcd data signal example dotclk 2) stn monochrome 8-bit data bus module lcd_cl2 lcd_data0 lcd_data1 lcd_data2 lcd_data3 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 lcd_data8 to 15 low lcd_data4 lcd_data5 lcd_data6 lcd_data7 b12 b13 b14 b15 figure 26.11 clock and lcd data signal example (stn monochrome 8-bit data bus module) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 919 of 1458 rej09b0033-0300 dotclk 3) stn color 4-bit data bus module lcd_cl2 r0 g0 b0 r1 lcd_data4 to 15 low lcd_data0 lcd_data1 lcd_data2 lcd_data3 g1 b1 r2 g2 b2 r3 g3 b3 r4 g4 b4 r5 g5 b5 r6 g6 b6 r7 g7 b7 r8 g8 b8 r9 g9 b9 r10 g10 b10 r11 g11 b11 b14 r15 g15 b15 r12 g12 b12 r13 g13 b13 r14 g14 figure 26.12 clock and lcd data signal example (stn color 4-bit data bus module) dotclk 4) stn color 8-bit data bus module lcd_cl2 lcd_data0 lcd_data1 lcd_data2 lcd_data3 r0 g0 b0 r1 g1 r2 g2 lcd_data8 to 15 low lcd_data4 lcd_data5 lcd_data6 lcd_data7 b1 b2 r3 g3 r4 g4 b3 r5 b4 g5 b5 r6 g6 r7 g7 b6 b7 r8 g8 b8 r9 g9 r10 g10 b9 b10 r11 g11 r12 g12 b11 r13 b12 g13 b13 r14 g14 r15 g15 b14 b15 figure 26.13 clock and lcd data signal example (stn color 8-bit data bus module) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 920 of 1458 rej09b0033-0300 dotclk 5) stn color 12-bit data bus module lcd_cl2 lcd_data0 lcd_data1 lcd_data2 lcd_data3 r0 g0 b0 r1 g1 r2 g2 lcd_data12 to 15 low lcd_data4 lcd_data5 lcd_data6 lcd_data7 b1 b2 r3 g3 r4 g4 b3 r5 b4 g5 b5 r6 g6 r7 g7 b6 b7 r8 g8 b8 r9 g9 r10 g10 b9 b10 r11 g11 r12 g12 b11 r13 b12 g13 b13 r14 g14 r15 g15 b14 b15 lcd_data8 lcd_data9 lcd_data10 lcd_data11 figure 26.14 clock and lcd data signal example (stn color 12-bit data bus module) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 921 of 1458 rej09b0033-0300 dotclk 6) stn color 16-bit data bus module lcd_cl2 lcd_data0 lcd_data1 lcd_data2 lcd_data3 r0 g0 b0 r1 g1 r2 g2 lcd_data4 lcd_data5 lcd_data6 lcd_data7 b1 b2 r3 g3 r4 g4 b3 r5 b4 g5 b5 r6 g6 r7 g7 b6 b7 r8 g8 b8 r9 g9 r10 g10 b9 b10 r11 g11 r12 g12 b11 r13 b12 g13 b13 r14 g14 r15 g15 b14 b15 lcd_data8 lcd_data9 lcd_data10 lcd_data11 lcd_data12 lcd_data13 lcd_data14 lcd_data15 figure 26.15 clock and lcd data signal example (stn color 16-bit data bus module) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 922 of 1458 rej09b0033-0300 dotclk 7) dstn monochrome 8-bit data bus module lcd_cl2 lcd_data0 lcd_data1 lcd_data2 lcd_data3 ub0 ub1 ub2 ub3 lb0 lb1 lb2 lb3 ub4 ub5 ub6 ub7 lcd_data8 to 15 low lcd_data4 lcd_data5 lcd_data6 lcd_data7 lb4 lb5 lb6 lb7 figure 26.16 clock and lcd data signal example (dstn monochrome 8-bit data bus module) dotclk 8) dstn monochrome 16-bit data bus module lcd_cl2 lcd_data0 lcd_data1 lcd_data2 lcd_data3 lcd_data4 lcd_data5 lcd_data6 lcd_data7 ub0 ub1 ub2 ub4 ub5 ub3 ub7 ub6 lb0 lb1 lb2 lb3 lb5 lb6 lb4 lb7 lcd_data8 lcd_data9 lcd_data10 lcd_data11 lcd_data12 lcd_data13 lcd_data14 lcd_data15 figure 26.17 clock and lcd data signal example (dstn monochrome 16-b it data bus module) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 923 of 1458 rej09b0033-0300 dotclk 9) dstn color 8-bit data bus module lcd_cl2 lcd_data0 lcd_data1 lcd_data2 lcd_data3 ur0 ug0 ub0 ur1 ug1 ur2 ug2 lcd_data8 to 15 low lcd_data4 lcd_data5 lcd_data6 lcd_data7 ub1 ub2 ur3 ug3 ur4 ug4 ub3 ur5 ub4 ug5 ub5 ur6 ug6 ur7 ug7 ub6 ub7 lr0 lg0 lb0 lr1 lg1 lr2 lg2 lb1 lb2 lr3 lg3 lr4 lg4 lb3 lr5 lb4 lg5 lb5 lr6 lg6 lr7 lg7 lb6 lb7 figure 26.18 clock and lcd data signal example (dstn color 8-bit data bus module) dotclk 10) dstn color 12-bit data bbus module lcd_cl2 lcd_data8 lcd_data9 lcd_data10 lcd_data11 ur0 ug0 ub0 ur1 ur2 ug2 ub2 ur3 ur4 ug4 ub4 ur5 ur6 ug6 ub6 ur7 lcd_data12 to 15 low lcd_data4 lcd_data5 lcd_data6 lcd_data7 ug1 ub1 lr0 lg0 ug3 ub3 lr2 lg2 ug5 ub5 lr4 lg4 ug7 ub7 lr6 lg6 lcd_data0 lcd_data1 lcd_data2 lcd_data3 lb0 lr1 lg1 lb1 lb2 lr3 lg3 lb3 lb4 lr5 lg5 lb5 lb6 lr7 lg7 lb7 figure 26.19 clock and lcd data signal example (dstn color 12-bit data bus module) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 924 of 1458 rej09b0033-0300 dotclk 11) dstn color 16-bit data bus module lcd_cl2 lcd_data0 lcd_data1 lcd_data2 lcd_data3 ur0 ug0 ub0 ur1 ug1 ur2 ug2 lcd_data4 lcd_data5 lcd_data6 lcd_data7 ub1 ub2 ur3 ug3 ur4 ug4 ub3 ur5 ub4 ug5 ub5 ur6 ug6 ur7 ug7 ub6 ub7 lcd_data8 lcd_data9 lcd_data10 lcd_data11 lcd_data12 lcd_data13 lcd_data14 lcd_data15 lr0 lg0 lb0 lr1 lg1 lr2 lg2 lb1 lb2 lr3 lg3 lr4 lg4 lb3 lr5 lb4 lg5 lb5 lr6 lg6 lr7 lg7 lb6 lb7 figure 26.20 clock and lcd data signal example (dstn color 16-bit data bus module) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 925 of 1458 rej09b0033-0300 dotclk 13) tft color 16-bit data bus module lcd_cl2 lcd_data0 lcd_data1 lcd_data2 b01 b02 b03 b04 lcd_data3 lcd_data4 lcd_data5 lcd_data6 b05 lcd_data7 lcd_data8 lcd_data9 lcd_data10 lcd_data11 lcd_data12 lcd_data13 lcd_data14 lcd_data15 g00 g01 g02 g03 g04 g05 r01 r02 r03 r04 r05 b11 b12 b13 b14 b15 g10 g11 g12 g13 g14 g15 r11 r12 r13 r14 r15 b21 b22 b23 b24 b25 g20 g21 g22 g23 g24 g25 r21 r22 r23 r24 r25 b31 b32 b33 b34 b35 g30 g31 g32 g33 g34 g35 r31 r32 r33 r34 r35 figure 26.21 clock and lcd data signal example (tft color 16-bit data bus module) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 926 of 1458 rej09b0033-0300 14) 8-bit interface color 640 840 stn-lcd dotclk lcd_cl2 lcd_data0 lcd_data1 lcd_data2 lcd_data3 r0 g0 b0 r1 g1 r2 g2 lcd_data8 to 15 low lcd_data4 lcd_data5 lcd_data6 lcd_data7 b1 b2 r3 g3 r4 g4 b3 r5 b4 g5 b5 r6 g6 r7 g7 b6 b7 r8 g8 b8 r9 g9 r10 g10 b9 g637 b637 r638 g638 r639 g639 b638 b639 r0 g0 b0 r1 g1 r2 g2 b1 lcd_cl1 one horizontal time ( ex. 640 + 8 3 (:3 characters) = 664 dclk) horizontal synchronization position lcd_cl1 valid valid valid valid valid lcd_data one horizontal time lcd_flm 1st line data 2nd line data one frame time (480 cl1) 1st line data lcd_cl2 2nd line data next frame time (480 cl1) no vertical retrace one vertical retrace lcd_cl1 lcd_data valid valid one horizontal time lcd_flm 1st line data 2nd line data one frame time (481 cl1) 1st line data lcd_cl2 2nd line data next frame time (480 cl1) vertical retrace time (one horizontal time) horizontal wave valid valid valid valid 480th line data one horizontal display time (640 dclk) horizontal retrace time horizontal synchronization width 480th line data figure 26.22 clock and lcd data signal example (8-bit interface color 640 480) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 927 of 1458 rej09b0033-0300 15) 16-bit i/f color 640 480 tft-lcd dotclk lcd_ cl2 lcd_data 0 lcd_data 1 lcd_data 2 lcd_data 3 b 0 , 3 b1, 3 b1, 4 b1, 5 b1, 6 b1, 7 g1, 2 b 0, 4 b 0, 5 b 0, 6 b 0, 7 g 0, 2 g 0, 3 g1, 3 g1, 4 g1, 5 g1, 6 g1, 7 r1, 3 g 0, 4 g 0, 5 g 0, 6 g 0, 7 r 0, 3 r 0, 4 r1, 4 r1, 5 r1, 6 r1, 7 r 0, 5 r 0, 6 r 0, 7 lcd_data 4 lcd_data 5 lcd_data 6 lcd_data 7 lcd_ cl1 horizontal retrace time lcd_ cl1 lcd_data valid valid valid one horizontal time lcd_ flm 1st line data 2nd line data one frame time (480 cl1) 1st line data lcd_ cl2 2nd line data 480th line data next frame time (480 cl1) no vertical retrace horizontal wave b639,3 b639,4 b639,5 b639,6 b639,7 g639,2 g639,3 g639,4 g639,5 g639,6 g639,7 r639,3 r639,4 r639,5 r639,6 r639,7 lcd_data 8 lcd_data 9 lcd_data 10 lcd_data 11 lcd_data 12 lcd_data 13 lcd_data 14 lcd_data 15 b0, 3 b0, 4 b0, 5 b0, 6 b0, 7 g0, 2 g0, 3 g0, 4 g0, 5 g0, 6 g0, 7 r0, 3 r0, 4 r0, 5 r0, 6 r0, 7 8dclk 8dclk 8dclk lcd_m_disp lcd_m_ disp horizontal synchronization position one horizontal time ( ex. 640 + 8 3 (:3 characters) = 664 dclk) valid valid valid one horizontal display time (640 dclk) horizontal synchronization width figure 26.23 clock and lcd data signal example (16-bit interface color 640 480) section 26 lcd controller (lcdc) rev. 3.00 jan. 18, 2008 page 928 of 1458 rej09b0033-0300 26.6 usage notes 26.6.1 procedure for halting access to di splay data storage vram (synchronous dram in area 3) follow the procedure below to halt access to vram for storing display data (synchronous dram in area 3). ? procedure for halting access to display data storage vram a. confirm that the lps1 and lps0 bits in ldpmmr are currently set to 1. b. clear the don bit in ldcntr to 0 (display-off mode). c. confirm that the lps1 and lps0 bits in ldpmmr have changed to 0. d. wait for the display time fo r a single frame to elapse. this halting procedure is required before selecti ng self-refreshing for the display data storage vram (synchronous dram in area 3) or making a transition to standby mode or module standby mode. section 27 a/d converter rev. 3.00 jan. 18, 2008 page 929 of 1458 rej09b0033-0300 section 27 a/d converter this lsi includes a 10-bit successive-approximation a/d converter allowing selection of up to four analog input channels. 27.1 features a/d converter features are listed below. ? 10-bit resolution ? four input channels ? high-speed conversion ? minimum conversion time: 15 s per channel ? three conversion modes ? single mode: a/d conversion on one channel ? multi mode: a/d conversion on one to four channels ? scan mode: continuous a/d conversion on one to four channels ? four 16-bit data registers ? a/d conversion results are transferred for storage into 16-bit data registers corresponding to the channels. ? sample-and-hold function ? a/d interrupt requested at the end of conversion ? at the end of a/d conversion, an a/d end interrupt (adi) can be requested. ? a/d conversion can be externally triggered section 27 a/d converter rev. 3.00 jan. 18, 2008 page 930 of 1458 rej09b0033-0300 figure 27.1 shows a block diagram of the a/d converter. 10-bit d/a addra addrb addrd bus interface peripheral data bus analog multi- plexer control circuit successive approxi- mation register + ? comparator sample-and- hold circuit adi interrupt signal av ss an 0 an 1 an 2 an 3 /8 /16 adcsr /4 av cc a/d converter adcr: a/d control register adcsr: a/d control/status register addra: a/d data register a addrb: a/d data register b addrc: a/d data register c addrd: a/d data register d [legend] internal data bus adtrg addrc figure 27.1 block diagram of a/d converter section 27 a/d converter rev. 3.00 jan. 18, 2008 page 931 of 1458 rej09b0033-0300 27.2 input pins table 27.1 summarizes the a/d converter's input pins. av cc and av ss are the power supply inputs for the analog circuits in the a/d converter. av cc also functions as the a/d converter reference voltage pin. table 27.1 pin configuration pin name abbreviation i/o function analog power supply pin avcc input analog power supply and reference voltage for a/d conversion analog ground pin avss input analog ground adc analog input pin 0 an0 input adc analog input pin 1 an1 input adc analog input pin 2 an2 input adc analog input pin 3 an3 input analog inputs adc external trigger pin adtrg input external trigger input for starting a/d conversion section 27 a/d converter rev. 3.00 jan. 18, 2008 page 932 of 1458 rej09b0033-0300 27.3 register descriptions the a/d converter has the following registers. ? a/d data register a (addra) ? a/d data register b (addrb) ? a/d data register c (addrc) ? a/d data register d (addrc) ? a/d control/status register (adcsr) 27.3.1 a/d data registers a to d (addra to addrd) the four a/d data registers (addra to addrd) are 16-bit read-only registers that store the results of a/d conversion. an a/d conversion produces 10-bit data, which is transferred for storage into the a/d data register corresponding to the selected channel. the upper 8 bits of th e result are stored in the upper byte (bits 15 to 6) of the a/d data register. bits 5 to 0 of an a/d data register are always read as 0. table 27.2 indicates the pairings of analog input channels and a/d data registers. each addr is initialized to h'0000 by a reset and the module standby function and in standby mode. table 27.2 analog input cha nnels and a/d data registers analog input channel a/d data register an0 addra an1 addrb an2 addrc an3 addrd section 27 a/d converter rev. 3.00 jan. 18, 2008 page 933 of 1458 rej09b0033-0300 27.3.2 a/d control/status registers (adcsr) adcsr is a 16-bit readable/writable register that selects the mode and controls the a/d converter. adcsr is initialized to h'0000 by a reset and the module standby function and in standby mode. bit bit name initial value r/w description 15 adf 0 r/(w) * a/d end flag indicates the end of a/d conversion. [clearing conditions] (1) cleared by reading adf while adf = 1, then writing 0 to adf (2) cleared when dmac is activated by adi interrupt and addr is read [setting conditions] single mode: a/d conversion ends multi mode: a/d conversion ends cycling through the selected channels scan mode: a/d conversion ends cycling through the selected channels note: clear this bit by writing 0. 14 adie 0 r/w a/d interrupt enable enables or disables the interrupt (adi) requested at the end of a/d conversion. set the adie bit while a/d conversion is not being made. 0: a/d end interrupt request (adi) is disabled 1: a/d end interrupt request (adi) is enabled section 27 a/d converter rev. 3.00 jan. 18, 2008 page 934 of 1458 rej09b0033-0300 bit bit name initial value r/w description 13 adst 0 r/w a/d start starts or stops a/d conversion. the adst bit remains set to 1 during a/d conversion. 0: a/d conversion is stopped 1: single mode: a/d conversion starts; adst is automatically cleared to 0 when conversion ends on all selected channels multi mode: a/d conversion starts; when conversion is complet ed cycling through the selected channels, adst is automatically cleared to 0 scan mode: a/d conversion starts and continues; a/d conversion is continuously performed until adst is cleared to 0 by software, by a reset, or by a transition to standby mode 12 dmasl 0 r/w dmac select selects an interrupt due to the end of a/d conversion or activation of the dmac. set the dmasl bit while a/d conversion is not being made. 0: an interrupt by the end of a/d conversion is selected 1: activation of the dmac by the end of a/d conversion is selected always read as 0 when each register of a/d is read through cpu. 11 10 ? ? 0 0 r r trigger enable enables or disables a/d conversion by external trigger input. 00: disables a/d conversion by external trigger input 01: reserved (setting prohibited) 10: reserved (setting prohibited) 11: a/d conversion is start ed at the rising edge of a/d conversion trigger pin ( adtrg ) 9 8 ? ? 0 0 r r reserved these bits are always read as 0. the write value should always be 0. section 27 a/d converter rev. 3.00 jan. 18, 2008 page 935 of 1458 rej09b0033-0300 bit bit name initial value r/w description 7 6 cks1 cks0 0 1 r/w r/w clock select selects the a/d conversion time. clear the adst bit to 0 before changing the conversion time. 00: conversion time = 151 states (maximum) 01: conversion time = 285 states (maximum) 10: conversion time = 545 states (maximum) 11: reserved (setting prohibited) when p 16.5 mhz, do not set cks1 and cks0 to 00. if set, a sufficient conversion time is not assured, causing inaccurate conversion or abnormal operation. 5 4 multi1 multi0 0 0 r/w r/w selects single mode, multi mode, or scan mode. 00: single mode 01: reserved (setting prohibited) 10: multi mode 11: scan mode 3 ? 0 r reserved these bits are always read as 0. the write value should always be 0. 2 1 0 ch2 ch1 ch0 0 0 0 r/w r/w r/w channel select 2 to 0 (ch2 to ch0) these bits and the multi bi t select the analog input channels. clear the adst bit to 0 before changing the channel selection. single mode multi mode or scan mode 000: an0 an0 001: an1 an0, an1 010: an2 an0 to an2 011: an3 an0 to an3 100: reserved (setting prohibited) 101: reserved (setting prohibited) 110: reserved (setting prohibited) 111: reserved (setting prohibited) note: * only 0 can be written to clear the flag. section 27 a/d converter rev. 3.00 jan. 18, 2008 page 936 of 1458 rej09b0033-0300 27.4 operation the a/d converter operates by su ccessive approximations with 10 -bit resolution. it has three operating modes: single mode, multi mode, and scan mode. 27.4.1 single mode single mode should be selected when only one a/d conversion on one channel is required. a/d conversion starts when the adst bit in the a/d control/status register (adcsr) is set to 1 by software. the adst bit remains set to 1 during a/d conversion and is automatically cleared to 0 when conversion ends. when conversion ends the adf bit in adcsr is set to 1. if the adie bit in adcsr is also set to 1 and dmasl is cleared to 0, an adi interrupt is requested at this time. to clear the adf flag to 0, first read adf, then write 0 to adf. when the mode or analog input channel must be switched during a/d conversion, to prevent incorrect operation, first clear the adst bit to 0 to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the mode or channel is changed. typical operations when channel 1 (an1) is selected in single mode are described next. figure 27.2 shows a timing diagram for th is example. 1. start the clock supply to the adc module (clear the mstp33 bit in stbcr3 to 0) to run the adc module. 2. single mode is selected (multi = 0), input channel an1 is selected (ch2 = ch1 = 0, ch0 = 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). 3. when a/d conversion is completed, the result is transferred into addrb. at the same time the adf flag is set to 1, the adst bit is cl eared to 0, and the a/d converter becomes idle. 4. when adf = 1, adie = 1, and dmasl = 0, an adi interrupt is requested. 5. the a/d interrupt handling routine starts. 6. the routine reads adf, then writes 0 to the adf flag. 7. the routine reads and processes the conversion result (addrb = 0). 8. execution of the a/d interrupt handling routine ends. 9. stop the clock supply to th e adc module (set the mstp33 bi t in stbcr3 to 1) to place the adc in the module standby state. section 27 a/d converter rev. 3.00 jan. 18, 2008 page 937 of 1458 rej09b0033-0300 channel 0 (an0) operating adie adst adf channel 1 (an1) operating channel 2 (an2) operating channel 3 (an3) operating addra addrb addrc addrd waiting waiting waiting waiting waiting waiting a/d conversion starts set set set clear* clear a/d conversion result 1 a/d conversion result 2 read result read result a/d conversion 1 a/d conversion result 2 note: vertical arrows ( ) indicate instruction execution by software. figure 27.2 example of a/d converter op eration (single mode, channel 1 selected) section 27 a/d converter rev. 3.00 jan. 18, 2008 page 938 of 1458 rej09b0033-0300 27.4.2 multi mode multi mode should be selected when performing a/d conversions on one or more channels. when the adst bit in the a/d conversion control/status register (adcsr) is set to 1 by software, a/d conversion starts on the first channel (an0). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1) starts immediately. when a/d conversions end on the se lected channels, the adst bit is cleared to 0. the conversion results are transferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel selection must be changed during a/d conversion, to prevent incorrect operation, first clear the adst b it to 0 to halt a/d conversion. after making the necessary changes, set the adst bit to 1. a/d conv ersion will start again fr om the first channel in the group. the adst bit can be set at the same tim e as the mode or channel selection is changed. typical operations when three ch annels (an0 to an2) are selected in scan mode are described next. figure 27.3 shows a timing diagram for this example. 1. start the clock supply to the adc module (clear the mstp33 bit in stbcr3 to 0) to run the adc module. 2. multi mode is selected (multi = 1), analog input channels an0 to an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 3. when a/d conversion of the first channel (an0 ) is completed, the result is transferred into addra. 4. next, conversion of the second channel (an1) starts automatically. 5. conversion proceeds in the same way through the third channel (an2). 6. when conversion of all selected channels (an0 to an2) is completed, the adf flag is set to 1 and adst bit is cleared to 0. if the adie bit is set to 1, an adi interrupt is requested at this time. 7. stop the clock supply to th e adc module (set the mstp33 bi t in stbcr3 to 1) to place the adc in the module standby state. section 27 a/d converter rev. 3.00 jan. 18, 2008 page 939 of 1458 rej09b0033-0300 channel 0 (an0) operating adst adf channel 1 (an1) operating channel 2 (an2) operating channel 3 (an3) operating addra addrb addrc addrd waiting waiting waiting waiting set clear clear a/d conversion result 2 waiting waiting a/d conversion result 3 a/d conversion 1 waiting a/d conversion result 1 transfer a/d conversion 3 a/d conversion a/d conversion 2 note: vertical arrows ( ) indicate instruction execution by software. figure 27.3 example of a/d co nverter operation (multi mode, channels an0 to an2 selected) section 27 a/d converter rev. 3.00 jan. 18, 2008 page 940 of 1458 rej09b0033-0300 27.4.3 scan mode scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit in the a/d control/status register (adcsr) is set to 1 by software, a/d conversion starts on the first channel (an0). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the a/d data registers corresponding to the channels. when the mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 to halt a/d conversion. after making the necessary changes, set the adst bit to 1. a/d conv ersion will start again fr om the first channel in the group. the adst bit can be set at the same tim e as the mode or channel selection is changed. typical operations when three ch annels (an0 to an2) are selected in scan mode are described next. figure 27.4 shows a timing diagram for this example. 1. start the clock supply to the adc module (clear the mstp33 bit in stbcr3 to 0) to run the adc module. 2. scan mode is selected, anal og input channels an0 to an2 ar e selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 3. when a/d conversion of the first channel (an0 ) is completed, the result is transferred into addra. 4. next, conversion of the second channel (an1) starts automatically. 5. conversion proceeds in the same way through the third channel (an2). 6. when conversion of all the selected channels (a n0 to an2) is completed, the adf flag is set to 1 and conversion of the first channel (an0) starts again. if the adie bit is set to 1, an adi interrupt is requested at this time. 7. steps 3 to 5 are repeated as long as the ads t bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. 8. stop the clock supply to th e adc module (set the mstp33 bi t in stbcr3 to 1) to place the adc in the module standby state. section 27 a/d converter rev. 3.00 jan. 18, 2008 page 941 of 1458 rej09b0033-0300 adst adf channel 0 (an0) operating channel 1 (an1) operating channel 2 (an2) operating channel 3 (an3) operating addra addrb addrc addrd waiting waiting waiting waiting waiting waiting waiting waiting waiting transfer a/d conversion 1 a/d conversion 4 a/d conversion 2 a/d conversion 3 a/d conversion result 1 a/d conversion result 4 a/d conversion result 2 a/d conversion result 3 clear * clear * set * continuous a/d conversion a/d conversion 5 notes: * vertical arrows ( ) indicate instruction execution by software. figure 27.4 example of a/d converter operation (scan mode, channels an0 to an2 selected) section 27 a/d converter rev. 3.00 jan. 18, 2008 page 942 of 1458 rej09b0033-0300 27.4.4 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then star ts conversion. figure 27.5 shows the a/d conversion timing. table 27.3 indicates the a/d conversion time. as indicated in figure 27.5, th e a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the wr ite access to adcsr. th e total conversion time therefore varies w ithin the ranges indicated in table 27.3. in multi mode and scan mode, the values given in table 27.3 apply to the first conversion. in the second and subsequent conversions the conversion the conversion time is fixed at 512 states (fixed) when cks1 = 1 and cks0 = 0, 256 states (fixed) when cks1 = 0 and cks0 = 1, and 128 states (fixed) when cks1 = 0 and cks0 = 0. p write signal adf * 1 input sampling timing t d a/d conversion start delay t spl input sampling time t conv a/d conversion time notes: 1. adcsr write cycle 2. adcsr address address * 2 t d t spl t conv figure 27.5 a/d conversion timing section 27 a/d converter rev. 3.00 jan. 18, 2008 page 943 of 1458 rej09b0033-0300 table 27.3 a/d conversio n time (single mode) cks1 = 1, cks0 = 0 cks1 = 0, cks0 = 1 cks1 = 0, cks0 = 0 symbol min. typ. max. min. typ. max. min. typ. max. a/d conversion start delay t d 18 ? 21 10 ? 13 6 ? 9 input sampling time t spl ? 129 ? ? 65 ? ? 33 ? a/d conversion time t conv 535 ? 545 275 ? 285 141 ? 151 note: values in the table are numbers of states (t cyc ) for p . 27.4.5 external tr igger input timing the a/d conversion can also be started by the external trigger input. the external trigger input is enabled at the adtrg pin when bits trge1 and trge0 in a/d control register (adcr) are set to 1. the falling edge of adtrg input pin sets the adst bit in the a/d control/status register (adcsr) to 1, and then a/d conversion is started. other operations are the same as when the adst bit is set to 1 by software, regardless of the conversion mode. figure 27.6 shows the timing. p adtrg external trigger signal adst a/d converter figure 27.6 external trigger input timing section 27 a/d converter rev. 3.00 jan. 18, 2008 page 944 of 1458 rej09b0033-0300 27.5 interrupts the a/d converter generates an interrupt (adi) at the end of a/d conversion. the adi interrupt request can be enabled or disabled by the adie bit on the dmasl bit in adcsr. 27.6 definitions of a/d conversion accuracy the a/d converter compares an analog value input from an analog input channel with its analog reference value and converts it to 10-bit digital data. the absolute accuracy of this a/d conversion is the deviation between the input analog value and the output digital value. it includes the following errors: ? offset error ? full-scale error ? quantization error ? nonlinearity error these four error quantities are explained below with reference to figure 27.7. in the figure, the 10 bits of the a/d converter have been simplified to 3 bits. offset error is the deviation between actual and ideal a/d conversion ch aracteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (000 in the figure) to 000000001 (001 in the figure)(figure 27.7, item (1)). full-scale error is the deviation between actual and ideal a/d conversion characteristics when the digital output value changes from the 1111111110 (110 in the figure) to the maximum 1111111111 (111 in the figure)(figure 27.7, item (2)). quantization error is the intrinsic error of the a/d converter and is expressed as 1/2 lsb (figure 27.7, item (3)). nonlinearity error is the de viation between actual an d ideal a/d conversion characteristics between zero voltage and full-scale voltage (figure 27.7, item (4)). note that it does not include offset, full-scal e, or quantization error. section 27 a/d converter rev. 3.00 jan. 18, 2008 page 945 of 1458 rej09b0033-0300 111 110 101 100 011 010 001 000 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs analog input voltage fs: full-scale voltage (3) quantization error ideal a/d conversion characteristic (4) nonlinearity error ideal a/d conversion characteristic actual a/d convertion characteristic (2) full-scale error digital output analog input voltage (1) offset error fs digital output figure 27.7 definitions of a/d conversion accuracy section 27 a/d converter rev. 3.00 jan. 18, 2008 page 946 of 1458 rej09b0033-0300 27.7 usage notes 27.7.1 notes on a/d conversion (1) notes on clearing the adf bit in the adcsr register problem : even though the adcsr.adf bit has been read as 1 and 0 was then written to the adf bit, the adf bit has no t been cleared to 0. condition : this problem arises when reading of the adf bit coincides with setting of the bit to 1 upon the end of a/d conversion. avoiding the problem : follow any of procedures (a), (b), or (c) below. (a) ensure that setting of the adf bit to 1 upon the end of a/d conversion does not coincide with reading of the adf bit. for example, read the adf bit as 1 and then write 0 to the bit during processing of the a/d conversion end interrupt (adi) that is generated at the end of a/d conversion (when the adf is set to 1). (b) if the adf bit has not been cleared, repeat the operation of reading it as 1 and then writing 0 to it. (c) initialize the adc and clear the adf bit by placing the adc in the module standby state. (2) notes on a/d conversion in scan mode problem: a/d conversion in scan mode is not stopped by clearing the adcsr.adst bit (to 0). condition: this problem arises when 0 is written to the adst bit in adcsr to stop a/d conversion while a/d conversion in scan mode is in progress. avoiding the problem: place the adc in module standby state after cleari ng the adst bit (to 0). placing the adc in the module standby state initializes the adc and stops a/d conversion. when further a/d conversion is required, restart a/d conversion after releasing the adc from the module standby state. (3) notes on transferring the result of a/d conversion by the dmac problem: an incorrect superfluous dma transfer is in cluded before dma tran sfer of the correct result of a/d conversion. section 27 a/d converter rev. 3.00 jan. 18, 2008 page 947 of 1458 rej09b0033-0300 condition: the problem arises in the following cases. also see the table below: (a) in single/multi mode the problem arises when a/d conversion is started while the setting of the adcsr.dmasl bit is 1, after having proceeded while the setting of the dmasl bit was 0 and then stopped. (b) in scan mode the problem arises when a/d conversion is started while the setting of the adcsr.dmasl bit is 1, after having proceeded and stopped. table 27.4 conditions for th e method of transferring re sults of a/d conversion and inclusion of s uperfluous dma in single/multi mode in scan mode the next conversion current conversion dmasl = 0 dmasl = 1 dmasl = 0 dmasl = 1 dmasl = 0 normal faulty normal faulty single mode/ multi mode dmasl = 1 normal normal normal normal dmasl = 0 normal faulty normal faulty scan mode dmasl = 1 normal faulty normal faulty avoiding the problem: follow either of procedures (a) or (b) below. (a) after a/d conversion has stopped, initialize the adc by placing it in the module standby state. start the next round of a/d conversio n after releasing the adc from the module standby state. (b) operation under the following conditions ensures that the problem will not arise. ? in single/multi mode transfer when dmasl = 0 transfer when dmasl = 0 transfer when dmasl = 1 transfer when dmasl = 1 ? in scan mode transfer when dmasl = 0 transfer when dmasl = 0 section 27 a/d converter rev. 3.00 jan. 18, 2008 page 948 of 1458 rej09b0033-0300 27.7.2 notes on a/d conversion-end int errupt and dma transfer generation of an interrupt or activation of the dmac upon the end of a/d conversion is only allowed once per end of a/d conversion. the conditions for the end of a/d conversion are the same as the setting conditions of the adf bit of adcsr. according to the table below, a/d conversion va lue should be transferred by dma transfer (in cycle steal mode), with the co rresponding conversion mode and number of channels for conversion. conversion mode number of channels for conversion data size transfer size for dmac single mode 1 1 word word 1 1 word word 2 2 words longword 3 3 words 16 bytes multi mode or scan mode 4 4 words 16 bytes 27.7.3 allowable signal-source impedance for the analog input design of this lsi, conversion accuracy is guaranteed for an input signal with signal-source impedance of 5 k ? or less. the specification is for charging input cap acitance of the sample and hold circuit of the a/d converter within sampling time. when the output impedance of the sensor exceeds 5 k ? , conversion accuracy is not guaranteed due to insufficient charging. if large external capacitance is set at conversion in single mode, signal-source impedance is ignored since input load is only internal input resistance of 3 k ? . however, an analog signal with large differential coefficient (5 mv/ s or greater) cannot be followed up because of a low-pass filter (figure 27.8). when converting high-speed analog signals or converting in scan mode, insert a low-impedance buffer. section 27 a/d converter rev. 3.00 jan. 18, 2008 page 949 of 1458 rej09b0033-0300 27.7.4 influence to absolute accuracy by adding capacitance, absolute accuracy may be degraded if noise is on gnd because there is coupling with gnd. therefore, co nnect electrically stable gnd su ch as avss to prevent absolute accuracy from being degraded. a filter circuit must not interfere with digital signals, or must not be an antenna on a mounting board. 20 pf c in = 15 pf 3 k ? to 5 k ? output impedance of sensor sensor input this lsi lowpass filter (c = 0.1 f) equivalent circuit of a/d converter figure 27.8 analog input circuit example 27.7.5 setting analog input voltage operating the chip in excess of the following voltage range may result in damage to chip reliability. during a/d conversion, the voltages (vann) input to the analog input pins ann should be in the range av ss vann av cc (n = 0 to 3). 27.7.6 notes on board design in designing a board, separate digital circuits and analog circuits. do not intersect or locate closely signal lines of a digital circuit and an analog circuit. an analog circuit may malfunction due to induction, thus affecting a/d conversion values. separate analog input pins (an0 to an3) and the analog power voltage (avcc) from digital circuits with analog ground (avss). connect analog ground (avss) to one point of stable ground (vss) on the board. section 27 a/d converter rev. 3.00 jan. 18, 2008 page 950 of 1458 rej09b0033-0300 27.7.7 notes on coun termeasures to noise connect a protective circuit between avcc and avss, as shown in figure 27.9, to prevent damage of analog input pins (an0 to an3) due to abnor mal voltage such as excessive serge. connect a bypass capacitor that is connected to avcc and a cap acitor for a filter that is connected to an0 to an3 to avss. when a capacitor for a filter is connected, input currents of an0 to an3 are averaged, may causing errors. if a/d conversion is frequently performed in scan mode, voltages of analog input pins cause errors when a current that is charged/discharged for capacitance of a sample & hold circuit in the a/d converter is hi gher than a current that is input through input impedance (rin). therefore, determine a ci rcuit constant carefully. 0.01 f 10 f av cc (a/d) an0 to an3 av ss (a/d) this lsi * 1 100 ? 0.1 f notes: * 1 values are for reference. r in * 2 * 2 r in is input impedance. figure 27.9 example of analog input protection circuit table 27.5 analog input pin ratings item min max unit analog input capacitance ? 20 pf allowable signal-source impedance ? 5 k ? section 27 a/d converter rev. 3.00 jan. 18, 2008 page 951 of 1458 rej09b0033-0300 20 pf an0 to an3 3 k ? to a/d converter note: values are for reference. figure 27.10 analog input pin equivalent circuit section 27 a/d converter rev. 3.00 jan. 18, 2008 page 952 of 1458 rej09b0033-0300 section 28 d/a converter (dac) rev. 3.00 jan. 18, 2008 page 953 of 1458 rej09b0033-0300 section 28 d/a converter (dac) this lsi incorporates a two-channel d/a co nverter (dac) with the following features. 28.1 features ? 8-bit resolution ? two output channels ? conversion time: max. 10 s (w hen load capacitance is 20 pf) ? output voltage: 0 v to avcc (analog power supply) figure 28.1 shows the block diagram for the dac. [legend] dacr: dadr0: dadr1: avcc: avss: dao0: dao1: d/a control register d/a data register 0 d/a data register 1 analog power supply analog ground analog output 0 analog output 1 analog i/o buffer dadr0 avcc avss da0 da1 dao1 dao0 dadr1 dacr 8-bit d/a converter d/a converter circuit internal peripheral clock (p ) control circuit peripheral data bus module data bus bus interface figure 28.1 block di agram of d/a converter section 28 d/a converter (dac) rev. 3.00 jan. 18, 2008 page 954 of 1458 rej09b0033-0300 28.2 input/output pins table 28.1 summarizes the input/output pins used by the d/a converter. table 28.1 pin configuration pin name i/o function avcc ? analog block power supply and d/a conversion reference voltage avss ? analog block ground da0 output channel 0 analog output da1 output channel 1 analog output 28.3 register descriptions the d/a converter has the following registers. refer to section 37, list of registers, for more details on the addresses and states of these registers in each operating mode. ? d/a data register 0 (dadr0) ? d/a data register 1 (dadr1) ? d/a control register (dacr) 28.3.1 d/a data registers 0 and 1 (dadr0, dadr1) dadr0 and dadr1 are 8-bit readable/writable registers that store data for d/a conversion. when the d/a output enable bits (daoe1, daoe0) of the da control register (dacr) are set to 1, the contents of the d/a data register are converted and output to analog output pins (da0, da1). the d/a data register is initialized to h'00 at reset. note that the d/a data register is not initialized upon entering the software standby, module standby, or hardware standby mode. bit bit name initial value r/w description 7 to 0 ? h'00 r/w 8-bit registers that store data for d/a conversion. section 28 d/a converter (dac) rev. 3.00 jan. 18, 2008 page 955 of 1458 rej09b0033-0300 28.3.2 d/a control register (dacr) the dacr register is an 8-bit readable/writable register that controls d/a converter operation. the dacr is initialized to h'3f at reset. note that the dacr is not initialized in software standby, module standby, or hardware standby mode. bit bit name initial value r/w description 7 daoe1 0 r/w controls d/a conversion for channel 1 and analog output. 0: d/a conversion for channel 1 and analog output (da1) are disabled 1: d/a conversion for channel 1 and analog output (da1) are enabled 6 daoe0 0 r/w controls d/a conversion for channel 0 and analog output. 0: d/a conversion for channel 0 and analog output (da0) are disabled 1: d/a conversion for channel 0 and analog output (da0) are enabled 5 to 0 ? all 1 r reserved these bits are always read as 1. the write value should always be 1. if 0 is written to these bits, correct operation cannot be guaranteed. section 28 d/a converter (dac) rev. 3.00 jan. 18, 2008 page 956 of 1458 rej09b0033-0300 28.4 operation the d/a converter incorporates two d/a channels that can operate individually. the d/a converter executes d/a conversion while analog output is enabled by the d/a control register (dacr). if the d/a data registers (dad r0 and dadr1) are modi fied, the d/a converter immediately initiates the new data conversion. when the daoe1 and daoe0 bits in the dacr register are set to 1, d/a conversion results are output. an example of d/a conversion for channel 0 is shown below. the operation timing is shown in figure 28.2. 1. write conversion data to dadr0. 2. when the daoe0 bit in dacr is set to 1, d/a conversion starts. the results are output after the conversion has ended. the output value will be (dadr0 contents/256) avcc. the conversion results are output continuously until dadr0 is modified or the daoe0 bit is cleared to 0. 3. when d/a data register 0 (dmdr0) is modified, the convers ion starts again. the results are output after the conversion has ended. 4. when the daoe0 bit is cleared to 0, analog output is disabled (high-impedance state). dadr0 address bus p dadr0 write cycle dadr0 write cycle dacr write cycle dacr write cycle daoe0 da0 [legend] t dconv : d/a conversion time high impedance state conversion result (1) conversion result (2) conversion data (1) conversion data (2) t dconv t dconv figure 28.2 d/a converter operation example section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 957 of 1458 rej09b0033-0300 section 29 pc card controller (pcc) the pc card controller (pcc) controls the external buffer, interrupts, and exclusive ports of the pc card interface to be connected to this lsi. us ing the pcc enables two slots of pc cards that conform to the pcmcia rev. 2.1/jeida ver. 4.2 standard to be easily connected to this lsi. 29.1 features ? as a pc card interface to be connected to physi cal area 6, an ic memory card interface and an i/o card interface are supported. ? outputs control signals for the external buffer ( pcc_drv ). ? supports a preemptive operating system by switching attribut e memory, common memory, and i/o space by using addresses. ? provides a segment bit (an address bit for the pc card) for common memory, enabling access to a 64-mbyte space fully confor ming to pcmcia specifications. ? disables the pcc operation and supports only a bu s interface of a pc car d interface (by using the p0use bit of pcc0gcr). section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 958 of 1458 rej09b0033-0300 figure 29.1 shows a block diagram of the pc card controller. pc card controller (pcc) area 6 pc card interface signals area 6 internal interrupt signals pcc_wait pcc_reset pcc_drv pcc_iois16 (wp) pcc_rdy( ireq ) pcc_bvd1 ( stschg ) pcc_bvd2 (spkr) pcc_cd1 pcc_cd2 pcc_vs1 pcc_vs2 pcc_reg battery dead software interrupt rdy/bsy signal change internal data bus card detection signal change internal bus control signal stschg signal change area 6: an ic memory card interface and an i/o card interface are supported. area 6 register (0:3) and register control register selection bus interface interrupt controller battery warning ireq signal figure 29.1 pc card controller block diagram section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 959 of 1458 rej09b0033-0300 29.1.1 pcmcia support this lsi supports an interface based on pcmcia specifications for physi cal areas 6. interfaces supported are the ic memory card interface and i/o card interface defined in the pcmcia rev. 2.1/jeida ver. 4.2 standard. both the ic me mory card interface and i/o card interface are supported in area 6. table 29.1 features of the pcmcia interface item feature access random access data bus 8/16 bits memory type masked rom, otprom, eprom, eeprom, flash memory, sram common memory capacity maximum 64 mbytes (sup ports full pcmcia specifications by using a segment bit (an address bit for the pc card)) attribute memory capacity maximum 32 mbytes i/o space capacity maximum 32 mbytes others dynamic bus sizing for i/o bus width * the pcmcia interface can be accessed from the address- conversion region and non-address-conversion region. note: * dynamic bus sizing for the i/o bus width is supported only in little-endian mode. this lsi can directly access 32- and 64-mbyte phys ical areas in a 64-mbyte memory space and an i/o space of the pc card (continuo us 32/16-mbyte area mode). this lsi provides a segment bit (an address bit for the pc card) in the general control register for area 6 to support a common memory space with fu ll pcmcia specifications (64 mbytes). (1) continuous 32-mbyte area mode setting 0 (initial value) in bit 3 (p0mmod) of the general control register enables the continuous 32-mbyte area mode. in this mode, the attri bute memory space and i/o memory space are 32 mbytes and the common memory space is 64 mbyt es. in the common memory space, set 1 in bit 2 (p0pa25) of the general control register to access an address of more than 32 mbytes. by this operation, 1 is output to a25 pin, enabling an address space of more than 32 mbytes to be accessed. when an address of 32 mbytes or less is accessed, set 0 in popa25. this bit does not affect access to attribute memory space or i/o memory space. figure 29.2 shows the relationshi p between the memory space of th is lsi and the memory and i/o spaces of the pc card in the continuous 32-mbyte area mode. memory space and i/o space are supported in area 6. section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 960 of 1458 rej09b0033-0300 in area 6, set 1 in bit 0 (p0reg) of the genera l control register to access the common memory space of the pc card, and set 0 in bit 0 to access th e attribute memory space (initial value: 0). by this operation, the set value is output to pcc_reg pin, enabling any space to be accessed. when the i/o space is accessed in area 6, the output of pcc_reg pin is always 0 regardless of the value of bit 0 (p0reg). see the register descriptions in section 29.3, register descriptions for details of register settings. this lsi memory space pc card address space general control register bit settings p0mmod = 0 p0pa24 = x p0pa25 = x p0reg = 0 (attribute) p0pa25 = 0 p0reg = 1 (common memory) p0pa25 = 0 p0reg = 1 (common memory) p0pa25 = x p0reg = x pin pccreg is always 0 attribute memory/ common memory 32 mbytes i/o space 32 mbytes p0reg p0pa25 h'18000000 h'1a000000 x: don't care area 6 32 mbytes i/o space common mermoy 32 mbytes total 64 mbytes attribute memory figure 29.2 continuous 32-mbyte area mode section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 961 of 1458 rej09b0033-0300 (2) continuous 16-mbyte area mode setting 1 in bit 3 (p0mmod) of the general control register enables the continuous 16-mbyte area mode. in this mode, the attribute memory space and i/o memory space are 16 mbytes, and the common memory space is 64 mbytes . in the common me mory space, set the pc card address in bit 2 (p0pa25) and bit 1 (p0pa24) of the general control re gister to access each address of 16 mbytes unit. by this operation, values are output to a25 and a2 4 pins, enabling an address space of more than 16 mbytes to be accessed (initial value: 0 for p0pa25). when an address of 16 mbytes or less is accessed, no settings are require d. this bit does not af fect access to attribute memory space or i/o memory space. figures 29.3 shows the relations hip between the memory space of this lsi and th e memory and i/o spaces of the pc card in the continuous 16 -mbyte area mode. memory space and i/o space are supported in area 6. the attribute memory space, comm on memory space, and i/o space of the pc card are provided as 16-mbyte physical spaces in this mode. therefore, this lsi automatically controls pcc_reg pin (the value of bit 0 (p0reg) in the general control register is ignored). in area 6, the output of pcc_reg pin is 0 when the attribute memory space or i/o space is accessed, and 1 when the common memory space is accessed. see the register descriptions in section 29.3, register descriptions for details of register settings. this lsi memory space pc card address space general control register bit settings p0mmod = 1 p0reg = x attribute memory 16 mbytes (pin pccreg is alwys 0) i/o space 16 mbytes (pin pccreg is alwys 0) attribute memory common memory i/o space 16 mbytes 16 mbytes 16 mbytes p0pa25 = x, p0pa24 = x p0pa25 = 0, p0pa24 = 0 p0pa25 = 0, p0pa24 = 1 p0pa25 = 1, p0pa24 = 0 p0pa25 = 1, p0pa24 = 1 common mermoy (pin pccreg is always 1) total 64 mbytes not used h'18000000 h'1a000000 p0pa25 = x, p0pa24 = x x: don't care area 6 p0pa25 p0pa24 figure 29.3 continuous 16 -mbyte area mode (area 6) section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 962 of 1458 rej09b0033-0300 29.2 input/output pins pcc related external pins are listed below. table 29.2 pcc pin configuration pin name abbreviation i/o description pcc wait request pcc_wait input hardware wait request signal pcc 16-bit input/output pcc_iois16 input write protection signal from pc card when ic memory interface is connected signal to indicate 16- bit i/o from pc card when i/o card interface is connected pcc ready pcc_rdy input ready/busy signal form pc card when ic memory interface is connected interrupt request signal from pc card when i/o card interface is connected pcc battery detection 1 pcc_bvd1 input buttery voltage detect 1 signal from pc card when ic memory interface is connected card status change signal from pc card when i/o card interface is connected pcc battery detection 2 pcc_bvd2 input buttery voltage detect 2 signal from pc card when ic memory interface is connected digital sound signal from pc card when i/o card interface is connected pcc card detection 1 pcc_cd1 input card detect 1 signal from pc card pcc card detection 2 pcc_cd2 input card detect 2 signal from pc card pcc voltage detection 1 pcc_vs1 input voltage sense 1 signal from pc card pcc voltage detection 2 pcc_vs2 input voltage sense 2 signal from pc card pcc space indication pcc_reg output area indicate signal for pc card pcc buffer control pcc_drv output buffer control signal pcc reset pcc_reset output re set signal for pc card section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 963 of 1458 rej09b0033-0300 29.3 register descriptions pcc has the following registers. ? area 6 interface status register (pcc0isr) ? area 6 general control register (pcc0gcr) ? area 6 card status change register (pcc0cscr) ? area 6 card status change interrupt enable register (pcc0cscier) 29.3.1 area 6 interface status register (pcc0isr) pcc0isr is an 8-bit read-only register, which is used to read the status of the pc card connected to area 6. the initial value of pcc0isr depends on the pc card status. bit bit name initial value r/w description 7 p0rdy/ ireq undefined * r pcc0 ready the value on the rdy/ bsy pin of the pc card connected to area 6 is read when the ic memory card interface is connected. the value of ireq pin of the pc card connected to area 6 is read when the i/o card interface is connected. this bit cannot be written to. 0: indicates that the value of rdy/ bsy pin is 0 when the pc card connected to area 6 is an ic memory card interface type. the value of ireq pin is 0 when the pc card connected to area 6 is the i/o card interface type. 1: indicates that the value of rdy/ bsy pin is 1 when the pc card connected to area 6 is the ic memory card interface type. the value of ireq pin is 1 when the pc card connected to area 6 is the i/o card interface type. section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 964 of 1458 rej09b0033-0300 bit bit name initial value r/w description 6 p0mwp undefined * r pcc0 write protect the value of wp pin of the pc card connected to area 6 is read when the ic memory card interface is connected. 0 is read when the i/o card interface is connected. this bit cannot be written to. 0: indicates that the value of wp pin is 0 when the pc card connected to area 6 uses the ic memory card interface type. the value of bit 6 is always 0 when the pc card connected to area 6 is the i/o card interface type. 1: indicates that the value of wp pin is 1 when the pc card connected to area 6 is the ic memory card interface type. 5 p0vs2 undefined * r pcc0 voltage sense 2 the value of vs2 pin of the pc card connected to area 6 is read. this bit cannot be written to. 0: the value of vs2 pin of the pc card connected to area 6 is 0 1: the value of vs2 pin of the pc card connected to area 6 is 1 4 p0vs1 undefined * r pcc0 voltage sense 1 the value of vs1 pin of the pc card connected to area 6 is read. this bit cannot be written to. 0: the value of vs1 pin of the pc card connected to area 6 is 0 1: the value of vs1 pin of the pc card connected to area 6 is 1 3 p0cd2 undefined * r pcc0 card detect 2 the value of cd2 pin of the pc card connected to area 6 is read. this bit cannot be written to. 0: the value of cd2 pin of the pc card connected to area 6 is 0 1: the value of cd2 pin of the pc card connected to area 6 is 1 section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 965 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 p0cd1 undefined * r pcc0 card detect 1 the value of cd1 pin of the pc card connected to area 6 is read. this bit cannot be written to. 0: the value of cd1 pin of the pc card connected to area 6 is 0 1: the value of cd1 pin of the pc card connected to area 6 is 1 1 p0bvd2/ p0spkr undefined * r 0 p0bvd1/ p0stschg undefined * r pcc0 battery voltage detect 2 and 1 the values of bvd1 and bvd2 pin of the pc card connected to area 6 are read when the ic memory card interface is connected. the values of stschg and spkr pin of the pc card connected to area 6 are read when the i/o card interface is connected. these bits cannot be written to. (1) the following applies to the ic memory interface. 11: the battery voltage of the pc card connected to area 6 is normal (battery good) 01: the battery must be changed although data is guaranteed for the pc card connected to area 6 (battery warning) x0: the battery voltage is abnormal and data is not guaranteed for the pc card connected to area 6 (battery dead) (2) the values of bits 1 and 0 for the i/o card interface are as follows: 0: the value of stschg or spkr of the pc card connected to area 6 is 0 1: the value of stschg or spkr of the pc card connected to area 6 is 1 note: * differs depending on the state of the pc card. section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 966 of 1458 rej09b0033-0300 29.3.2 area 6 general control register (pcc0gcr) pcc0gcr is an 8-bit readable/writable register, wh ich controls the external buffer, resets, address a25 and a24 pins, and reg pin, and sets the pc card type fo r the pc card connected to area 6. pcc0gcr is initialized by a power-on reset but retains its value in a manual reset and in software standby mode. bit bit name initial value r/w description 7 p0drve 0 r/w pcc0 buffer control controls the external buffer for the pc card connected to area 6. 0: high-level setting for control pcc_drv pin of the external buffer for the pc card connected to area 6 1: low-level setting for control pcc_drv pin of the external buffer for the pc card connected to area 6 6 p0pccr 0 r/w pcc0 card reset controls resets for the pc card connected to area 6. 0: low-level setting for re set pcc_reset pin for the pc card connected to area 6 1: high-level setting for reset pcc_reset pin for the pc card connected to area 6 5 p0pcct 0 r/w pcc0 card type specifies the type of the pc card connected to area 6. cleared to 0 when the pc card is the ic memory card interface type; set to 1 when the pc card is the i/o card interface type. 0: the pc card connected to area 6 is handled as the ic memory card interface type 1: the pc card connected to area 6 is handled as the i/o card interface type section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 967 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 p0use 0 r/w pcc0 use/not use specifies that the pc card controller to be worked or not worked. 0: pc card controller doesn't work 1: pc card controller works note: when setting p0use to 1, following settings are required. when p0use is set to 1 and p0pcct is set to 0, bits 21 and 20 (sa1 and sa0) in the cs6bwcr register of bsc should be set to 0. when p0use and p0pcct are set to 1, bits 21 and 20 (sa1 and sa0) in the cs6bwcr register of bsc should be set to 1. before p0use is set to 1, bits 15 to 12 (type3 to type0) in cs6bbcr of bsc should be set to 0101. 3 p0mmod 0 r/w pcc0 mode controls pcc_reg and a24 pins for the pc card connected to area 6. spec ifies either a24 of the address to be accessed or bit p0reg for outputting to pcc_reg pin. when the common memory space is accessed, specifies either a24 of the address to be accessed or bit p0pa24 for outputting to a24 pin. by this operation, continuous 32 or 16 mbytes can be selected for the address area of the common memory space of the pc card. 0: bit p0reg is output to pcc_reg pin, and a24 of address to be accessed is output to a24 pin (continuous 32-mbyte area mode) 1: a24 of address to be accessed is output to pcc_reg pin. when the common memory space is accessed, p0pa24 is output to a24 pin (continuous 16-mbyte area mode) section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 968 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 p0pa25 0 r/w pc card address controls a25 pin for the pc card connected to area 6. when the common memory space is accessed for the pc card connected to area 6, this bit is output to a25 pin. when the attribute memo ry space or i/o space is accessed, this bit is meaningless. 0: when the common memory space is accessed for the pc card connected to area 6, 0 is output to a25 pin 1: when the common memory space is accessed for the pc card connected to area 6, 1 is output to a25 pin 1 p0pa24 0 r/w pc card address controls a24 pin for the pc card connected to area 6. when bit p0mmod is 1 and the common memory space is accessed for the pc card connected to area 6, this bit is output to a24 pin. when bit p0mmod is 0 or the attribute memory space or i/o space is accessed, this bit is meaningless. 0: when bit p0mmod is 1 and the common memory space is accessed for the pc card connected to area 6, 0 is output to a24 pin 1: when bit p0mmod is 1 and the common memory space is accessed for the pc card connected to area 6, 1 is output to a24 pin 0 p0reg 0 r/w pcc0reg space indication controls pcc_reg pin for the pc card connected to area 6. when bit p0mmod is 0, this bit is output to pcc_reg pin for the pc card connected to area 6. when bit p0mmod is 1 or the i/o card interface is accessed, this bit is meaningless. 0: when bit p0mmod is 0 and the pc card connected to area 6 is accessed, 0 is output to pcc_reg pin 1: when bit p0mmod is 0 and the pc card connected to area 6 is accessed, 1 is output to pcc_reg pin section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 969 of 1458 rej09b0033-0300 29.3.3 area 6 card status change register (pcc0cscr) pcc0cscr is an 8-bit readable/writable able regi ster. pcc0cscr bits are set to 1 by interrupt sources of the pc card connected to area 6 (only bit 7 can be set to 1 as required). pcc0cscr is initialized by a power-on reset but retains its value in a manual reset and in software standby mode. bit bit name initial value r/w description 7 p0scdi 0 r/w pcc0 software card detect change interrupt a pcc0 software card detect change interrupt can be generated by writing 1 to this bit. when this bi t is set to 1, the same interrupt as the pcc0 card detect change interrupt (bit 3 set status) occurs if bit 3 (pcc0 card detect change enable) in the area 6 card status change interrupt enable register (pcc0cscier) is set to 1. if bit 3 is cleared to 0, no interrupt occurs. 0: no software card detect change interrupt occurs for the pc card connected to area 6 1: software card detect change interrupt occurs for the pc card connected to area 6 6 ? 0 ? reserved this bit is always read as 0. t he write value should always be 0. 5 p0ireq 0 r/w pcc0ireq request indicates the interrupt request for the ireq pin of the pc card when the pc card connected to area 6 is the i/o card interface type. the p0ireq bit is set to 1 when an interrupt request signal in pulse mode or level mode is input to the ireq . the mode is selected by bits 5 and 6 (pcc0ireq interrupt enable bits) in the area 6 card status change interrupt enable register (pcc0cscier). this bit can be cl eared to 0 only in pulse mode. write 0 to bit 5 to clear the bit to 0. this bit is not changed if 1 is written. in level mode, bit 5 is a read-only bit, which reflects the ireq state (if the ireq is low, 1 is read). this bit always reads 0 on the ic memory card interface. 0: no interrupt request on the ireq of the pc card when the pc card is on the i/o card interface 1: an interrupt request on the ireq of the pc card has occurred when the pc card is on the i/o card interface section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 970 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 p0sc 0 r/w pcc0 status change indicates a change in the value of the stschg of the pc card when the pc card connected to area 6 is the i/o card interface type. when the stschg is changed from 1 to 0, the p0sc bit is set to 1. when stschg is not changed, the p0sc bit remains at 0. write 0 to bit 4 when this bit is set to 1 in order to clear this bit to 0. this bit is not changed if 1 is written. this bit always reads 0 on the ic memory card interface. 0: stschg of the pc card is not changed when the pc card is on the i/o card interface 1: stschg of the pc card is changed from 1 to 0 when the pc card is on the i/o card interface 3 p0cdc 0 r/w pcc0 card detect change indicates a change in the value of the cd1 and cd2 in the pc card connected to area 6. when the cd1 and cd2 values are changed, the p0cdc bit is set to 1. when the values are not changed, the p0cdc bit remains at 0. write 0 to bit 3 in order to clear this bit to 0. this bit is not changed if 1 is written. 0: cd1 and cd2 in the pc card are not changed 1: cd1 and cd2 in the pc card are changed 2 p0rc 0 r/w pcc0 ready change indicates a change in the value of the rdy/ bsy of the pc card when the pc card connected to area 6 is the ic memory card interface type. when the rdy/ bsy is changed from 0 to 1, the p0rc bit is set to 1. when the rdy/ bsy is not changed, the p0rc bit remains at 0. write 0 to bit 2 in order to clear this bit to 0. this bit is not changed if 1 is written. this bit always reads 0 on the i/o card interface. 0: rdy/ bsy in the pc card is not changed when the pc card is on the ic memory card interface 1: rdy/ bsy in the pc card is changed from 0 to 1 when the pc card is on the ic memory card interface section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 971 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 p0bw 0 r/w pcc0 battery warning indicates whether the bvd2 and bvd1 of the pc card are in the state in which "the battery must be changed although the data is guaranteed" when the pc card connected to area 6 is on the ic memory card interface. when the bvd2 and bvd1 are 0 and 1, respectively, the p0bw bit is set to 1; in other cases, the p0bw bit remains at 0. this bit is updated when the bvd2 and bvd1 are changed. write 0 to bit 1 in order to clear this bit to 0. this bit is not ch anged if 1 is written. this bit always reads 0 on the i/o card interface. 0: bvd2 and bvd1 of the pc card are not in the battery warning state when the pc card is in the ic memory card interface 1: bvd2 and bvd1 of the pc card are in the battery warning state and "the battery must be changed although the data is guaranteed" when the pc card is on the ic memory card interface 0 p0bd 0 r/w pcc0 battery dead indicates whether the bvd2 and bvd1 of the pc card are in the state in which "the battery must be changed since the data is not guaranteed" when the pc card connected to area 6 is on the ic memory card interface. when the bvd2 and bvd1 are 1 and 0 or 0 and 0, the p0bd bit is set to 1; in other cases, the p0bd bit remains at 0. this bit is updated when the bvd2 and bvd1 are changed. write 0 to bit 0 in order to clear this bit to 0. this bit is not changed if 1 is written. this bit always reads 0 on the i/o card interface. 0: bvd2 and bvd1 of the pc card are not in the state in which "the battery must be changed since the data is not guaranteed" when the pc card is on the ic memory card interface 1: bvd2 and bvd1 of the pc card are in the state in which "the battery must be changed since the data is not guaranteed" when the pc card is on the ic memory card interface section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 972 of 1458 rej09b0033-0300 29.3.4 area 6 card status change in terrupt enable register (pcc0cscier) the area 6 card status change interrupt en able register (pcc0cscier) is an 8-bit readable/writable register. pcc0 cscier enables or disables in terrupt requests for interrupt sources for the pc card connected to area 6. when a pcc0cscier is set to 1, the corresponding interrupt is enabled, and when the bit is cleared to 0, the interrupt is disabled. pcc0cscier is initialized by a power-on reset but retains its value in a manual reset and in software standby mode. bit bit name initial value r/w description 7 p0cre 0 r/w pcc0 card reset enable when this bit is set to 1, and when the cd1 and cd2 detect that a pc card is connected to area 6, the area 6 general control register (p cc0gcr) is initialized. 0: the area 6 general contro l register (pcc0gcr) is not initialized even if a pc card is detected in area 6 1: the area 6 general contro l register (pcc0gcr) is initialized when a pc card is detected connected to area 6 section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 973 of 1458 rej09b0033-0300 bit bit name initial value r/w description 6 ireqe1 0 r/w 5 ireqe0 0 r/w pcc0ireq request enable these bits enable or disable ireq interrupt requests and select the interrupt mode when the pc card connected to area 6 is the i/o card interface type. note that bit 5 (p0ireq) in the area 6 card status change register (pcc0cscr) is cleared if the values in bits 6 and 5 in this register are changed. these bits have no meaning on the ic memory card interface. 00: ireq requests are not accepted for the pc card connected to area 6. bit 5 in the status change register (pcc0cscr) functions as a read-only bit that indicates the inverse of the ireq signal. 01: the level-mode ireq interrupt request signal is accepted for the pc card connected to area 6. in level mode, an interrupt occurs when level 0 of the signal input from the ireq is detected. 10: the pulse-mode ireq interrupt request signal is accepted for the pc card connected to area 6. in pulse mode, an interrupt occurs when a falling edge from 1 to 0 of the signal input from the ireq is detected. 11: the pulse-mode ireq interrupt request signal is accepted for the pc card connected to area 6. in pulse mode, an interrupt occurs when a rising edge from 0 to 1 of the signal input from the ireq is detected. 4 p0sce 0 r/w pcc0 status change enable when the pc card connect ed to area 6 is on the i/o card interface, bit 4 enables or disables the interrupt request when the value of the bvd1 (stschg) is changed. this bit has no meaning in the ic memory card interface. 0: no interrupt occurs for the pc card connected to area 6 regardless of the value of the bvd1 (stschg) 1: an interrupt occurs for the pc card connected to area 6 when the value of the bvd1 (stschg) is changed from 1 to 0 section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 974 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 p0cde 0 r/w pcc0 card detect change enable bit 3 enables or disables the interrupt request when the values of the cd1 and cd2 are changed. 0: no interrupt occurs for the pc card connected to area 6 regardless of the values of the cd1 and cd2 1: an interrupt occurs for the pc card connected to area 6 when the values of the cd1 and cd2 are changed 2 p0re 0 r/w pcc0 ready change enable when the pc card connected to area 6 is on the ic memory card interface, bit 2 enables or disables the interrupt request when the value of the rdy/ bsy is changed. this bit has no meaning on the i/o card interface. 0: no interrupt occurs for the pc card connected to area 6 regardless of the value of the rdy/ bsy 1: an interrupt occurs for the pc card connected to area 6 when the value of the rdy/ bsy is changed from 0 to 1 1 p0bwe 0 r/w pcc0 battery warning enable when the pc card connected to area 6 is on the ic memory card interface, bit 1 enables or disables the interrupt request when the bvd2 or bvd1 are in the state in which "the battery must be changed although the data is guaranteed". this bit has no meaning on the i/o card interface. 0: no interrupt occurs when the bvd2 or bvd1 are in the state in which "the battery must be changed although the data is guaranteed" 1: an interrupt occurs when the bvd2 or bvd1 are in the state in which "the battery must be changed although the data is guaranteed" section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 975 of 1458 rej09b0033-0300 bit bit name initial value r/w description 0 p0bde 0 r/w pcc0 battery dead enable when the pc card connected to area 6 is on the ic memory card interface, bit 0 enables or disables the interrupt request when the bvd2 and bvd1 are in the state in which "the battery must be changed since the data is not guaranteed". this bit has no meaning on the i/o card interface. 0: no interrupt occurs when the bvd2 and bvd1 are in the state in which "the battery must be changed since the data is not guaranteed" 1: an interrupt occurs when the bvd2 and bvd1 are in the state in which "the battery must be changed since the data is not guaranteed" section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 976 of 1458 rej09b0033-0300 29.4 operation 29.4.1 pc card connection specification (interface di agram, pin correspondence) a25 to a0 d15 to d0 pcc0drv rd/ wr ce1b ce2b rd we iciord iciowr pcc_reset pcc_reg a25 to a0 d15 to d0 cd1 cd2 vs1 vs2 ce1 ce2 oe we /pgm ( iord ) ( iowr ) reset reg area 6 pc card (memory or i/o) g g g dir dir g d7 to d0 d15 to d8 pcc_wait pcc_iois16 pcc_rdy pcc_bvd1 pcc_bvd2 wait wp( iois16 ) rdy/ bsy ( ireq ) bvd1 ( stschg ) bvd2 ( spkr ) g pcc_cd1 / cd2 pcc_vs1 / vs2 this lsi figure 29.4 interface section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 977 of 1458 rej09b0033-0300 table 29.3 pcmcia support interface ic memory card interface i/o card interface pin signal name i/o function signal name i/o function this lsi corresponding pin 1 gnd ground gnd ground ? 2 d3 i/o data d3 i/o data d3 3 d4 i/o data d4 i/o data d4 4 d5 i/o data d5 i/o data d5 5 d6 i/o data d6 i/o data d6 6 d7 i/o data d7 i/o data d7 7 ce1 i card enable ce1 i card enable ce1b 8 a10 i address a10 i address a10 9 oe i output enable oe i output enable rd 10 a11 i address a11 i address a11 11 a9 i address a9 i address a9 12 a8 i address a8 i address a8 13 a13 i address a13 i address a13 14 a14 i address a14 i address a14 15 we / pgm i write enable we / pgm i write enable we 16 rdy/ bsy o ready/busy ireq o interrupt request pcc_rdy 17 vcc power supply vcc power supply ? 18 vpp1 programming power supply vpp1 programming and peripheral power supply ? 19 a16 i address a16 i address a16 20 a15 i address a15 i address a15 21 a12 i address a12 i address a12 22 a7 i address a7 i address a7 23 a6 i address a6 i address a6 24 a5 i address a5 i address a5 25 a4 i address a4 i address a4 section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 978 of 1458 rej09b0033-0300 ic memory card interface i/o card interface pin signal name i/o function signal name i/o function this lsi corresponding pin 26 a3 i address a3 i address a3 27 a2 i address a2 i address a2 28 a1 i address a1 i address a1 29 a0 i address a0 i address a0 30 d0 i/o data d0 i/o data d0 31 d1 i/o data d1 i/o data d1 32 d2 i/o data d2 i/o data d2 33 wp o write protect iois16 o 16-bit i/o port pcc_iois16 34 gnd ground gnd ground ? 35 gnd ground gnd ground ? 36 cd1 o card detection cd1 o card detection pcc_cd1 37 d11 i/o data d11 i/o data d11 38 d12 i/o data d12 i/o data d12 39 d13 i/o data d13 i/o data d13 40 d14 i/o data d14 i/o data d14 41 d15 i/o data d15 i/o data d15 42 ce2 i card enable ce2 i card enable ce2b 43 vs1 o voltage sense vs1 o voltage sense pcc_vs1 44 rfu reserved iord i i/o read iciord 45 rfu reserved iowr i i/o write iciowr 46 a17 i address a17 i address a17 47 a18 i address a18 i address a18 48 a19 i address a19 i address a19 49 a20 i address a20 i address a20 50 a21 i address a21 i address a21 51 vcc power supply vcc power supply ? section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 979 of 1458 rej09b0033-0300 ic memory card interface i/o card interface pin signal name i/o function signal name i/o function this lsi corresponding pin 52 vpp2 programming power supply vpp2 programming and peripheral power supply ? 53 a22 i address a22 i address a22 54 a23 i address a23 i address a23 55 a24 i address a24 i address a24 56 a25 i address a25 i address a25 57 vs2 o voltage sense vs2 o voltage sense pcc_vs2 58 reset i reset reset i reset pcc_reset 59 wait o wait request wait o wait request pcc_wait 60 rfu reserved inpack o input acknowledge ? 61 reg i attribute memory space select reg i attribute memory space select pcc_reg 62 bvd2 o battery voltage detection spkr o digital sound signal pcc_bvd2 63 bvd1 o battery voltage detection stschg o card status change pcc_bvd1 64 d8 i/o data d8 i/o data d8 65 d9 i/o data d9 i/o data d9 66 d10 i/o data d10 i/o data d10 67 cd2 o card detection cd2 o card detection pcc_cd2 68 gnd ground gnd ground ? section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 980 of 1458 rej09b0033-0300 29.4.2 pc card interface timing (1) memory card interface timing ckio tpcm1 tpcm2 a25 to a0 pcc_drv rd/ wr cexx rd (read) d15 to d0 (write) we (read) d15 to d0 (read) pcc_reg pcc_reset 0 0 figure 29.5 pcmcia memory card interface basic timing section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 981 of 1458 rej09b0033-0300 ckio a25 to a0 d15 to d0 (read) d15 to d0 (write) tpcm0 tpcm0w tpcm1 tpcm1w tpcm1w tpcm2 tpcm2w pcc_reset 0 0 pcc_drv pcc_wait rd/ wr cexx rd (read) we (read) pcc_reg figure 29.6 pcmcia memory card interface wait timing section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 982 of 1458 rej09b0033-0300 (2) i/o card interface timing ckio tpcm1 tpcm2 a25 to a0 pcc_drv iciord (read) d15 to d0 (write) iciowr (read) d15 to d0 (read) pcc_reset 0 rd/ wr cexx pcc_reg figure 29.7 pcmcia i/o ca rd interface basic timing section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 983 of 1458 rej09b0033-0300 ckio a25 to a0 d15 to d0 (read) d15 to d0 (write) pcc_wait pcc_iois16 tpci0 tpci0w tpci1 tpci1w tpci1w tpci2 tpci2w pcc_reset 0 0 pcc_drv iciord (read) iciowr (read) rd/ wr cexx pcc_reg figure 29.8 pcmcia i/o ca rd interface wait timing section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 984 of 1458 rej09b0033-0300 tpci0 tpci1 tpci1w tpci2 tpci1 tpci1w tpci2 tpci2w ckio 0 0 a25 to a1 a0 d15 to d0 (read) d15 to d0 (write) pcc0wait iois16 pcc_reset pcc_drv iciord (read) iciowr (read) rd/ wr cexx pcc_reg figure 29.9 dynamic bus sizing timi ng for pcmcia i/o card interface section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 985 of 1458 rej09b0033-0300 29.5 usage notes (1) external bus frequency limit when using pc card according to the pc card standard , the attribute memory access time is specified as 600 ns (3.3 v)/300 ns (5 v). therefore, wh en this lsi accesses attribute memory, the bus cycle must be coordinated with the pc card interf ace timing. in this lsi, the timi ng can be adjusted by setting the ted, teh, and pcw values in the cs6bwcr regi ster, allowing a pc car d to be used within the above frequency ranges. the common memory access time and i/o access time (based on the (iord) and (iowr) signals) are also similarly specified (see table below), and a pc card must be used within the above ranges in order to satisfy all these specifications. pc card space access time (5 v operat ion) access time (3.3 v operation) attribute memory 300 ns 600 ns common memory 250 ns 600 ns i/o space (pulse width of iord and iowr ) 165 ns 165 ns (2) pin function control and card type switching when setting pin function controller pin functions to dedicated pc card use ("other function"), the disabled state should first be set in the card status change interrupt enable register (pcc0cscier). also, the card status change register (pcc0cscr) must be cleared after the setting has been made. however, this restriction does not apply to the card detection pins ( cd1 and cd2 ). when changing the card type bit (p0pcct) in the area 6 general control register (pcc0gcr), the disabled state should first be set in the card status change interrupt enable register (pcc0cscier). also, the card status change register (pcc0cscr) must be cleared after the setting has been made. reason: when pc card controller settings are modified , the functions of pc card pins that generate various interrupts change, with the result that unnecessary interrupts may be generated. section 29 pc card controller (pcc) rev. 3.00 jan. 18, 2008 page 986 of 1458 rej09b0033-0300 (3) setting procedure when using pc card controller the following steps should be followed when using a card controller: 1. set bit 12 (map) in the common control register (cmncr) of bus state controller to 1. 2. set bits 15 to 12 (type3 to type0) in the bus control register for cs6b (cs6bbcr) of the bus state controller to b'0101. 3. set bit 4 (p0use) in the area 6 general control register in the pc card controller to 1. 4. set the pin function controller to custom pc card pin functions ("other functions"). section 30 sim card module (sim) scis000a_0000200110000 rev. 3.00 jan. 18, 2008 page 987 of 1458 rej09b0033-0300 section 30 sim card module (sim) the smart card interface supports ic cards (smart cards) conforming to the iso/iec 7816-3 (identification card) specification. 30.1 features ? communication functions asynchronous half-duplex transmission protocol selectable between t = 0 and t = 1 modes data length: 8 bits parity bit generation and check selectable character protection addition time selectable output cl ock cycles per etu transmission of error si gnal (parity error) in receive mode when t = 0 detection of error signal and auto matic character retransmission in transmit mode when t = 0 selectable minimum character interval of 11 etus (n = 255) when t = 1 (etu: elementary time unit) selectable direct convention/inverse convention output clock can be fixed in high or low state ? freely selectable bit rate by on-chip baud rate generator ? four types of interrupt source transmit data empty, receive data full, transmit/receive error, transmit complete ? dma transfer through dma transfer requests for transmit da ta empty and receive data full, the direct memory access controller (dmac) can be started and used for data transfer. ? the time waiting for the operation when t = 0, and the time waiting for a character when t = 1 can be observed. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 988 of 1458 rej09b0033-0300 figure 30.1 shows a block diagram of the smart card interface. scscmr: scrsr: scrdr: sctsr: sctdr: scsmr: scscr: scsc2r: scssr: scbrr: scwait: scgrd: scsmpl: smart card mode register receive shift register receive data register transmit shift register transmit data register serial mode register serial control register serial control 2 register serial status register bit rate register wait time register guard extension register sampling register [legend] sim_clk sim_d sim_rst module data bus baud rate generator serial clock eri transmit/receive control txi rxi tei transmit data empty receive data full interrupt controller dma controller scrdr sctdr scrsr sctsr parity generation parity check scsmr scscr scssr scscmr scsc2r scwait scgrd scbrr scsmpl p peripheral bus bus interface figure 30.1 smart card interface section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 989 of 1458 rej09b0033-0300 30.2 input/output pins the pin configuration of the smart car d interface is shown in table 30.1. table 30.1 pin configuration name abbreviation i/o function sim data sim_d * i/o transmit/receive data input/output sim clock sim_clk output clock output sim reset sim_rst output smart card reset output note: * in explaining transmit and receive operat ions, the transmit data and receive data sides shall be referred to as txd and rxd, respectively. 30.3 register descriptions the sim card module has the following registers. refer to section 37, list of registers, for more details on the addresses and states of these registers in each operating mode. ? serial mode register (scsmr) ? bit rate register (scbrr) ? serial control register (scscr) ? transmit shift register (sctsr) ? transmit data register (sctdr) ? serial status register (scssr) ? receive shift register (scrsr) ? receive data register (scrdr) ? smart card mode register (scscmr) ? serial control 2 register (scsc2r) ? guard extension register (scgrd) ? wait time register (scwait) ? sampling register (scsmpl) section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 990 of 1458 rej09b0033-0300 30.3.1 serial mode register (scsmr) scsmr is an 8-bit readable/writable register that selects settings for the communication format of the smart card interface. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 4 o/ e 0 r/w parity mode selects whether even or odd parity is to be used when adding a parity bit and checking parity. 0: even parity * 1 1: odd parity * 2 notes: 1. when set to even parity, during transmission a parity bit is added such that the sum of 1 bits in the parity bit and transmit characters is even. during reception, a check is performed to ensure that the sum of 1 bits in the parity bit and the receive characters is even. 2. when set to odd parity, during transmission a parity bit is added such that the sum of 1 bits in the parity bit and transmit characters is odd. during reception, a check is performed to ensure that the sum of 1 bits in the parity bit and the receive characters is odd. 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 991 of 1458 rej09b0033-0300 30.3.2 bit rate register (scbrr) scbrr is an 8-bit readable/writable register that sets the transmit/receive bit rate. bit bit name initial value r/w description 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 1 0 brr2 brr1 brr0 1 1 1 r/w r/w r/w set the transmit/receive bit rate 2 to 0. the scbrr setting can be determined from the following formula. sck_frequency = p 2 ( brr + 1) the units of p (peripheral clock frequency) and sck_frequency are mhz. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 992 of 1458 rej09b0033-0300 30.3.3 serial control register (scscr) scscr is an 8-bit readable/writable register that selects transmit or receive operation, the serial clock output, and whether to enable or disable interrupt requests for the smart card interface. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when serial transmit data is transferred from the transmit data register (sctdr) to the transmit shift register (sctsr), and the tdre flag in the serial status register (scssr) is set to 1, transmit data empty interrupt (txi) requests are enabled/disabled. 0: disables transmit data em pty interrupt (txi) requests * 1: enables transmit data em pty interrupt (txi) requests note: * a txi can be canceled either by clearing the tdre flag, or by clearing the tie bit to 0. 6 rie 0 r/w receive interrupt enable when serial receive data is transferred from the receive shift register (scrsr) to the receive data register (scrdr), and the rdrf flag in scssr is set to 1, receive data full interrupt (rxi) requests, and transmit/receive error interrupt (eri) requests due to parity errors, overrun errors, and error signal status are enabled/disabled. 0: disables receive data full interrupt (rxi) requests and transmit/receive error interrupt (eri) requests * 1 * 2 1: enables receive data full interrupt (rxi) requests and transmit/receive error interrupt (eri) requests * 2 notes: 1. rxi and eri interrupt requests can be canceled either by clearing the rdrf, per, orer or ers flag, or by clearing the rie bit to 0. 2. wait error interrupt (eri) requests are enabled or disabled by using the wait_ie bit in scscr. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 993 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 te 0 r/w transmit enable enables/disables serial transmit operations. 0: disables transmission * 1 1: enables transmission * 2 * 3 notes: 1. the tdre flag in scssr is fixed to 1. 2. in this state, if transmit data is written to sctdr, the transmit operation is initiated. before setting the te bit to 1, the serial mode register (scsmr) and smart card mode register (scscmr) must always be set, to determine the transmit format. 3. even if the te bit is cleared to 0, the ers flag is unaffected, and the previous state is retained. 4 re 0 r/w receive enable enables/disables serial receive operations. 0: disables reception * 1 1: enables reception * 2 notes: 1. clearing the re bit to 0 has no effect on the rdrf, per, ers, orer, or wait_er flag, and the previous state is retained. 2. if the start bit is detec ted in this state, serial reception is initiated. before setting the re bit to 1, scsmr and scscmr must always be set, to determine the receive format. 3 wait_ie 0 r/w wait enable enables/disables wait error interrupt requests. 0: disables wait error interrupt (eri) requests 1: enables wait error interrupt (eri) requests 2 teie 0 r/w transmit end interrupt enable when transmission ends and the tend flag is set to 1, transmit end interrupt (tei) requests are enabled/disabled. 0: disables transmit end interrupt (tei) requests * 1: enables transmit end interrupt (tei) requests * note: * a tei can be canceled either by writing transmit data to sctdr and clearing the tend bit, or by clearing the teie bit to 0 after the tdre flag in scssr is read as 1. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 994 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 1, 0 select the clock source for the smart card interface, and enable/disable clock output from the sim_clk pin. 00: fix the output pin at low 01: clock output as the output pin 10: fix the output pin at high 11: clock output as the output pin 30.3.4 transmit shift register (sctsr) sctsr is a shift register that transmits serial data. the smart card interface transfer s transmit data from the transmit data register (sctdr) to sctsr, and then sends the data in order from the lsb or msb to the sim_txd pin to perform serial data transmission. when data transmission of one byte is completed, transmit data is automatically transferred from sctdr to sctsr, and transmission is initiated. wh en the tdre flag in the serial status register (scssr) is set to 1, no data is transferred from sctdr to sctsr. direct reading and writing of sctsr from the cpu or dmac is not possible. 30.3.5 transmit data register (sctdr) sctdr is an 8-bit readable/writable register that stores data for serial transmission. when the smart card interface detects a vacancy in the transmit shift register (sctsr), transmit data written to sctdr is transferred to sctsr, and serial transmission is initiated. during sctsr serial data transmission, if the next transmit data is written to sctdr, continuous serial transmission is possible. bit bit name initial value r/w description 7 to 0 sctd7 to sctd0 all 1 r/w transmit data store data for serial transmission. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 995 of 1458 rej09b0033-0300 30.3.6 serial status register (scssr) scssr is an 8-bit readable/writable register that indicates the operating state of the smart card interface. bit bit name initial value r/w description 7 tdre 1 r/w transmit data register empty indicates that data was transferred from the transmit data register (sctdr) to the transmit shift register (sctsr), and that the next serial transmit data can be written to sctdr. 0: indicates that valid transmit data is written to sctdr [clearing conditions] ? when the te bit in ccscr is 1, and data is written to sctdr ? when 0 is written to the tdre bit 1: indicates that there is no valid transmit data in sctdr [setting conditions] ? on reset ? when the te bit in scscr is 0 ? when data is transferred from sctdr to sctsr, and data can be written to sctdr section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 996 of 1458 rej09b0033-0300 bit bit name initial value r/w description 6 rdrf 0 r/w receive data register full indicates that received data is stored in the receive data register (scrdr). 0: indicates that no valid received data is stored in scrdr [clearing conditions] ? on reset ? when data is read from scrdr ? when 0 is written to rdrf 1: indicates that valid received data is stored in scrdr [setting condition] when serial reception is completed normally, and received data is transferred from scrsr to scrdr. note: in t = 0 mode, when a parity error is detected during reception, the scrdr cont ents and rdrf flag are unaffected, and the previous state is retained. on the other hand, in t = 1 mode, when a parity error is detected during reception, the received data is transferred to scrdr, and the rdrf flag is set to 1. in both t = 0 and t = 1 modes, even if the re bit in the serial control register (scscr) is cleared to 0, the scrdr contents and rdrf flag are unaffected, and the previous state is retained. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 997 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 orer 0 r/w overrun error indicates that an overrun error occurred during reception, resulting in abnormal termination. 0: indicates that reception is in progress, or that reception was completed normally * 1 [clearing conditions] ? on reset ? when 0 is written to the orer bit 1: indicates that an overrun error occurred during reception * 2 [setting condition] when the rdrf bit is set to 1 and the next serial reception is completed. notes: 1. when the re bit in scscr is cleared to 0, the orer flag is unaffected and the previous state is retained. 2. in scrdr, the receiv ed data before the overrun error occurred is lost, and the data that had been received at the time when the overrun error occurred is retained. further, with the orer bit set to 1, subsequent serial reception cannot be continued. 4 ers 0 r/w error signal status indicates the status of error signals returned from the receive side during transmission. in t = 1 mode, this flag is not set. 0: indicates that an error signal indicating detection of a parity error was not sent from the receive side [clearing conditions] ? on reset ? when 0 is written to the ers bit 1: indicates that an error signal indicating detection of a parity error was sent from the receive side [setting condition] when an error signal is sampled. note: even if the te bit in scscr is cleared to 0, the ers flag is unaffected, and the previous state is retained. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 998 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 per 0 r/w parity error indicates that a parity error has occurred during reception, resulting in abnormal termination. 0: indicates that reception is in progress, or that reception was completed normally * 1 [clearing conditions] ? on reset ? when 0 is written to the per bit 1: indicates that a parity error occurred during reception * 2 [setting condition] when the sum of 1 bit in the received data and parity bit does not match the even or odd parity specified by the o/e bit in the serial mode register (scsmr). notes: 1. when the re bit in scscr is cleared to 0, the per flag is unaffected, and the previous state is retained. 2. in t = 0 mode, the data received when a parity error occurs is not transferred to scrdr, and the rdrf flag is not set. on the other hand, in t = 1 mode, the data received when a parity error occurs is transferred to scrdr, and the rdrf flag is set. when a parity error occurs, the per flag should be cleared to 0 before the sampling timing for the next parity bit. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 999 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 tend 1 r transmit end indicates that transmission is ended. the tend flag is read-only, and cannot be written. 0: indicates that transmission is in progress [clearing condition] when transmit data is transferred from sctdr to sctsr, and serial transmission is initiated. 1: indicates that transmission is ended [setting conditions] ? on reset ? when the ers flag is 0 (normal transmission) after one byte of serial character and a parity bit are transmitted note: the tend flag is set 1 etu before the end of the character protection time. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1000 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 wait_er 0 r/w wait error indicates the wait timer error status. 0: indicates that the interval between the start of two successive characters has not exceeded the etu set by scwait. [clearing conditions] ? on reset ? when 0 is written to the wait_er flag 1: indicates that the interval between the start of two successive characters has exceeded the etu set by scwait. [setting conditions] ? in t = 0 mode, when the interval between the start of a character to be received and immediately preceding transmitted or received character exceeds the (value of 60 scwait: operation wait time) etu. ? in t = 1 mode, when the interval between the start of two successive received characters exceeds the (scwait value: character protection time) etu. notes: 1. even if the re bit in scscr is cleared to 0, the wait_er flag is unaffected, and the previous state is retained. 2. in t = 0 mode, even if the setting condition for the wait_er flag is satisfied when the re bit is set to 1, the wait_er flag may not be set to 1. in this case, the re bit has been set to 1, then the wait_er flag is set to 1 after 60 (scwait + n) etu (n 0: depending on the timing for setting the re bit to 1) since the last transmission or reception. 3. in t = 0 mode, if the wait_er flag does not need to be set to 1 after 60 (scwait + n) etu since the last transmission or reception, the mode should be changed from t = 0 to t = 1, and changed to t = 0 again by the pb bit in scscmr. in t = 1 mode, if the wait_er flag does not need to be set to 1 after (scwait) etu since the la st reception, the mode should be changed from t = 1 to t = 0, and changed to t = 1 again by the pb bit in scscmr. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1001 of 1458 rej09b0033-0300 bit bit name initial value r/w description 0 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 30.3.7 receive shift register (scrsr) scrsr is a register that receives serial data. the smart card interface receives serial data inpu t from the sim_rxd pin in order, from the lsb or msb, and sets it in scrsr, converting it to pa rallel data. when reception of one byte of data is completed, the data is automatically transferre d to scrdr. the cpu or dmac cannot directly read from or write to scrsr. 30.3.8 receive data register (scrdr) scrdr is an 8-bit read-only register that stores received serial data. when reception of one byte of serial data is completed, the smart card interface transfers the received serial data from the receive shift regist er (scrsr) to scrdr for storage, and completes the receive operation. thereafter, scrsr can r eceive data. in this way, scrsr and scrdr constitute a double buffer, enabling continuous rece ption of data. scrdr cannot be written to by the cpu or dmac. bit bit name initial value r/w description 7 to 0 scrd7 to scrd0 all 0 r receive data store received serial data. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1002 of 1458 rej09b0033-0300 30.3.9 smart card mode register (scscmr) scscmr is an 8-bit readable/writable register th at selects functions of the smart card interface. bit bit name initial value r/w description 7 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. 6 lcb 0 r/w last character when this bit is set to 1, the character protection time is 2 etus, and the setting of the gu ard extension register is invalid. 0: the character protection ti me is determined by the value of the guard extension register. 1: the character protection time is 2 etus. 5 pb 0 r/w protocol selects the t = 0 or t = 1 protocol. 0: the smart card interface operates according to the t = 0 protocol. 1: the smart card interface operates according to the t = 1 protocol. 4 ? 0 r/w reserved this bit is always read as 0. the write value should always be 0. 3 sdir 0 r/w smart card data transfer direction selects the format for serial/parallel conversion. 0: transmits the sctdr contents in lsb-first. received data is stored in scrdr as lsb-first. 1: transmits the sctdr contents in msb-first. received data is stored in scrdr as msb-first. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1003 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 sinv 0 r/w smart card data inversion specifies inversion of the data logic level. in combination with the function of bit 3, used for tr ansmission to or reception from the inverse convention card. the sinv bit does not affect the parity bit. 0: transmits the sctdr contents without change. stores received data in scrdr without change. 1: inverts the sctdr contents and transmits it. inverts received data and stores it in scrdr. 1 rst 0 r/w smart card reset controls the output of the sim_rst pin of the smart card interface. 0: the sim_rst pin of the smar t card interface outputs low level. 1: the sim_rst pin of the smar t card interface outputs high level. 0 smif 1 r/w smart card interface mode select this bit is always read as 1. the write value should always be 1. 30.3.10 serial control 2 register (scsc2r) scsc2r is an 8-bit readable/writable register that enables or disables receive data full interrupt (rxi) requests. bit bit name initial value r/w description 7 eio 0 r/w error interrupt only when the eio bit is 1, even if the rie bit is set to 1, a receive data full interrupt (rxi) request is not sent to the cpu. when the dmac is used with this setting, the cpu processes only eri requests. receive data full interrupt (rxi) requests are determined by the rie bit setting. 6 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1004 of 1458 rej09b0033-0300 30.3.11 guard extension register (scgrd) scgrd is an 8-bit readable/writable register th at sets the time added fo r character protection. bit bit name initial value r/w description 7 to 0 scgrd7 to scgrd0 all 0 r/w guard extension indicate the time added for character protection after transmitting a character to the smart card. the interval between the start of two successive characters is 12 etus (no addition) when the value of this register is h'00, is 13 etus when the value is h'01, and so on, up to 266 etus for h'fe. if the value of this register is h'ff, the interval between the start of two successive characters is 11 etus in t = 1 mode and is 12 etus in t = 0 mode. 30.3.12 wait time register (scwait) scwait is a 16-bit readable/writabl e register. if the interval betw een the start of two successive characters exceeds the set value (in etu units), a wait time error is generated. bit bit name initial value r/w description 15 to 0 scwait15 to scwait0 all 0 r/w wait time register ? t = 0 in this mode, the operation wait time can be set in this register. if the interval between the start of characters to be received and transmitted or received characters immediately before exceeds the (60 the value set in this register) etu, the wait_er flag is set to 1. however, if scwait is set to h'0000, the wait_er flag is set after 60 etus. ? t = 1 in this mode, the character wait time can be set in this register. if the interval between the start of two successive received characters exceeds the (the value set in this register) etu, the wait_er flag is set to 1. however, if scwait is set to h'0000, the wait_er flag is set after 1 etu. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1005 of 1458 rej09b0033-0300 30.3.13 sampling register (scsmpl) scsmpl is a 16-bit readable/writable register that sets the number of serial clock cycles per etu. bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 10 to 0 scsmpl10 to scsmpl0 h'173 r/w setting for number of serial clock cycles per etu the number of serial clock cycles per etu is (scsmpl value + 1). the value written to scsmpl should always be h'0007 or greater. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1006 of 1458 rej09b0033-0300 30.4 operation 30.4.1 overview the main functions of the smar t card interface are as follows. ? one frame consists of 8-bit data and one parity bit. ? during transmission, a character protection time, set using scgrd and the lcb and pb bits in scscmr, is inserted between the end of each parity bit and the beginning of the next frame. ? during reception in t = 0 mode, when a parity error is detected, low level is output for a duration of 1 etu as an error signal, 10.5 etus after the start bit. ? during transmission in t = 0 mode, if an error signal is sampled, after 2 etus or more have elapsed, the same data is automatically transmitted. ? only asynchronous communication functions are supported; there is no clocked synchronous communication function. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1007 of 1458 rej09b0033-0300 30.4.2 data format figure 30.2 shows the data format used by the smart card interface. the smart card interface performs a parity check for each frame during reception. during reception in t = 0 mode, if a parity error is detected, an error si gnal is returned to the transmit side, requesting data retransmission. when the transmit side samples the error signal, it retransmits the same data. during reception in t = 1 mode, if a parity error is detected, an error signal is not returned. during transmission, error signals are not samp led and data is not retransmitted. ds d0 d1 d2 d3 d4 d5 d6 d7 dp ds d1 d2 d3 d4 d5 d6 d7 dp ds d0 de ds d0 d1 d2 d3 d4 d5 d6 d7 dp ds when no parity error occurs when a parity error occurs in t=0 mode when a parity error occurs in t=1 mode transmitter output transmitter output transmitter output receiver output ds: start bit, d0 to d7: data bits, dp: parity bit, de: error signal figure 30.2 data format us ed by smart card interface the operation sequence is as follows. 1. when not in use, the data line is in a high-i mpedance state and fixed at high level by a pull-up resistance. 2. the transmit side initiates transmission of on e frame of data. the data frame begins with the start bit (ds: low level). this is followed by eight data bits (d0 to d7) and the parity bit (dp). section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1008 of 1458 rej09b0033-0300 3. the smart card interface then returns the data line to high impedance. the data line is held at high level by the pull-up resistance. 4. the receive side pe rforms a parity check. if there is no parity error an d reception is normal, reception of the next frame is awaited, without further action. on the other hand, when a parity error has occurred in t = 0 mode, an error signal (de: low level) is output, requesting data retransmission. after output of an error signal with the specified duration, the receive si de again sets the signal line to the high-impedance state. the signal line returns to high level by means of the pull-up resistance. if in t = 1 mode, however, no error signal is output even if a parity error occurs. 5. if the transmit side does not receive an er ror signal, the next frame is transmitted. on the other hand, if in t = 0 mode and an error signal is received, the data for which the error occurred is retransmitted as in step 2 above. in t = 1 mode, however, error signals are not received and retransmission is not performed. 30.4.3 register settings table 30.2 shows a map of the bits in the registers used by the smart card interface. bits for which 0 or 1 is shown must always be set to the value shown. the method for setting the bits other than these is explained below. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1009 of 1458 rej09b0033-0300 table 30.2 register settings for smart card interface bit register bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 scsmr 0 0 pe o/ e 0 0 0 0 scbrr 0 0 0 0 0 brr2 brr1 brr0 scscr tie rie te re wait_ie teie cke1 cke0 sctdr sctd7 sctd6 sctd5 sctd4 sctd3 sctd2 sctd1 sctd0 scssr tdre rdrf orer ers per tend wait_er 0 scrdr scrd7 scrd6 scrd5 scrd4 scrd3 scrd2 scrd1 scrd0 scscmr 0 lcb pb 0 sdir sinv rst 1 scsc2r eio 0 0 0 0 0 0 0 scwait scwait15 to scwait0 scgrd scgrd7 to scgrd0 scsmpl scsmpl10 to scsmpl0, bits 11 to 15 are 0 ? serial mode register (scsmr) setting when the ic card is set for the direct convention, the o/ e bit is cleared to 0; for the inverse convention, it is set to 1. ? bit rate register (scbrr) setting sets the bit rate. for the method of computing settings, refer to section 30.4.4, clocks. ? serial control register (scscr) settings each interrupt can be enabled and disabled using the tie, rie, tei e, and wait_ie bits. by setting either the te or re bit to 1, transmission or reception is selected. the cke1 and cke0 bits are used to select the clock output state. for details, refer to section 30.4.4, clocks. ? smart card mode register (scscmr) settings when the ic card is set for the direct conventi on, both the sdir and sinv bits are cleared to 0; for the inverse convention, both are set to 1. the smif bit is always set to 1. figure 30.3 below shows the register settings an d waveform examples at the start character for two types of ic cards (a direct-convention type and an inverse-convention type). for the direct-convention type, the logical level 1 is assigned to the z state, and the logical level 0 to the a state, and transmission and recep tion are performed in lsb-first. the data of the above start character is then h'3b. even parity is used according to the smart card specification, and so the parity bit is 1. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1010 of 1458 rej09b0033-0300 for the inverse-convention type, the logical level 1 is assigned to the a state, and the logical level 0 to the z state, and transmission and r eception are performed in ms b-first. the data of the start character shown in figure 30.3 is then h'3f. even parity is used according to the smart card specification, and so the parity b it is 0 corresponding to the z state. in addition, the only d7 to d0 bits are inverted by the sinv bit. the o/ e bit in scsmr is set to odd parity mode to invert the parity bit. in tr ansmission and reception, the setting condition is similar. ds d0 d1 d2 d3 d4 d5 d6 d7 dp ds d7 d6 d5 d4 d3 d2 d1 d0 dp a zz a zz a az z a zz a aa a az a (z) (z) (z) (z) state state (a) direct convention (sdir=sinv=o/ e =0) (b) inverse convention (sdir=sinv=o/ e =1) figure 30.3 examples of start character waveforms section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1011 of 1458 rej09b0033-0300 30.4.4 clocks only the internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock in the smart card interface. the bit rate is set using the bit rate register (scbrr) and the sampling register (scsmpl), usin g the formula indicated below. examples of bit rates are listed in table 30.3 here, when the cke0 bit is set to 1 and the clock output is selected, a clock signal is output from the sim_clk pin with frequency equal to (scsmpl + 1) times the bit rate. b = p 10 6 /{(s+1) 2 (n+1)} where b = bit rate (bits/s) p = operating frequency of the peripheral module s = scsmpl setting (0 s 2047) n = scbrr setting (0 n 7). table 30.3 example of bit rates (bits/s) for scbrr settings (p = 19.8 mhz, scsmpl = 371) scbrr setting sck frequency (mhz) bit rate (bits/s) 7 1.2375 3327 6 1.414 3802 5 1.65 4435 4 1.98 5323 3 2.475 6653 2 3.3 8871 1 4.95 13306 0 9.9 26613 note: the bit rate is a value that is rounded off below the decimal point. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1012 of 1458 rej09b0033-0300 30.4.5 data transmit/receive operation (1) initialization prior to data transmission and reception, the following procedure should be used to initialize the smart card interface. initialization is also necessary when switching from tr ansmit mode to receive mode, and when switching from receive mode to transmit mode. an exampl e of the initialization process is shown in the fl owchart of figure 30.4. step (1) to step (7) of figure 30.4 correspond to the following operation. 1. clear the te and re bits in the se rial control register (scscr) to 0. 2. clear the error flags per, or er, ers, and wait_er in the seri al status register (scssr) to 0. 3. set the parity bit (o/ e bit) in the serial mode register (scsmr). 4. set the lcb, pb, smif, sdir, and sinv bits in the smart card mode register (scscmr). 5. set the value corresponding to the bit rate to the bit rate register (scbrr). 6. set the clock source select bits (cke1 and cke0 bits) in the serial co ntrol register (scscr). at this time, the tie, rie, te, re, teie, and wait_ie bits should be cleared to 0. if the cke0 bit is set to 1, a clock signal is output from the sim_clk pin. 7. after waiting at least 1 etu, set the tie, rie, te, re, teie, and wait_ie bits in scscr. except for self-check, the te bit and re bit should not be set simultaneously. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1013 of 1458 rej09b0033-0300 yes no wait initialization clear the te and re bits in scscr to 0 clear the ers, per, orer, and wait_er flags in scssr to 0 set the parity using the o/ e bit in scsmr set the lcb, pb, smif, sdir, and sinv bits in scscmr set scbrr set the clock using the cke1 and cke0 bits in scscr. clear the tie, rie, te, re, teie, and wait_ie flags to 0. has a 1-bit interval elapsed? set the tie, rie, te, and re bits in scscr end (1) (2) (3) (4) (5) (6) (7) figure 30.4 example of initialization flow section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1014 of 1458 rej09b0033-0300 (2) serial data transmission data transmission in smart card mode includes error signal sampling and retransmit processing. an example of transmit processing is shown in figure 30.5. step (1) to step (6) of figure 30.5 correspond to the following operation. 1. follow the initialization procedure ab ove to initialize the smart card interface. 2. confirm that the ers bit (error flag) in scssr is cleared to 0. 3. repeat steps (2) and (3) until it can be confirmed that the tdre flag in scssr is set to 1. 4. write transmit data to sctdr, and perform transmission. at this time, the tdre flag is automatically cleared to 0. when transmission of the start bit is started, the tend flag is automatically cleared to 0, and the tdre flag is automatically set to 1. 5. when performing continuous data transmission, return to step (2). 6. when transmission is ende d, clear the te bit to 0. interrupt processing can be performed in the above series of processing. when the tie bit is set to 1 to enable interrupt requests and if transmission is started and the tdre flag is set to 1, a transmit data empty inte rrupt (txi) request is issued. when the rie bit is set to 1 to enable interrupt requests and if an er ror occurs during transmission and the ers flag is set to 1, a transmit/receive error in terrupt (eri) request is issued. for details, refer to interrupt operations in section 30.4.5, data tr ansmit/receive operation. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1015 of 1458 rej09b0033-0300 yes no no yes yes no yes no no yes initialization start transmission ers=0? error processing tdre=1? write transmit data to sctdr all data transmitted? ers=0? error processing tend=1? tdre=1? clear te bit in scscr to 0 transmit end (1) (2) (3) (4) (5) (6) figure 30.5 example of transmit processing section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1016 of 1458 rej09b0033-0300 (3) serial data reception an example of data receive processing in smart card mode is shown in figure 30.6. step (1) to step (6) of figure 30.6 correspond to the following operation. 1. follow the initialization procedure ab ove to initialize the smart card interface. 2. confirm that the per, orer, and wait_er flags in scssr are 0. if one of these flags is set, after performing the prescribed receive error processing, clea r the per, orer, and wait_er flags to 0. 3. repeat steps (2) and (3) in the figure until it can be confirmed that the rdrf flag is set to 1. 4. read received data from scrdr. 5. when receiving data conti nuously, return to step (2). 6. when reception is ended, clear the re bit to 0. interrupt processing can be performed in the above series of processing. when the rie bit is set to 1 and the eio bit is cl eared to 0 and if the rdrf flag is set to 1, a receive data full interrupt (rxi) request is issued. if the rie bit is set to 1, an error occurs during reception, and either the orer, per, or wait_e r flag is set to 1, a transmit/receive error interrupt (eri) request is issued. for details, refer to, interrupt operations in s ection 30.4.5, data tran smit/receive operation. if a parity error occurs during reception and the per flag is set to 1, in t = 0 mode the received data is not transferred to scrdr, and so this data cannot be read . in t = 1 mode, received data is transferred to scrdr, and so this data can be read. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1017 of 1458 rej09b0033-0300 yes no no yes yes no initialization start reception are per, orer, and wait_er all 0s? error processing rdrf=1? read received data from scrdr all data received? clear re bit in scscr to 0 receive end (1) (2) (3) (4) (5) (6) figure 30.6 example of receive processing (4) switching modes when switching from receive mode to transmit mo de, after confirming that reception has been completed, start initialization, and then clear the re bit to 0 and set the te bit to 1. completion of reception can be confirmed through the rdrf flag. when switching from transmit mode to receive mo de, after confirming that transmission has been completed, start initialization, and then clear the te bit to 0 and set the re bit to 1. completion of transmission can be confirmed through the tdre and tend flags. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1018 of 1458 rej09b0033-0300 (5) interrupt operations the smart card interface has four types of interrupt requests: transmit data empty interrupt (txi) requests, transmit/receive e rror interrupt (eri) reques ts, receive data full interrupt (rxi) requests, and transmit end interr upt (tei) requests. ? when the tdre flag in scssr is set to 1, a txi request is issued. ? when the rdrf flag in scssr is set to 1, an rxi request is issued. ? when the ers, orer, per, or wait_er flag in scssr is set to 1, an eri request is issued. ? when the tend flag in scssr is set, a tei request is issued. table 30.4 lists the interrupt sour ces for the smart card interface. each of the interrupt requests can be enabled or disabled using the tie, rie, teie, and wait_ie bits in scscr and the eio bit in scsc2r. in addition, each interrupt request can be sent independen tly to the interrupt controller. table 30.4 interrupt sources of smart card interface operating state flags mask bits interrupt sources tdre tie txi normal operation tend teie tei transmit mode error ers rie eri normal operation rdrf rie, eio rxi orer, per rie eri receive mode error wait_er wait_ie eri section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1019 of 1458 rej09b0033-0300 (6) data transfer using dmac the smart card interface enables recep tion and transmission using the dmac. in transmission, when the tdre flag in scssr is set to 1, a dma transfer request for transmit data empty is issued. if a dma transfer request for transmit data empty is set in advance as a dmac activation source, the dmac can be activat ed and made to transfer data when a dma transfer request for tran smit data empty occurs. when in t = 0 mode and if an error signal is received during transmission, the same data is automatically retransmitted. at the time of this re transmission, no dma transfer request is issued, and so the number of byt es specified to the dm ac can be transmitted. when using the dmac for transmit data processing and performing error processing as a result of an interrupt request sent to the cpu, the tie bit should be cleared to 0 so that no txi requests are generated, and the rie bit should be set to 1 so that an eri request is issued. the ers flag set when an error signal is received is not cleared automatically, and so should be cleared by sending an interrupt request to the cpu. in receive operation, when the rdrf flag in scssr is set to 1, a dma transfer request for receive data full is issued. by setting a dma transf er request for receive data full in advance as a dmac activation source, the dmac can be activat ed and made to transfer data when a dma transfer request for receive data full occurs. when in t = 0 mode and if a parity error occurs during reception, a data retransmit request is issued. at this time the rdrf flag is not set, and a dma transfer reques t is not issued, so the number of bytes specified to the dmac can be received. when using the dmac for receive data processing and performing error processing as a result of an interrupt request sent to the cpu, the rie bit should be set to 1 and the eio bit to 1, so that no rxi requests are generated and only eri requests are generated. the per, orer, and wait_er flags that are set by a receive error are not automatically cleared, and so should be cleared by sending an interrupt request to the cpu. when using the dmac for transmission and reception, the dmac should always be set first and put into the enabled state, before setting the smart card interface. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1020 of 1458 rej09b0033-0300 30.5 usage notes the following matters should be noted when using the smart card interface. (1) receive data timing and receive margin when scsmpl holds its initial va lue, the smart card interface operates at a basic clock frequency 372 times the transfer rate. during reception, the smart card in terface samples the falling edge of the start bit using the serial clock for internal synchron ization. receive data is captured in ternally at the rising edge of the 186th serial clock pulse. this is shown in figure 30.7. 00 185 185 371 0 371 d0 d1 372 clock pulses 186 clock pulses basic clock received data start bit synchronization sampling timing data sampling timing (rxd) figure 30.7 receive data sampling timing in smart card mode section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1021 of 1458 rej09b0033-0300 hence the receive margin can be expressed as follows. formula for receive margin in smart card mode: m = ( 0.5 ? 2n n 1 ) ?? d ? 0.5 ( l ? 0.5 ) f ( l + f ) 100% where m: receive margin ( % ) n: ratio of the bit rate to the clock (n = 372) d: clock duty (d = 0 to 1.0) l: frame length (l = 10) f: absolute value of the deviation of the clock frequency in the above formula, if f = 0 and d = 0.5, then the receive margin is as follows. when d = 0.5, f = 0, m = (0.5 ? 1/2 372) 100% = 49.866%. (2) retransmit operation retransmit operations when the smart card interface is in receive mode and in transmit mode are described below. (a) retransmission when the smart card interface is in receive mode (t = 0) figure 30.8 shows retransmit opera tions when the smart card interf ace is in receive mode. step (1) to step (5) of figure 30.8 correspond to the following operation. 1. if an error is detected as a result of checking the received parity bit, the per bit in scssr is automatically set to 1. at this time, if the rie bit in scscr is set to enable, an eri request is issued. the per bit in scssr should be cleared to 0 before the sampling timing for the next parity bit. 2. the rdrf bit in scssr is not set for frames in which a parity error occurs. 3. if no error is detected as a result of checking the received parity bit, the per bit in scssr is not set. 4. if no error is detected as a result of check ing the received parity bit, it is assumed that reception was completed normally, an d the rdrf bit in scssr is au tomatically set to 1. if the rie bit in scscr is 1 and the eio bit is 0, an rxi request is generated. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1022 of 1458 rej09b0033-0300 5. if a normal frame is received, the pin reta ins its high-impedance state at the timing for transmission of error signals. d0 d1 d2 d3 d4 d5 d6 d7 dp ds d0 d1 d2 d3 d4 d5 d6 d7 dp ds d0 d1 d2 d3 d4 ds rdrf de per (de) nth transmit frame retransmit frame (n+1)th transmit frame (1) (2) (4) (3) (5) figure 30.8 retransmission when smar t card interface is in receive mode (b) retransmission when the smart card interface is in transmit mode (t = 0) figure 30.9 shows retransmit oper ations when the smart card inte rface is in transmit mode. step (1) to step (4) of figure 30.9 corr espond to the following operation 1. after completion of transmission of one frame, if an error signal is returned from the receive side, the ers bit in scssr is set to 1. if the rie bit in scscr is set to enable, an eri request is issued. the ers bit in scssr should be cleared to 0 before the sampling timing for the next parity bit. 2. in t = 0 mode, the tend bit in scssr is not set for a frame when an error signal indicating an error is received. 3. if no error signal is returned from the r eceive side, the ers bit in scssr is not set. 4. if no error signal is returned from the receive side, it is assumed that transmission of one frame, including retransmission, is completed, and the tend bit in scssr is set to 1. at this time, if the tie bit in scscr is set to enable, a tei interrupt request is issued. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1023 of 1458 rej09b0033-0300 d0 d1 d2 d3 d4 d5 d6 d7 dp ds d0 d1 d2 d3 d4 d5 d6 d7 dp ds d0 d1 d2 d3 d4 ds tend tdre de ers (de) nth transmit frame retransmit frame (n+1)th transmit frame transmission from sctdr to sctsr transmission from sctdr to sctsr (1) (2) (3) (4) figure 30.9 retransmit standby mode (clock stopped) when smart card interface is in transmit mode (3) standby mode switching when switching between smart card interface mode and standby mode, in order to retain the clock duty, the following switching procedure should be used. step (1) to step (7) of figure 30.10 correspond to the following operation. ? when switching from smart card interface mode to standby mode a. write 0 to the te and re bits in the serial control register (scscr), to stop transmit and receive operations. at the same time, set th e cke1 bit to the value for the output-fixed state in standby mode. b. write 0 to the cke0 bit in scscr to stop the clock. c. wait for one cycle of the serial clock. during this interval, the duty is retained, and the clock output is fixed at the specified level. d. make the transition to standby mode. ? to return from standby mode to smart card interface mode e. cancel the standby state. f. set the cke1 bit in the serial control register (scscr) to the value of the output-fixed state at the beginning of standby (the current sim_clk pin state). g. write 1 to the cke0 bit in scscr to output a clock signal. clock signal generation begins at normal duty. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1024 of 1458 rej09b0033-0300 sim_clk normal operation normal operation standby mode (1) (2) (3) (4) (5) (6) (7) figure 30.10 procedure for stopping clock and restarting (4) power-on and clock output in order to retain the clock duty from power-on, the following switching procedure should be used. 1. the initial state is set to port-input with high impedance. in order to fix the potential, a pull-up resistance/pull-down resistance is used. 2. use the cke1 bit in the serial control re gister (scscr) to fix the specified output. 3. set the cke0 bit in scscr to 1 to start clock output. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1025 of 1458 rej09b0033-0300 (5) pin connections an example of pin connections for the smart card interface is shown in figure 30.11. in communication with the smart card, transmission and reception are performed using a single data transmit line. the data transmit line should be pulled up by a resistance on the power supply v cc side. when using the clock generated by the smart car d interface with the ic card, the sim_clk pin output is input to the clk pin of the ic card. if an internal clock of the ic card is used, this connection is not needed. sim_d sim_clk sim_rst i/o clk rst 20 k ? smart card interface note: for details, refer to iso/iec7816-3. smart card this lsi reset line clock line data line figure 30.11 example of pin connections in smart card interface note: the transmission/reception in loop can perf orm self-check when the re and te bits are set to 1 without connecting to the ic card. section 30 sim card module (sim) rev. 3.00 jan. 18, 2008 page 1026 of 1458 rej09b0033-0300 (6) transmit end interrupt in continuous transmission, when the teie bit is always set to 1, the tend bit is set to 1 at a transmit end. therefore, the unnecessary transmit end interrupt (tei) request occurs. when sctsr starts transmitting afte r the last transmit data is written to sctdr, the teie bit in scscr should be set to 1 so that the occurrence of the unnecessary tei interrupt request can be prevented. the waveform of the timing to set the teie bit to 1 is shown in figure 30.12. d0 d1 d2 d3 d4 d5 d6 d7 dp ds d0 d1 d2 d3 d4 d5 d6 d7 dp ds d0 d1 d2 d3 d4 d5 d6 d7 dp ds tend tdre (de) (de) teie (de) transmit frame transmit frame last frame unnecessary tend set timing teie set timing tei request figure 30.12 teie set timing section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1027 of 1458 rej09b0033-0300 section 31 multimediacard interface (mmcif) this lsi includes a multimediacard interf ace (mmcif). the mmcif has mmc mode. the mmcif is a clock-synchronou s serial interface that tr ansmits/receives data that is distinguished in terms of command and response. a number of command/responses are predefined in the multimediacard. as the mmcif specifies a comm and code and command type/response type upon the issuance of a comman d, commands extended by the secure multimediacard (secure- mmc) and additional commands can be supported in future within the range of combinations of currently defined command types/response types. 31.1 features ? interface that complies with 'the multimedia card system specification version 3.1' ? supports mmc mode ? for the card interface, 16.5-mbps bit rate (max) at a peripheral- module operating clock of 33 mhz ? incorporates sixty-four 16-bit data-transfer fifos ? dma transfer request can be issued ? four interrupt sources fifo empty/full, command/response/data transfer complete, transfer error, and fifo ready ? mmc mode interface via the clk output (transfer clock out put) pin, cmd inpu t/output (command transmission/response reception) pin, and dat input/output (data transmission/reception) pin section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1028 of 1458 rej09b0033-0300 a block diagram of the mmcif is shown in figure 31.1. mmcif fifo peripheral bus data transmission/ reception control mmc mode control card clock generator interrupt control command transmission/ response contol internal bus interface int_err_n int_fstat_n int_tran_n int_frdy_n mmc_clk mmc_cmd mmc_dat csa csb mmc_odmo d mmc_vddon port interface figure 31.1 block diagram of mmcif section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1029 of 1458 rej09b0033-0300 31.2 input/output pins table 31.1 summarizes the pins of the mmcif. table 31.1 pin configuration pin name abbreviation (mmc) i/o function mmc_clk clk output clock output pin mmc_cmd cmd i/o command output/response input pin mmc_dat dat i/o data input/output pin mmc_vddon mmc_vddon output mmc power control mmc_odmod mmc_odmod output open drain mode control (active-low signal) note: to describe transmission and reception oper ation, the data-transmi ssion and data-reception sides as mctxd and mcrxd, respectively. to insert/detach a card or for signals for switching open-drain/cmos mode, use ports of this lsi. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1030 of 1458 rej09b0033-0300 31.3 register descriptions the mmcif has the following registers. refer to section 37, list of registers, for more details on the addresses and states of these registers in each operating mode. ? mode register (moder) ? command type register (cmdtyr) ? response type register (rsptyr) ? transfer byte number count register (tbcr) ? transfer block number counter (tbncr) ? command registers 0 to 5 (cmdr0 to cmdr5) ? response registers 0 to 16 (rspr0 to rspr16) ? response register d (rsprd) ? command start register (cmdstrt) ? operation control register (opcr) ? command timeout control register (ctocr) ? data timeout register (dtoutr) ? card status register (cstr) ? interrupt control registers 0 and 1 (intcr0 and intcr1) ? interrupt status registers 0 and 1 (intstr0 and intstr1) ? pin mode control register (iomcr) ? transfer clock control register (clkon) ? vdd/open drain control register (vdcnt) ? data register (dr) ? fifo pointer clear register (fifoclr) ? dma control register (dmacr) ? interrupt control register 2 (intcr2) ? interrupt status register 2 (intstr2) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1031 of 1458 rej09b0033-0300 31.3.1 mode register (moder) moder specifies the mmcif operating mode. the mmcif has an operating mode: mmc mode. three signals, clock, command, an d data signals, are used as the interfaces between the host system and the mmc in mmc mode. the clock signal is used to make the host system and the mmc synchronize each other. the command signal is used to issue a command from the host system to the mmc and send a response from th e mmc to the host system. the data signal is used to write data to and read data from the mmc. the command and data signals are bidirectional buses. the following sequence should be repeated when the mmcif uses the mmc: send a command, wait for the end of the command sequence and the end of the data busy state, and send the next command. bit bit name initial value r/w description 7 to 1 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. 0 ? 0 r/w reserved the write value should always be 0. 31.3.2 command type register (cmdtyr) cmdtyr specifies the command format in conjunction with rsptyr. bits ty1 and ty0 specify the existence and direction of transfer data, and bits ty6 to ty2 specify the additional settings. all of bits ty6 to ty2 should be cleared to 0 or only one of them should be set to 1. bits ty6 to ty2 can only be set to 1 if the corresponding settings in bits ty1 and ty0 allow that setting. if this register is not set correctly, operation cannot be guaranteed. to perform single-block transfer, bits ty1 and ty0 should be set to 01 or 10 and bits ty6 to ty2 to 0. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1032 of 1458 rej09b0033-0300 bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 ty6 0 r/w specifies the pre-defin ed multiblock transfer. bits ty1 and ty0 should be set to 01 or 10. when the command which specifies this bit is used, the transfer block size and the num ber of transfer blocks should be specified in tbcr and tbncr, respectively. 5 ty5 0 r/w specifies the multiblock transfer while the secure mmc is used. bits ty1 and ty0 should be set to 01 or 10. when the command which specifies this bit is used, the transfer block size and the num ber of transfer blocks should be specified in tbcr and tbncr, respectively. 4 ty4 0 r/w this bit is set to 1 when the cmd12 command is issued. bits ty1 and ty0 should be set to 00. 3 ty3 0 r/w specifies the stream tr ansfer. bits ty1 and ty0 should be set to 01 or 10. the stream transfer can be used only in mmc mode. the command sequence of the st ream transfer specified by this bit ends when it is stopped by the cmd12 command. 2 ty2 0 r/w specifies the open-ended multiblock transfer. bits ty1 and ty0 should be set to 01 or 10. the command sequence of the st ream transfer specified by this bit ends when it is stopped by the cmd12 command. 1 0 ty1 ty0 0 0 r/w r/w specify the existence and di rection of transfer data. 00: a command without data transfer 01: a command with read data reception 10: a command with write data transmission 11: setting prohibited table 31.2 summarizes the correspondence between the commands described in the multimediacard system specification version 3.1 and the settings of cmdtyr and rsptyr. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1033 of 1458 rej09b0033-0300 31.3.3 response type register (rsptyr) rsptyr specifies command format in conjunction with cmdtyr. bits rty2 to rty0 are used to specify the number of response bytes, and b its rty5 and rty4 are used to make additional settings. bit bit name initial value r/w description 7, 6 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 5 rty5 0 r/w this bit is set when a command with r1b response is issued. 4 rty4 0 r/w makes settings so that the command response (other than r2 response) crc is checked by crc7. bits rty2 to rty0 should be set to 100. 3 rty3 0 r/w reserved 2 1 0 rty2 rty1 rty0 0 0 0 r/w r/w r/w these bits specify the number of command response bytes. 000: a command needs no command response. 001: setting prohibited 010: setting prohibited 011: setting prohibited 100: a command needs a 6-byte command response. specified by r1, r1b, r3, r4, and r5 responses. 101: a command needs a 17-byte command response. specified by r2 response. 110: setting prohibited 111: setting prohibited note: checking crc by rty4 is not checking the command response crc error bit but checking the command response crc. this checki ng is not performed for the crc of the r2 command response in mmc mode. table 31.2 summarizes the correspondence between the commands described in the multimediacard system specification version 3.1 and the settings of cmdtyr and rsptyr. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1034 of 1458 rej09b0033-0300 table 31.2 correspondence between commands and settings of cmdtyr and rsptyr ? mmc mode cmdtyr rsptyr cmd index abbreviation resp 6 5 4 3 2 1 to 0 6 5 4 2 to 0 cmd0 go_idle_state ? 00 000 cmd1 send_op_cond r3 00 100 cmd2 all_send_cid r2 00 101 cmd3 set_relative_addr r1 00 * 100 cmd4 set_dsr ? 00 000 cmd7 select/deselect_card r1b 00 1 * 100 cmd9 send_csd r2 00 101 cmd10 send_cid r2 00 101 cmd11 read_dat_until_stop r1 1 01 * 100 cmd12 stop_transmission r1b 1 00 1 * 100 cmd13 send_status r1 00 * 100 cmd15 go_inactive_state ? 00 000 cmd16 set_blocklen r1 00 * 100 cmd17 read_single_block r1 * 01 * 100 cmd18 read_multiple_block r1 * 1 * 1 01 * 100 cmd20 write_dat_until_stop r1 1 10 * 100 cmd23 set_block_count r1 00 * 100 cmd24 write_block r1 * 10 * 100 cmd25 write_multiple_block r1 * 1 * 1 10 * 100 cmd26 program_cid r1 10 * 100 cmd27 program_csd r1 10 * 100 cmd28 set_write_prot r1b 00 1 * 100 cmd29 clr_write_prot r1b 00 1 * 100 cmd30 send_write_prot r1 01 * 100 cmd32 * tag_sector_start r1 00 * 100 cmd33 * tag_sector_end r1 00 * 100 cmd34 * untag_sector r1 00 * 100 cmd35 tag_erase_group_start r1 00 * 100 section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1035 of 1458 rej09b0033-0300 cmdtyr rsptyr cmd index abbreviation resp 6 5 4 3 2 1 to 0 6 5 4 2 to 0 cmd36 tag_erase_group_end r1 00 * 100 cmd37 * untag_erase_group r1 00 * 100 cmd38 erase r1b 00 1 * 100 cmd39 fast_io r4 00 * 100 cmd40 go_irq_state r5 00 * 100 cmd42 lock_unlock r1b 10 1 * 100 cmd55 app_cmd r1 00 * 100 cmd56 gen_cmd r1b * 2 1 * 100 notes: * of cmd index: these commands are no t support by more developed mmc than mmca ver 3.1. * 1 of ty2 andty6 in cmdtyr: when specify the number of blocks in advance, set ty6; set ty2 when the number of blocks is not specified. * of ty5 bit in cmdtyr: set to perform multi block transfer using secure mmc. * of rty4 in rsptyr: set to 1 after che cking crc in the command response other than r2. (crc of the r2 command response cannot be checked.) * 2 of cmd56: when reading, write 01; 10 when writing. blank: set 0. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1036 of 1458 rej09b0033-0300 31.3.4 transfer byte number count register (tbcr) tbcr is an 8-bit readable/writable register that specifies the number of bytes to be transferred (block size) for each single block transfer co mmand. tbcr specifies the number of data block bytes not including the start and end bytes and crc. the multiblock transfer command corresponds to th e number of bytes of each data block. this setting is ignored by the stream tran sfer command in mmc mode stream. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 c3 c2 c1 c0 0 0 0 0 r/w r/w r/w r/w transfer data block size 0000: 1 byte 0001: 2 bytes 0010: 4 bytes 0011: 8 bytes 0100: 16 bytes 0101: 32 bytes 0110: 64 bytes 0111: 128 bytes 1000: 256 bytes 1001: 512 bytes 1010: 1024 bytes 1011: 2048 bytes 1100 to 1111: setting prohibited section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1037 of 1458 rej09b0033-0300 31.3.5 transfer block number counter (tbncr) tbncr sets the number of blocks to be transferre d when multiblock transfer is specified by bits ty5 and ty6 in cmdtyr. the contents of tbncr is decremented for every 1-block transfer completion. when the contents of tbncr is 0, the command sequence is terminated, and an interrupt is generated. bit bit name initial value r/w description 15 to 0 tbncr all 0 r/w transfer block number counter [clearing condition] when the specified number of blocks are transferred and 0 is written to tbncr. 31.3.6 command registers 0 to 5 (cmdr0 to cmdr5) cmdr are six 8-bit registers. a command is wr itten to cmdr as shown in table 31.3, and a command is transmitted by setting the start bit in cmdstrt to 1. table 31.3 cmdr configuration register contents operation cmdr0 start bit, host bit, and command index command index writing sets the start bit to 0, and the host bit to 1. cmdr1 to cmdr4 command argument command argument writing cmdr5 crc, end bit setting of crc is unnecessary (automatic calculation) setting of end bit is unnecessary (end bit is set to 1) ? cmdr0 bit bit name initial value r/w description 7 start 0 r/w start bit (this bit should be set to 0) 6 host 0 r/w transmission bit (this bit should be set to 1) 5 to 0 index all 0 r/w command indexes section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1038 of 1458 rej09b0033-0300 ? cmdr1 to cmdr4 bit bit name initial value r/w description 7 to 0 cmdr1 to cmdr4 all 0 r/w command arguments see specifications for the mmc. ? cmdr5 bit bit name initial value r/w description 7 to 1 crc all 0 ? this bit is unnecessary to be set, and is always read as 0. 0 end 0 ? this bit is unnecessary to be set, and is always read as 0. 31.3.7 response registers 0 to 16 and d (rspr0 to rspr16 and rsprd) rspr0 to rspr16 are seventeen 8-bit command response registers. rsprd is a 5-bit data register. the number of command response bytes differs according to the command. the number of command response bytes can be specified by the response type register (rsptyr) in the mmcif. the command response is shifted-in from the bit 0 in rspr16, and shifted to the number of command response bytes 8 bits. table 31.4 summarizes th e correspondence be tween the number of command response bytes and valid rspr. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1039 of 1458 rej09b0033-0300 table 31.4 correspondence between command response byte number and rspr mmc mode response rspr registers 6 bytes (r1, r1b, r3, r4, r5) 17 bytes (r2) rspr0 ? 1st byte rspr1 ? 2nd byte rspr2 ? 3rd byte rspr3 ? 4th byte rspr4 ? 5th byte rspr5 ? 6th byte rspr6 ? 7th byte rspr7 ? 8th byte rspr8 ? 9th byte rspr9 ? 10th byte rspr10 ? 11th byte rspr11 1st byte 12th byte rspr12 2nd byte 13th byte rspr13 3rd byte 14th byte rspr14 4th byte 15th byte rspr15 5th byte 16th byte rspr16 6th byte 17th byte rspr0 to rspr16 are simple shift registers. a command response that has been shifted in is not automatically cleared, and it is continuously shifted until it is shifted out from the bit 7 in rspr0. to clear unnecessary bytes to h'00, write arbitrary values to each rspr. ? rspr0 to rspr16 bit bit name initial value r/w description 7 to 0 rspr all 0 r/w these bits are cleared to h'00 by writing an arbitrary value. rspr0 to rspr16 are continuous 17-byte shift registers. command response is stored. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1040 of 1458 rej09b0033-0300 ? rsprd bit bit name initial value r/w description 7 to 5 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. 4 to 0 rsprd all 0 r/w these bits are cleared to h'00 by writing an arbitrary value. command response is stored. 31.3.8 command start register (cmdstrt) cmdstrt triggers the start of command transmission, represen ting the start of a command sequence. the following operations should be completed before the command sequence starts. command transmission: ? analysis of prior command response, clearin g the command response register write if necessary ? analyze/transfer receive data of prior command if necessary ? preparation of transmission data of the next command if necessary ? setting of cmdtyr, rspt yr, tbcr, and tbncr cmdr0 to cmdr4, cmdtyr, rsptyr, tbcr, and tbncr should not be changed until command transmission has ended (the cwre flag in cstr has been set to 1). ? setting of cmdr0 to cmdr4 the command sequences are controlled by the sequencers in each mmcif side and mmc side. normally, these operate synchron ously, however, these may become temporarily unsynchronized when an error occurs or when a command is abor ted. take care to set the cmdoff bit in opcr, to issue the cmd12 command, and to process an error in mmc mode. a new command sequence should be started after confirming that the command sequences on both the mmcif and mmc sides have ended. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1041 of 1458 rej09b0033-0300 bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 start 0 r/w starts command transmission when 1 is written. this bit is cleared by hardware. 31.3.9 operation cont rol register (opcr) opcr controls command operation abort, and suspends or continues data transfer. bit bit name initial value r/w description 7 cmdoff 0 r/w command off aborts all command operations (mmcif command sequence) when 1 is written after a command is transmitted. this bit is then cleared by hardware. write enable period: from command transmission completion to command sequence end writes 0: operation is not affected. writes 1: command sequence is forcibly aborted. 6 ? 0 ? reserved this bit is always read as 0. the write value should always be 0. 5 rd_ conti 0 r/w read continue after 1 is written, this bit is cleared by hardware when mmcif resumes reading data. resumes read data reception when the sequence is halted according to fifo full or termination of block reading in multiblock read. write enable period: while mcclk for read data reception is halted writes 0: operation is not affected. writes 1: resumes mcclk ou tput and read data reception. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1042 of 1458 rej09b0033-0300 bit bit name initial value r/w description 4 dataen 0 r/w data enable starts write data transmission by a command with write data. resumes write data transmission when the transfer clock is halted according to fifo empty or one block writing is terminated in multiblock write. write enable period: (1) after reception of a command response with write data, (2) while transfer clock is halted according to fifo empty, (3) when one block writing in multiblock write is terminated writes 0: operation is not affected. writes 1: starts or resumes transfer clock output and write data transmission. 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. for write data transmission, the contents of th e command response and data response should be analyzed, and then transmission should be triggered. in addition, write data transmission should be temporarily halted according to fifo full/empty , and it should be resume d when the preparation has been completed. for multiblock transfer, the transfer clock output should be temporarily halted for every block break to select either to continue to the next block or to abort the multiblock transfer command by issuing the cmd12 command, and the transfer clock output should be resumed. to continue to the next block, the rd_conti and dataen bits should be set to 1. to issue the cmd12 command, the cmdoff bit should be set to 1 to abort the command sequence on the mmcif side. setting rd_conti or datae bit between blocks, can be omitted when auto mode is used in pre-define multi block transfer. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1043 of 1458 rej09b0033-0300 31.3.10 command timeout control register (ctocr) ctocr specifies a cycle to generate a timeout for the command response. when receiving the command res ponse, ctoutc continues counti ng the transfer clock, and enters the command timeout error state when th e number of transfer clock reaches the number specified in ctocr. when the cterie bit in intcr1 is set to 1, the cteri flag in intstr1 is set. to perform command timeout error handling, the command sequence should be aborted by setting the cmdoff bit to 1, and then the cteri flag should be cleared. bit bit name initial value r/w description 7 to 1 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. 0 ctsel0 1 r/w 0: 128 transfer clocks from command transmission completion to response reception completion 1: 256 transfer clocks from command transmission completion to response reception completion note: when r2 response (17-byte command respons e) is required, a timeout is generated during response reception if the ctsel0 bit is set to 0. therefore, set the ctsel0 bit to 1. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1044 of 1458 rej09b0033-0300 31.3.11 data timeout register (dtoutr) dtoutr specifies a cycle to generate a data timeout. the 16-bit counter (dtoutc) and a prescaler count the peripheral clock to monitor the data timeout. the prescaler always counts the peripheral clock, and outputs a count pulse for every 10000 peripheral clocks. the initial value of dtoutc is 0, and dtoutc starts counting the pres caler output from the start of the command sequence. dtoutc is cleared when the command sequence has ended, or when the command sequence has been aborted by setting the cmdoff bit to 1, after which dtoutc stops counting the prescaler output. when the command sequence does not end, dt outc continues counting the prescaler output, and enters the data timeout error states when th e number of prescaler out put reaches the number specified in dtoutr. when the dterie bit in intcr1 is set to 1, the dteri flag in intstr1 is set. to perform data timeout error handling , the command sequence should be aborted by setting the cmdoff bit to 1, and then the dteri flag should be cleared to prevent extra-interrupt generation. for a command with data busy state, as the co mmand sequence is terminated before entering the data busy state, data timeout cannot be monitored. timeout in the data busy state should be monitored by firmware. when dtoutr is set to 0, a data timeout is generated immediately after the command sequence has started. bit bit name initial value r/w description 15 to 0 dtoutr all 1 r/w data timeout time/10000 data timeout time is determi ned by peripheral clock cycle dtoutr setting value 10000. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1045 of 1458 rej09b0033-0300 31.3.12 card status register (cstr) cstr indicates the mmcif status du ring command sequence execution. bit bit name initial value r/w description 7 busy 0 r command busy indicates command execution state. when the cmdoff bit in opcr is set to 1, this bit is cleared to 0 because the mmcif command sequence is aborted. 0: idle state waiting for a command, or data busy state 1: command sequence execution in progress 6 fifo_ full 0 r fifo full when read data is received, this bit is set to 1 after fifo has been full. this bit is cleared to 0 when rd_conti is set to 1 or command sequence is ended. 0: the fifo is empty 1: the fifo is full 5 fifo_ empty 0 r fifo empty when write data is transmitted, th is bit is set to 1 after fifo has been empty. this bit is cleared to 0 when dataen is set to 1 or command sequence is ended. 0: the fifo includes data 1: the fifo is empty 4 cwre 0 r command register write enable indicates whether the cmdr command is being transmitted or has been transmitted. 0: the cmdr command has bee n transmitted, or the start bit in cmdstrt has not been set yet, so the new command can be written. 1: the cmdr command is waiting for transmission or is being transmitted. if the new command is written, a malfunction will result. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1046 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 dtbusy 0 r data busy indicates command execution st atus. indicates that the mmc is in the busy state during or after the command sequence of a command without data transfer, which includes the busy state in the response, or of a command with write data has been ended. 0: idle state waiting for a command, or command sequence execution in progress. 1: mmc indicates data busy after command sequence ends. 2 dtbusy_ tu undefined r data busy pin state monitors level of the dat pin and do pin. this bit is monitored to confirm whether the card is in busy state by deselecting the card in busy state, and then selecting the card, again. 0: indicates that the card is in busy state. 1: idle state waiting for command. 1 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 0 req 0 r interrupt request indicates whether an interrupt is requested. an interrupt request is the logical sum of the intstr0, intstr1, and intstr2 flags. the intstr0, intstr1, and intstr2 flags are set by the enable bits in intcr0, intcr1, and intcr2. 0: no interrupts requested 1: an interrupt is requested section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1047 of 1458 rej09b0033-0300 31.3.13 interrupt control regist ers 0 and 1 (intcr0 and intcr1) intcr enable or disable each flag set of intstr0 and intstr1 and interrupts. ? intcr0 bit bit name initial value r/w description 7 feie 0 r/w fifo empty flag enable 0: disables fifo empty flag setting 1: enables fifo empty flag setting 6 ffie 0 r/w fifo full flag enable 0: disables fifo full flag setting 1: enables fifo full flag setting 5 drpie 0 r/w data response end flag enable 0: disables data response end flag setting 1: enables data response end flag setting 4 dtie 0 r/w data transfer end flag enable 0: disables data transfer end flag setting 1: enables data transfer end flag setting 3 crpie 0 r/w command response end flag enable 0: disables command response end flag setting 1: enables command response end flag setting 2 cmdie 0 r/w command output end flag enable 0: disables command output end flag setting 1: enables command output end flag setting 1 dbsyie 0 r/w data busy end flag enable 0: disables data busy end flag setting 1: enables data busy end flag setting 0 btie 0 r/w multiblock transfer end flag enable 0: disables multiblock transfer end flag setting 1: enables multiblock transfer end flag setting section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1048 of 1458 rej09b0033-0300 ? intcr1 bit bit name initial value r/w description 7 intrq2e 0 r/w int_err_n interrupt enable 0: disables int_err_n interrupt 1: enables int_err_n interrupt 6 intrq1e 0 r/w int_tran_n interrupt enable 0: disables int_tran_n interrupt 1: enables int_tran_n interrupt 5 intrq0e 0 r/w int_fstat_n interrupt enable 0: disables int_fstat_n interrupt 1: enables int_fstat_n interrupt 4 ? 0 ? reserved this bit is always read as 0. the write value should always be 0. 3 wrerie 0 r/w write error flag enable 0: disables write error flag setting 1: enables write error flag setting 2 crcerie 0 r/w crc error flag enable 0: disables crc error flag setting 1: enables crc error flag setting 1 dterie 0 r/w data timeout error flag enable 0: disables data timeout error flag setting 1: enables data timeout error flag setting 0 cterie 0 r/w command timeout error flag enable 0: disables command timeout error flag setting 1: enables command timeout error flag setting section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1049 of 1458 rej09b0033-0300 31.3.14 interrupt status registers 0 and 1 (intstr0 and intstr1) intstr enable or disable mmcif interrupts. ? intstr0 bit bit name initial value r/w description 7 fei 0 r/(w) * fifo empty flag [setting condition] when fifo becomes empty wh ile feie = 1 and write data is transmitted. (when the fifo_empty bit in cstr is set.) [clearing condition] write 0 after reading fei = 1. 6 ffi 0 r/(w) * fifo full flag [setting condition] when fifo becomes full while ffie = 1 and read data is received. (when the fifo_full bit in cstr is set.) [clearing condition] write 0 after reading ffi = 1. 5 drpi 0 r/(w) * data response flag [setting condition] when the crc status is received while drpie = 1. [clearing condition] write 0 after reading drpi = 1. 4 dti 0 r/(w) * data transfer end flag [setting condition] when the number of bytes of data transfer specified in tbcr ends while dtie = 1. [clearing condition] write 0 after reading dti = 1. 3 crpi 0 r/(w) * command response reception end flag [setting condition] when command response reception ends while crpie = 1. [clearing condition] write 0 after reading crpi = 1. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1050 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 cmdi 0 r/(w) * command transmit end flag [setting condition] when command transmission ends while cmdie = 1. [clearing condition] write 0 after reading cmdi = 1. 1 dbsyi 0 r/(w) * data busy end flag [setting condition] when data busy state ends while dbsyie = 1. [clearing condition] write 0 after reading dbsyi = 1. 0 bti 0 r/(w) * multiblock transfer end flag [setting condition] when the number of bytes of data transfer specified by tbcr after tbncr has been decremented to 0 ends while btie = 1. [clearing condition] write 0 after reading bti = 1. note: * cleared by writing 0 after reading 1. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1051 of 1458 rej09b0033-0300 ? intstr1 bit bit name initial value r/w description 7 to 4 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. 3 wreri 0 r/(w) * write error flag [setting condition] when a status error for transmit data response (write error) is detected while wreie = 1. [clearing condition] write 0 after reading wrei = 1. note: when the write error occurs, halt the command sequence by setting the cmdoff bit to 1. 2 crceri 0 r/(w) * crc error flag [setting condition] when a crc error for command response or receive data, and crc status error for transmission data response are detected while crcerie = 1. for any non-r2 command response, crc is checked when the rty4 in rsptyr is set for enabling. for the r2 command response, crc is not checked; therefore, this flag is not set. [clearing condition] write 0 after reading crceri = 1. note: when the crc error occurs, halt the command sequence by setting the cmdoff bit to 1. 1 dteri 0 r/(w) * data timeout error flag [setting condition] when a data timeout error specified in dtoutr occurs while dterie = 1. [clearing condition] write 0 after reading dteri = 1. note: when the data timeout error occurs, clear the dteri flag after halting the command sequence by setting the cmdoff bit to 1. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1052 of 1458 rej09b0033-0300 bit bit name initial value r/w description 0 cteri 0 r/(w) * command timeout error flag [setting condition] when a command timeout error specified in tocr occurs while cterie = 1. [clearing condition] write 0 after reading cteri = 1. note: when the command timeout error occurs, clear the cteri flag after halting the command sequence by setting the cmdoff bit to 1. note: * cleared by writing 0 after reading 1. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1053 of 1458 rej09b0033-0300 31.3.15 transfer clock control register (clkon) clkon controls the transfer clock frequency and clock on/off. the 33-mhz peripheral clock is needed, and bits csel3 to csel0 should be set to 0001 for a 16.5-mbps transfer clock of the mmcif. at this time, transfer should be performed by sufficiently slow transfer clock in the open drain state. in the command sequence, do not perform clock on/off or frequency modification. bit bit name initial value r/w description 7 clkon 0 r/w clock on 0: stops the transfer clock output from the clk/sclk pin. 1: outputs the transfer clo ck from the clk/sclk pin. 6 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 csel3 csel2 csel1 csel0 0 0 0 0 r/w r/w r/w r/w transfer clock frequency select 0000: setting prohibited 0001: uses the 1/2-divided peripheral clock as a transfer clock. 0010: uses the 1/4-divided peripheral clock as a transfer clock. 0011: uses the 1/8-divided peripheral clock as a transfer clock. 0100: uses the 1/16-divided peripheral clock as a transfer clock. 0101: uses the 1/32-divided peripheral clock as a transfer clock. 0110: uses the 1/64-divided peripheral clock as a transfer clock. 0111: uses the 1/128-divided peripheral clock as a transfer clock. 1000: uses the 1/256-divided peripheral clock as a transfer clock. 1001 to 1111: setting prohibited note: the maximum operating frequency of the peripheral clock is 33.34 mhz. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1054 of 1458 rej09b0033-0300 31.3.16 vdd/open-drain control register (vdcnt) vdcnt can use mmc_odmod signal to control open drain. the mmc_vddon signal output can be used to control the mmc power supply (vdd) on/off. bit bit name initial value r/w description 7 vddon 0 r/w specifies mmc_vddon signal to be used as a mmc power supply (vdd) control signal. 0: mmc_vddon is low signal output 1: mmc_vddon is high signal output 6 odmod 0 r/w specifies mmc_odmod signal to be used to control cmd output open drain in mmc mode. 0: mmc_odmod signal is low signal output 1: mmc_odmod signal is high signal output 5 to 0 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. 31.3.17 data register (dr) dr is a register for reading/writing fifo data. word/byte access is enabled to addresses of this register. bit bit name initial value r/w description 15 to 0 (7 to 0) dr undefined r/w register for reading/writing fifo data. word/byte access is enabled. however, byte access is disabled to address 2n+1. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1055 of 1458 rej09b0033-0300 31.3.18 fifo pointer clear register (fifoclr) the fifo write/read pointe r is cleared by writing any value to fifoclr. bit bit name initial value r/w description 7 to 0 fifoclr ? w the fifo pointer is cleared by writing any value to this register. 31.3.19 dma control register (dmacr) dmacr sets dma request signal output. dmaen enables/disables a dma request signal. the dma request signal is output by a value that has been set to bits set2 to set0. set this register before executing a multiblock transfer command (cmd18 or cmd25). auto mode cannot be used for open-ended multiblock transfer. bit bit name initial value r/w description 7 dmaen 0 r/w 0: disables output of dma request signal. (initial value) 1: enables output of dma request signal. 6 auto 0 r/w this bit is set when the pre-defined multiblock transfer using dma transfer is performed in auto mode. 0: auto mode is not used. 1: auto mode is used. 5 to 3 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1056 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 1 0 set2 set1 set0 0 0 0 r/w r/w r/w sets dma request signal assert condition. 000: not output (initial value) 001: fifo remained data is 1/ 4 or less of fifo capacity. 010: fifo remained data is 1/ 2 or less of fifo capacity. 011: fifo remained data is 3/ 4 or less of fifo capacity. 100: fifo remained data is at least 1 byte. 101: fifo remained data is 1/4 or more of fifo capacity. 110: fifo remained data is 1/2 or more of fifo capacity. 111: fifo remained data is 3/4 or more of fifo capacity. 31.3.20 interrupt cont rol register 2 (intcr2) the intcr2 enables or di sables an interrupt. bit bit name initial value r/w description 7 intrq3e 0 r/w int_frdy_nb interrupt enable 0: interrupt disabled 1: interrupt enabled 6 to 1 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. 0 frdyie 0 r/w fifo preparation end flag enable 0: disables fifo preparation end flag set 1: enables fifo preparation end flag set section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1057 of 1458 rej09b0033-0300 31.3.21 interrupt status register 2 (intstr2) the intstr2 controls the mmcif interrupt output. if setting condition is satisfied, frdyi is set even though it has been cleared. disable flag setting by frdyie in intcr2 before clearing frdyi. bit bit name initial value r/w description 7 to 2 ? all 0 ? reserved these bits are always read as 0. the write value should always be 0. 1 frdy_tu 1 r when frdyi setti ng condition is satisfied. read value 0: when fifo remained data is less than data set as assert condition by dmacr 1: when fifo remained data is other than data set as assert condition by dmacr 0 frdyie 0 r/(w) * fifo preparation end flag enable [setting condition] when fifo remained data is less than data set as assert condition by dmacr while frdyie = 1 and the dmaen bit is set. [clearing condition] write 0 after reading frdyi = 1. note: * cleared by writing 0 after reading 1. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1058 of 1458 rej09b0033-0300 31.4 operation the multimediacard is an external storage me dia that can be easily disconnected. the mmcif controls data transfer with the multimediacard, and operates in mmc mode. insert the mmc and turn on the power supply. then operate the mmcif by applying transfer clocks after setting an appropriate transfer clock frequency. the mmc_vddon signal and mmc_odmod signal can be used for mmc power control and open drain mode control, respectively. the series of operations from command sending, command response reception, data transmission/reception, and data response re ception is called the command sequence. the command sequence starts from sending a command by setting the start bit in cmdstrt to 1, and ends when all necessary data transmissi on/reception and response reception has been completed. the mmc supports the data busy stat e in which only specific command is accepted to program/erase the flash memory in the mmc du ring command sequence execution and after command sequence execution has ended. the data bu sy state is indicated by a 0 output from the mmc side to the dat pin in mmc mode. note: do not connect or disconnect the mmc during command sequence or data busy. 31.4.1 operations in mmc mode mmc mode is an operating mode in which the transfer clock is output from the mmc_clk pin, command transmission/response receive occurs via the mmc_cmd pin, and data is transmitted/received via the mmc_dat pin. in this mode the next command can be issued while data is being transmitted/received. this feature is applied to the multiblock transf er and stream transfer. in this case, the ne xt command is the cmd12 command, which aborts the current command sequence. in mmc mode, a broadcast command that simultan eously issues a comman d to multiple mmcs is supported. after the information for the mmc that is inserted by using the broadcast command is acknowledged, a relative address is given to each mmc. one mmc is selected by the relative address, other mmcs are deselected, and variou s commands are issued to the selected mmc. commands in mmc mode is basically classified into three types: broadcast, relative address, and flash memory operation commands. the mmc is op erated by issuing a command according to card status. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1059 of 1458 rej09b0033-0300 (1) operation of broadcast commands the cmd0, cmd1, cmd2, and cmd4 are broadcas t commands. the sequence assigning relative addresses to individual mmcs consists of th ese commands and the cmd3 command. in this sequence, the cmd output format is open drain, and the command response is wired-or. in this case, the transfer clock frequency should be set sufficiently slow. ? all mmcs are initialized to the idle state by the cmd0. ? the operation condition register (ocr) of a ll mmcs is read via wired-or, and mmcs that cannot operate are deac tivated by the cmd1. the deactivated mmcs enter the ready state. ? the card identification (cid) of all mmcs in the ready state is read via wired-or by the cmd2. the individual mmc compares its cid and data on the mmc_cmd, and if different, aborts cid output. a single mmc in which the cid can be entirely output enters the acknowledge state. ? a relative address (rca) is given to the mmc in the acknowledge state by the cmd3. the mmc to which the rca is given enters the standby state. ? cmd2 and cmd3 are repeated, assigning rcas to all mmcs in the ready state, entering each into the standby state. note: when the r2 response (17-byte command response) is required, the ctsel0 bit should be set to 1 since a timeout is generated during response reception if the ctsel0 bit is set to 0. (2) operation of relative address commands the cmd7, cmd9, cmd10, cmd13, cmd15, cmd39, and cmd55 are relative address commands that address the mmc by rca. the rela tive address commands are used to read mmc administration information and original informa tion, and to change the specific card status. the cmd7 sets one addressed mmc to the transfer state, and other mmcs to the standby state. only the mmc in the transfer st ate can execute a flash-memory op eration command other than the broadcast and relative address commands. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1060 of 1458 rej09b0033-0300 (3) operation of commands that do not require command response some broadcast commands do not require command response. figure 31.2 shows an exampl e of the command sequence for commands that do not require command response. figure 31.3 shows the operational flow for commands that do not require command response. ? the settings needed to is sue a command are made. ? the start bit in cmdstrt is set to 1 to start command transmission. ? the end of command sequence is detected by poling the busy flag in cstr or by the command output end interrupt (cmdi). clk cmd dat cmdstrt (start) intstr0 (cmdi) cstr (cwre) (busy) (req) input/output pins command output (48 bits) command transmission started command transmission ended command transmission period command sequence period figure 31.2 example of co mmand sequence for commands that do not require command response section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1061 of 1458 rej09b0033-0300 ye s no start command sequence set command data to cmdr0 to cmdr4 set command type to cmdtyr set command response type to rsptyr set 1 to cmdstrt/(start) is (cmdi) interrupt detected? end command sequence figure 31.3 operational flow for comman ds that do not require command response section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1062 of 1458 rej09b0033-0300 (4) operation of commands without data transfer the broadcast, relative address, and flash memo ry operation commands include a number of commands that do not include da ta transfer. such commands execute the desired data transfer using command arguments and command responses. for a command that is related to time- consuming processing such as flash memory write/erase, th e mmc indicates the data busy state via the mmc_dat. figures 31.4 and 31.5 show examples of the command sequence for commands without data transfer. figure 31.6 shows the operational flow for commands without data transfer. ? settings needed to issue a command are made. ? the start bit in cmdstrt is set to start command transmission. ? command transmission complete can be conf irmed by the command output end interrupt (cmdi). ? a command response is received from the mmc. ? if the mmc does not return the command response , the command response is detected by the command timeout error (cteri). ? the end of a command sequence is detected by poling the busy flag in cstr or by the command response end interrupt (crpi). ? whether the data busy state is entered or not is determined by the dtbusy bit in cstr. if the data busy state is entered, the end of the data busy state is detected by the data busy end interrupt (dbsyi). ? when the crc error (crceri) or command time out error (cteri) occurs, write 1 to the cmdoff bit. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1063 of 1458 rej09b0033-0300 clk cmd dat cmdstrt (start) intstr0 (cmdi) cstr (busy) (req) (crpi) (dbsyi) ( dtbusy_tu ) ( dtbusy ) input/output pins command output (48 bits) command transmission started command response reception (no busy state) command transmission period command sequence execution period response reception completed (cwre) figure 31.4 example of command sequen ce for commands with out data transfer (no data busy state) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1064 of 1458 rej09b0033-0300 clk cmd dat cmdstrt (start) intstr0 (cmdi) cstr (cwre) (busy) (req) (crpi) (dbsyi) (dtbusy_tu) (dtbusy) input/output pins command output (48 bits) command transmission started command response reception command transmission period command sequence execution period response reception completed busy state completed (busy state) data busy period figure 31.5 example of command sequen ce for commands with out data transfer (with data busy state) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1065 of 1458 rej09b0033-0300 write command type to cmdtyr write response type to rsptyr write 1 to cmdstrt write 1 to cmdoff crceri interrupt generated? * r1b response? dbsyi interrupt generated? dtbusy detected? command sequence start write command to cmdr0 to cmdr4 ye s ye s ye s ye s ye s ye s no no no no no no crpi interrupt generated? command sequence end cteri interrupt generated? note * : for the r2 command response, no crc check is performed by hardware. therefore, perform crc checking by software to see if there is an error. figure 31.6 operational flowchar t for commands without data transfer section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1066 of 1458 rej09b0033-0300 (5) commands with read data flash memory operation commands include a nu mber of commands involving read data. such commands confirm the card status by the command argument and command response, and receive card information and flash memo ry data from the dat pin. for multiblock transfer, there ar e two methods. one is the ope n-ended method in which the instruction for continuing/suspending the command sequence is made by suspending the transfer for every block. another one is the pre-defined method in which the transfer is performed after setting the number of blocks to be transferred. the command sequence is suspen ded when fifo is full between the block transfers. when the command sequence is suspen ded, data in the receive data fifo is processed, if necessary, and the command sequence is then continued. figures 31.7 to 31.10 show the examples of th e command sequence for commands with read data. figures 31.11 to 31.14 show the operational flowcharts for commands with read data. ? settings needed to issue a comma nd are made. fifo is cleared. ? the start bit in cmdstrt is set to 1 to start command transmission. ? command transmission complete can be conf irmed by the command output end interrupt (cmdi). ? a command response is received from the mmc. ? if the mmc does not return the command response , the command response is detected by the command timeout error (cteri). ? read data from the mmc is received. ? the suspension inter-blocks in multiblock transfer and suspension according to the fifo full are detected by the data transfer end interrupt (dti) and fifo full interrupt (ffi), respectively. to continue the command sequence, the rd_conti bit in opcr should be set to 1. to end the command sequence, the cmdoff bit in opcr should be set to 1, and the cmd12 should be issued. note that the cmd12 is not required other than when the sequence is suspended in pre-defined multiblock transfer. ? the end of the command sequence is detected by polling the busy flag in cstr or by the data transfer end flag (dti) or the multiblock transfer (pre-defined) end flag (bti). ? when the crc error (crceri) or command time out error (cteri) occurs during command response reception, write 1 to the cmdoff bit. ? when the crc error (crceri) or data timeout error (dteri) occurs during the read data reception, write 1 to the cm doff bit to clear the fifo. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1067 of 1458 rej09b0033-0300 note: in multiblock transfer, if you terminate the command sequence (by writing 1 in the cmdoff bit) before the command response reception is completed (crpi = 1), the command response cannot be received co rrectly. to receive a command response, continue the command sequence (by setting the rd_conti bit to 1) until the reception of the command response is completed. clk cmd dat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (req) (crpi) (dti) (ffi) (fifo_full) cmd17(read_single_block) opcr (rd_conti) input/output pins command command response read data command transmission started single block read command execution sequence figure 31.7 example of command sequence for commands with read data (block size fifo size) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1068 of 1458 rej09b0033-0300 clk cmd dat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (req) (crpi) (dti) (ffi) (fifo_full) cmd17 (read_single_block) opcr (rd_conti) input/output pins transfer clock transmission halted transfer clock transmission resumed command response command block data reception suspended read data read data block data reception resumed reading data from fifo single block read command execution sequence command transmission started figure 31.8 example of command sequence for commands with read data (block size > fifo size) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1069 of 1458 rej09b0033-0300 clk cmd dat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (req) (crpi) (dti) (ffi) (fifo_full) cmd18(read_multiple_block) cmd12(stop_transmission) opcr (rd_conti) input/output pins transfer clock transmission halted transfer clock transmission resumed command response command response command command read data read data read data command transmission started block data reception ended multiblock read command execution sequence stop command execution sequence figure 31.9 example of command sequence for commands with read data (multiblock transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1070 of 1458 rej09b0033-0300 clk cmd dat cmdstrt ( start ) intstr0 ( cmdi ) ( cmdoff ) cstr ( cwre ) ( busy ) ( req ) ( crpi ) ( dti ) ( ffi ) ( fifo_full ) cmd11(read_dat_until_stop) cmd12(stop_transmission) opcr ( rd_conti ) input/output pins transfer clock transmission halted transfer clock transmission resumed transfer clock transmission resumed command response command command response command read data read data read data stop command execution sequence command transmission started data reception resumed data reception suspended data reception ended read data from fifo stream read command execution sequence figure 31.10 example of command se quence for commands with read data (stream transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1071 of 1458 rej09b0033-0300 command sequence start command sequence end fifo clear write transfer block size to tbcr execute cmd16 execute cmd17 (cmdr to cmdstrt) read response register read data from fifo fifo clear write 1 to cmdoff write 1 to rd_conti read data from fifo write 1 to cmdoff ye s ye s no ye s no ye s no ye s no no ye s no ye s no ye s ye s no no ye s no ye s no does cmd16 end successfully? is crceri interrupt generated? is crpi interrupt generated? cap len - cap n(ffi) is response status normal? is dteri interrupt generated? is crceri interrupt generated? is dteri interrupt generated? is dti interrupt generated? is ffi interrupt generated? is cteri interrupt generated? * block length (byte) len: cap: n(ffi): fifo size (byte) the number of feis from the start of read sequence note: * figure 31.11 operational flowchart for commands with read data (single block transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1072 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 execute cmd18 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? command sequence start fifo clear ye s ye s ye s ye s no no is crceri interrupt generated? ye s no no no is response status normal? does cmd16 end successfully? [1] [2] figure 31.12 operational flowchart for commands with read data (open-ended multiblock transfer) (1) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1073 of 1458 rej09b0033-0300 [1] [2] write 1 to rd_conti read data from fifo read data from fifo write 1 to cmdoff execute cmd12 write 1 to cmdoff write 1 to cmdoff execute cmd12 fifo clear ye s no ye s no ye s ye s ye s ye s no no no no is crceri interrupt generated? is dteri interrupt generated? is dteri interrupt generated? is dti interrupt generated? is ffi interrupt generated? is next block read? block length (byte) len: cap: n(ffi): fifo size (byte) the number of ffis from the start of read sequence n(dti): the number of dtis from the start of read sequence note: * cap len (1 + n(dti)) - cap n(ffi) command sequence end * ye s no figure 31.12 operational flowchart for commands with read data (open-ended multiblock transfer) (2) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1074 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 write the number of transfer blocks to tbcr execute cmd23 execute cmd18 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? command sequence start fifo clear ye s ye s ye s ye s no no is crceri interrupt generated? ye s no no no ye s no is response status normal? does cmd16 end successfully? does cmd23 end successfully? [1] [2] figure 31.13 operational flowchart for commands with read data (pre-defined multiblock transfer) (1) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1075 of 1458 rej09b0033-0300 [1] [2] write 1 to rd_conti read data from fifo read data from fifo write 1 to cmdoff write 1 to cmdoff write 1 to cmdoff execute cmd12 fifo clear ye s no no ye s ye s no ye s ye s ye s ye s ye s no no no no no is crceri interrupt generated? is dteri interrupt generated? is dteri interrupt generated? is dti interrupt generated? tbncr value = n(dti)? is ffi interrupt generated? is bti interrupt generated? block length (byte) len: cap: n(ffi): fifo size (byte) the number of ffis from the start of read sequence n(dti): the number of dtis from the start of read sequence note: * cap len (1 + n(dti)) - cap n(ffi) * command sequence end figure 31.13 operational flowchart for commands with read data (pre-defined multiblock transfer) (2) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1076 of 1458 rej09b0033-0300 command sequence start command sequence end fifo clear execute cmd11 (cmdr to cmdstrt) read response register read data from fifo fifo clear write 1 to cmdoff write 1 to cmdoff execute cmd12 execute cmd12 write 1 to rd_conti read data from fifo write 1 to cmdoff ye s ye s no ye s no ye s no no ye s ye s no no ye s no is crceri interrupt generated? is crpi interrupt generated? is dteri interrupt generated? is response status normal? is ffi interrupt generated? is data read completed? is cteri interrupt generated? figure 31.14 operational flowchart for commands with read data (stream transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1077 of 1458 rej09b0033-0300 (6) commands with write data flash memory operation commands include a number of commands involving write data. such commands confirm the card status by the co mmand argument and command response, and transmit card information and flash memory data fr om the dat pin. for a command that is related to time-consuming processing such as flash me mory programming, the mmc indicates the data busy state via the dat pin. for multiblock transfer, there are two methods. one is the open-ended method in which the instruction for continuing/suspending the command sequence is made by suspending the transfer for every block. another one is the pre-defined method in which the transfer is performed after setting the number of blocks to be transferred. the command sequence is suspende d when fifo is full between the block transf ers. when the command sequence is suspen ded, data in the receive data fifo is processed, if necessary, and the command sequence is then continued. figures 31.15 to 31.18 show examples of the command sequence for commands with write data. figures 31.19 to 31.22 show the operational flowcharts for commands with write data. ? settings needed to issue a command are made. the fifo is cleared. ? the start bit in cmdstrt is set to 1 to start command transmission. ? a command response is received from the mmc. ? if the mmc does not return the command response , the command response is detected by the command timeout error (cteri). ? write data is set to the fifo. ? the dataen bit in opcr is set to start write data transmission. ? suspension inter-blocks in multib lock transfer and suspension according to the fifo empty are detected by the data response end interrupt flag (drpi) and fifo empty interrupt flag (fei), respectively. to continue the co mmand sequence, data should be written to the fifo, and the dataen bit in opcr should be set to 1. to end the command sequence, the cmdoff bit in opcr should be set to 1, and the cmd12 should be issued. note that the cmd12 is not required other than when the sequence is suspended in pre- defined multiblock transfer. ? the end of the command sequence is detected by poling the busy flag in cstr, data response end flag (dpri), or multiblock transfer (pre-defined) end flag (bti). ? in addition, after the end of data transfer (after drpi is detected), whether the data busy state is entered or not is determined by the dtbusy bit in cstr. if the data busy state is entered, cancellation of the data busy state is detected by the data busy end interrupt (dbsyi). section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1078 of 1458 rej09b0033-0300 ? when the crc error (crceri) or command time out error (cteri) occurs during command response reception, write 1 to the cmdoff bit. ? when the crc error (crceri) or data timeout error (dteri) occurs during the write data transmission, write 1 to the cmdoff bit. clk cmd dat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (dtbusy_tu) (dtbusy) (req) (crpi) (dti) (dbsyi) (fei) (fifo_empty) cmd24 (write_single_block) opcr (dataen) (drpi) input/output pins command command response command transmission started single block write command execution sequence write data status busy figure 31.15 example of command se quence for commands with write data (block size fifo size) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1079 of 1458 rej09b0033-0300 input/output pins clk cmd dat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (dtbusy_tu) (req) single block write command execution sequence (crpi) (drpi) (dbsyi) (dti) (fei) (fifo_empty) (dtbusy) cmd24 (write_single_block) opcr (da ta en) transfer clock transmission halted transfer clock transmission resumed command transmission started write data write data busy block data transmission suspended block data transmission resumed writing data to fifo figure 31.16 example of command se quence for commands with write data (block size > fifo size) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1080 of 1458 rej09b0033-0300 clk cmd dat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (dtbusy_tu) (dtbusy) (req) (crpi) (drpi) (dbsyi) (dti) (fei) (fifo_empty) cmd25 (write_multiple_block) cmd12 (stop_transmission) opcr (dataen) input/output pins command command command response command response command transmission started write data write data write data status block data transmission started block data reception end next block data transmission started stop command execution sequence figure 31.17 example of command se quence for commands with write data (multiblock transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1081 of 1458 rej09b0033-0300 clk cmd dat cmdstrt (start) intstr0 (cmdi) (cmdoff) cstr (cwre) (busy) (dtbusy_tu) (req) (crpi) (drpi) (dbsyi) (dti) (fei) (fifo_empty) cmd20 (write_dat_until_stop) cmd12(stop_transmission) (dtbusy) opcr (dataen) input/output pins command command response command command response command transmission started write data write data write data stop command execution sequence busy tr a n s fe r clock transmission halted tr a n s fe r clock transmission halted tr a n s fe r clock transmission resumed tr a n s fe r clock transmission resumed writing data to fifo data transmission suspended data transmission suspended data transmission resumed data transmission ended stream write command execution sequence figure 31.18 example of command se quence for commands with write data (stream transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1082 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 write data to fifo write 1 to dataen cap n(fei) len * execute cmd24 (cmdr to cmdstrt) read response register is crpi interrupt generated? is crceri interrupt generated? is cteri interrupt generated? is dtbusy detected? is dbsyi interrupt is generated? is dti interrupt generated? is fei interrupt generated? is drpi interrupt generated? is crceri interrupt generated? command sequence start fifo clear ye s ye s no ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s no no no no no no no command sequence end is response status normal? write1 to cmdoff block length (byte) len: cap: n(fei): fifo size (byte) the number of feis from the start of write sequence does cmd16 end successfully? is dteri interrupt generated? ye s no no no no no note: * figure 31.19 operational flowchart for commands with write data (single block transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1083 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 execute cmd25 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? command sequence start fifo clear ye s ye s ye s ye s no is crceri interrupt generated? no ye s no no no does cmd16 end successfully? is response status normal? [1] [2] figure 31.20 operational flowchart for commands with write data (open-ended multiblock transfer) (1) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1084 of 1458 rej09b0033-0300 write 1 to cmdoff write 1 to cmdoff execute cmd12 command sequence end write 1 to dataen write data to fifo * 1 cap n(fei) - len (1 + n(drpi)) len * 2 is crceri interrupt generated? is dteri interrupt generated? is dti interrupt generated? is drpi interrupt generated? is fei interrupt generated? is dtbusy detected? is dbsyi interrupt generated? is next block written? [1] [2] ye s ye s ye s ye s ye s ye s ye s ye s ye s no no no no no no no no no block length (byte) len: cap: n(fei): fifo size (byte) the number of feis from the start of write sequence n(drpi): the number of drpis from the start of write sequence 2. notes: 1. write data of block length when block length fifo size, data of fifo size when block length > fifo size. figure 31.20 operational flowchart for commands with write data (open-ended multiblock transfer) (2) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1085 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 execute cmd25 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? command sequence start fifo clear ye s ye s ye s ye s no no no no no does cmd16 end successfully? write the number of transfer blocks to tbncr execute cmd23 ye s does cmd23 end successfully? is response status normal? [1] [2] is crceri interrupt generated? ye s no figure 31.21 operational flowchart for commands with write data (pre-defined multiblock transfer) (1) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1086 of 1458 rej09b0033-0300 write 1 to cmdoff write 1 to cmdoff write 1 to cmdoff execute cmd12 command sequence end write 1 to dataen write data to fifo * 1 cap n(fei) - len (1 + n(drpi)) len * 2 is crceri interrupt generated? is dteri interrupt generated? is dti interrupt generated? is drpi interrupt generated? is fei interrupt generated? is dtbusy detected? is dbsyi interrupt generated? tbncr = n(drpi)? is bti interrupt generated? [1] [2] ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s no no no no no no no no no no block length (byte) len: cap: n(fei): fifo size (byte) the number of feis from the start of write sequence n(drpi): the number of drpis from the start of write sequence 2. notes: 1. write data of block length when block length fifo size, data of fifo size when block length > fifo size. figure 31.21 operational flowchart for commands with write data (pre-defined multiblock transfer) (2) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1087 of 1458 rej09b0033-0300 execute cmd20 (cmdr to cmdstrt) read response register is crpi interrupt generated? is fei interrupt generated? has all data been written to fifo? is cteri interrupt generated? command sequence start fifo clear write 1 to daten write data to fifo ye s ye s ye s no no is crceri interrupt generated? ye s ye s no ye s no command sequence end is response status normal? write 1 to cmdoff execute cmd12 write 1 to cmdoff no no figure 31.22 operational flowchart for commands with write data (stream transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1088 of 1458 rej09b0033-0300 31.5 operations using dmac 31.5.1 operation of read sequence for transfer with dmac, set mmcif (dmacr) after setting dmac. transmit the read command after setting the dmacr. figures 31.23 to 31.26 show the operational flowcharts for read sequence. ? fifo is cleared and dmacr is set. ? read command transmission is started. ? read data is received from the mmc. ? after read sequence, fifo include s data. if necessary, 100 is written to the set2 to set0 bits in dmacr to read every data in fifo. ? the end of the transfer with the dmac is co nfirmed, and 0 is set to the dmaen bit in dmacr. ? when the crc error (crceri) or the command timeout error (cteri) occurs during command response reception, write 1 to the cmdoff bit and set dmacr to h'00. ? when the crc error (crceri) or the data timeout error (dteri) occurs during read data reception, write 1 to the cmdoff bit and set dmacr to h'00 to clear the fifo. when the dma is in use, and detected that read ing is completed successfu lly after block transfer in pre-defined multiblock transfer, reading the next block is automatically performed again by setting the auto bit in dmacr to 1. figures 31.27 shows the operational flowchart for pre- defined multi read sequences in mmc mode. ? fifo is cleared. ? the number of blocks is set to tbncr. ? dmacr is set. ? read command transmission is started. ? command response and read data are received from the mmc. ? if the mmc does not return the command response , it detected by the command timeout error flag (cteri). ? command sequence end is detect ed by polling the busy flag in cstr or the multiblock transfer (pre-defined) end flag (bti). ? errors during command sequence (data reception) are detected by the crc error flag and the data timeout error flag. when these flags are detected, set the cmdoff bit in opcr to 1 to issue the cmd12 command and su spend the command sequence. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1089 of 1458 rej09b0033-0300 ? after read sequence, fifo includes data. if necessary, 100 is written to the set2 to set0 bits in dmacr to read every data in fifo. ? the end of the transfer with the dmac is co nfirmed, and 0 is set to the dmaen bit in dmacr. ? when the crc error (crceri) or the command timeout error (cteri) occurs during command response reception, write 1 to the cmdoff bit and set dmacr to h'00. ? when the crc error (crceri) or the data timeout error (dteri) occurs during read data reception, write 1 to the cmdoff bit and set dmacr to h'00 to clear the fifo. notes: 1. access from the dmac the fifo should be performed by byte or longword data. 2. in multiblock transfer, no normal command response can be received if you terminate the command sequence (by writing 1 in the cmdoff bit) before the command response end interrupt (crpi). to receive a normal command response, you need to continue the command sequence (by setting the rd_conti bit to 1) until the reception of the command re sponse is completed. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1090 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 set dmac set dmacr (mmcif) set dmacr to h'84 execute cmd17 (cmdr to cmdstrt) read response register is crceri interrupt generated? is cteri interrupt generated? is dti interrupt generated? is crceri interrupt generated? command sequence start fifo clear ye s ye s no no ye s ye s no ye s ye s no ye s no no no is crpi interrupt generated? ye s no set dmacr to h'00 command sequence end is response status normal? does dma transfer end? write 1 to cmdoff write 1 to cmdoff set dmacr to h'00 fifo clear set dmacr to h'00 does cmd16 end successfully? is dteri interrupt generated? ye s no figure 31.23 operational flowchart for read sequence (single block transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1091 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 execute cmd18 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? command sequence start fifo clear set dmac set dmacr (mmcif) ye s ye s ye s ye s no no is crceri interrupt generated? ye s no no no is response status normal? does cmd16 end successfully? [1] [2] figure 31.24 operational flowchart for read sequence (open-ended multiblock transfer) (1) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1092 of 1458 rej09b0033-0300 write 1 to rd_conti write 1 to cmdoff execute cmd12 set dmacr to h'00 write 1 to cmdoff set dmacr to h'00 fifo clear write 1 to cmdoff execute cmd12 set dmacr to h'00 set dmacr to h'84 ye s ye s no ye s ye s no ye s no no no is crceri interrupt generated? is dteri interrupt generated? does dma transfer end? is dti interrupt generated? is next block read? command sequence end [1] [2] figure 31.24 operational flowchart for read sequence (open-ended multiblock transfer) (2) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1093 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 set the number of transfer blocks to tbncr execute cmd23 execute cmd18 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? command sequence start fifo clear ye s ye s ye s ye s no no is crceri interrupt generated? ye s no no no ye s no is response status normal? does cmd16 end successfully? does cmd23 end successfully? set dmac set dmacr (mmcif) [1] [2] figure 31.25 operational flowchart for read sequence (pre-defined multiblock transfer) (1) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1094 of 1458 rej09b0033-0300 write 1 to rd_conti write 1 to cmdoff execute cmd12 set dmacr to h'00 write 1 to cmdoff set dmacr to h'00 fifo clear write 1 to cmdoff set dmacr to h'00 set dmacr to h'84 ye s ye s no ye s ye s ye s ye s no no no no no is crceri interrupt generated? is dteri interrupt generated? does dma transfer end? is dti interrupt generated? tbncr = n(dti)? is bti interrupt generated? command sequence end * n(dti): the number of dtis from the start of read sequence note: * [1] [2] figure 31.25 operational flowchart for read sequence (pre-defined multiblock transfer) (2) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1095 of 1458 rej09b0033-0300 execute cmd11 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? command sequence start fifo clear set dmac set dmacr (mmcif) ye s ye s ye s no no is crceri interrupt generated? ye s no ye s no ye s no command sequence end is response status normal? write 1 to cmdoff execute cmd12 set dmacr to h'00 write 1 to cmdoff write 1 to cmdoff execute cmd12 fifo clear is dteri interrupt generated? does dma transfer end? no figure 31.26 operational flowchart for rear sequence (stream read transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1096 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 write the number of transfer blocks to tbncr execute cmd23 execute cmd18 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? command sequence start fifo clear ye s ye s ye s ye s no no is crceri interrupt generated? ye s no no no ye s no is response status normal? does cmd16 end successfully? does cmd23 end successfully? set dmac set dmacr (mmcif) [1] [2] figure 31.27 operational flowchart for pre-defined multiblock read transfer in auto mode (1) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1097 of 1458 rej09b0033-0300 write 1 to cmdoff execute cmd12 set dmacr to h'00 write 1 to cmdoff set dmacr to h'00 fifo clear write 1 to cmdoff set dmacr to h'00 set dmacr to h'84 ye s ye s no ye s ye s no no no is crceri interrupt generated? is dteri interrupt generated? does dma transfer end? is bti interrupt generated? command sequence end [1] [2] figure 31.27 operational flowchart for pre-defined multiblock read transfer in auto mode (2) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1098 of 1458 rej09b0033-0300 31.5.2 operation of write sequence for transfer with dmac, set mmcif (dmacr) af ter setting dmac. the fifo ready flag is generated after dmacr is set and data more than threshold set in dmacr is written to the fifo. start transmission to the mmc after setting the flag . figures 31.28 to 31.31 show the operational flowcharts for write sequence in mmc mode. ? fifo is cleared. ? write command is transmitted. ? dmacr is set and write data is set to the fifo. ? confirmed that the data more than dmacr setti ng condition is written to the fifo by the fifo ready flag (frdyi), or that all data is written to the fifo by the dmac, and then the dataen bit in opcr is set to 1 to start write data transmission. ? the end of the transfer with the dmac is co nfirmed, and 0 is set to the dmaen bit in dmacr. ? when the crc error (crceri) or the command timeout error (cteri) occurs during command response reception, write 1 to the cmdoff bit. ? when the crc error (crceri), write error (wre ri), or data timeout error (dteri) occurs during write data transmission, 1 is written to the cmdoff bit and dmacr is set to h'00 to clear the fifo. when the dma is in use, an interrupt between blocks in pre-defined multiblock transfer can be processed by hard by setting the auto bit in dmacr to 1. figure 31.32 shows the operational flowchart for pre-defined multi write sequence in mmc mode. ? fifo is cleared. ? the number of blocks is set to tbncr. ? the start bit in cmdstrt is set to 1 and command transmission is started. ? command response is received from the mmc. ? if the mmc does not return the command response , it detected by the command timeout error flag (cteri). ? dmacr is set and write data is set to the fifo. ? the end of the transfer with the dmac is co nfirmed, and 0 is set to the dmaen bit in dmacr. ? command sequence end is detect ed by polling the busy flag in cstr or the multiblock transfer (pre-defined) end flag (bti). section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1099 of 1458 rej09b0033-0300 ? errors during command sequen ce (data transmission) are det ected by the crc error flag (crceri) or the data timeout error flag. when in terrupts are detected, set the cmdoff bit in opcr to 1 to issue the cmd12 command and suspend the command sequence. ? not in the data busy state is confirmed. if the da ta busy state is entered, the data busy state is detected by the data busy end flag (dbsyi). ? after data transfer (after drpi is detected), check whether the data busy state is entered. if the data busy state is entered, the end of the data bu sy state is detected by the data busy end flag (dbsyi). ? the cmdoff bit is set to 1 and command sequence is ended. ? when the crc error (crceri) or the command timeout error (cteri) occurs during command response reception, write 1 to the cmdoff bit. ? when the crc error (crceri), write error (w reri), or the data timeout error (dteri) occurs during write data transmission, write 1 to the cmdoff bit and set dmacr to h'00 to clear the fifo. note: access from the dmac to the fifo should be performed by byte or longword data. section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1100 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 set dmac set dmacr (mmcif) execute cmd24 (cmdr to cmdstrt) read response register is crceri interrupt generated? is cteri interrupt generated? is drpi interrupt generated? is crceri or wreri interrupt generated? command sequence start fifo clear ye s ye s no no ye s no ye s ye s no ye s no no no is crpi interrupt generated? ye s ye s no ye s ye s no command sequence end is response status normal? is dbsyi interrupt generated? is dtbusy detected? write 1 to cmdoff does cmd16 end successfully? is dteri interrupt generated? ye s no write 1 to daten does dma transfer end? ye s ye s set dmacr to h'00 is frdyi interrupt is generated or does dma transfer end? no no is dti interrupt generated? ye s no figure 31.28 operational flowchart fo r write sequence (single block transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1101 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 execute cmd25 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? command sequence start fifo clear ye s ye s ye s ye s no no is crceri interrupt generated? ye s no no no is response status normal? does cmd16 end successfully? set dmac set dmacr (mmcif) [1] [2] figure 31.29 operational fl owchart for write sequence (open-ended multiblock transfer) (1) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1102 of 1458 rej09b0033-0300 write 1 to cmdoff execute cmd12 set dmacr to h'00 write 1 to cmdoff fifo clear write 1 to cmdoff execute cmd12 ye s ye s no ye s no ye s no no ye s ye s no is crceri or wreri interrupt generated? is dteri interrupt generated? is drpi interrupt generated? is dbsyi interrupt generated? is dtbusy detected? is next block written? write 1 to daten does dma transfer end? ye s ye s set dmacr to h'00 is frdyi interrupt generated or does dma transfer end? no no is dti interrupt generated? ye s no no command sequence end [1] [2] figure 31.29 operational fl owchart for write sequence (open-ended multiblock transfer) (2) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1103 of 1458 rej09b0033-0300 write transfer block size to tbcr execute cmd16 write the number of transfer blocks to tbncr execute cmd23 execute cmd25 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? command sequence start fifo clear ye s ye s ye s ye s no no is crceri interrupt generated? ye s no no no ye s no is response status normal? does cmd16 end successfully? does cmd23 end successfully? set dmac set dmacr (mmcif) [1] [2] figure 31.30 operational fl owchart for write sequence (pre-defined multiblock transfer) (1) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1104 of 1458 rej09b0033-0300 write 1 to cmdoff execute cmd12 set dmacr to h'00 write 1 to cmdoff fifo clear write 1 to cmdoff ye s ye s no ye s no no ye s ye s no ye s no crceri or wreri interrupt generated? is dteri interrupt generated? is drpi interrupt generated? is dbsyi interrupt generated? is dtbusy detected? tbncr = n(drpi)? write 1 to daten does dma transfer end? ye s ye s set dmacr to h'00 is frdyi interrupt is generated or does dma transfer end? no no is dti interrupt generated? ye s no ye s no is bti interrupt generated? no command sequence end n (drpi): the number of drpis from the start of write sequence note: * [1] [2] figure 31.30 operational fl owchart for write sequence (pre-defined multiblock transfer) (2) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1105 of 1458 rej09b0033-0300 execute cmd20 (cmdr to cmdstrt) read response register is crpi interrupt generated? is fei interrupt generated? is cteri interrupt generated? start command sequence fifo clear set dmac write 1 to daten set dmacr (mmcif) ye s ye s ye s no no is crceri interrupt generated? does dma transfer end? ye s ye s ye s no ye s no command sequence end is response status normal? write 1 to cmdoff execute cmd12 set dmacr to h'00 write 1 to cmdoff is frdyi interrupt generated or does dma transfer end? no no no figure 31.31 operational flowchart fo r write sequence (stream write transfer) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1106 of 1458 rej09b0033-0300 write transfer block size to tbcr write the number of transfer blocks to tbncr execute cmd16 execute cmd25 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? command sequence start fifo clear set dmac set dmacr (mmcif) ye s ye s ye s no no is crceri interrupt generated? ye s no no no is response status normal? does cmd16 end successfully? execute cmd23 ye s ye s no does cmd23 end successfully? [1] [2] figure 31.32 operational flowchart for pre-defied multiblock write transfer in auto mode (1) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1107 of 1458 rej09b0033-0300 write 1 to cmdoff execute cmd12 set dmacr to h'00 write 1 to cmdoff fifo clear write 1 to cmdoff ye s ye s no ye s no no ye s ye s no is crceri or wreri interrupt generated? is dteri interrupt generated? is bti interrupt generated? is dbsyi interrupt generated? is dtbusy detected? ye s set dmacr to h'00 does dma transfer end? no no command sequence end [1] [2] figure 31.32 operational flowchart for pre-defied multiblock write transfer in auto mode (2) section 31 multimediacard interface (mmcif) rev. 3.00 jan. 18, 2008 page 1108 of 1458 rej09b0033-0300 31.6 mmcif interrupt sources table 31.5 lists the mmcif interrupt sources. the in terrupt sources are classi fied into four groups, and four interrupt vectors are assigned. each interrupt source can be individually enabled by the enable bits in intcr0 to intcr2. the disabled interrupt source does not set the flag. table 31.5 mmcif interrupt sources name interrupt source interrupt flag write error wreri crc error* crceri* data timeout error dteri int_err_n command timeout error cteri fifo empty fei int_fstat_n fifo full ffi data response dpri data transfer end dti command response end crpi command output end cmdi data busy end dbsyi int_tran_n block transfer end bti int_frdy_n fifo ready frdyi note: * excluding the crc error in the r2 command response. section 32 ssl accelerator (ssl) rev. 3.00 jan. 18, 2008 page 1109 of 1458 rej09b0033-0300 section 32 ssl accelerator (ssl) ssl accelerator (ssl: security socket layer) pe rforms the rsa operati on (rsa: rivest shamir adleman) with public key which is used to sign data with a digital signature, and encrypts or decrypts the common key, des (d ata encryption standard), and tr iple-des that are used to preserve secrecy of data in the network to perform efficient encryption communication. with the rsa operation circuit, 32 to 512-bit width of addition, subtraction, and multiplication and 512-bit width of macro operations as well as 512-bit width of rsa operation (modular multiplication using multiple precision integers) are executed. the ssl accelerator can use 56 bits or more encry ption key. if to be exported or the like, the necessary procedures must be taken according to the foreign exchange law. please contact your nearest renesas technology sales office when you re quire the detailed functional specification for the ssl accelerator. section 32 ssl accelerator (ssl) rev. 3.00 jan. 18, 2008 page 1110 of 1458 rej09b0033-0300 section 33 user break controller (ubc) ubcs300s_000020020300 rev. 3.00 jan. 18, 2008 page 1111 of 1458 rej09b0033-0300 section 33 user break controller (ubc) the user break controller (ubc) provides functions that simplify program debugging. these functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. break conditions that can be set in the ubc are instruction fetch or data read/write access, data si ze, data contents, address value, and stop timing in the case of instruction fetch. 33.1 features 1. the following break comparison conditions can be set. number of break channels: two channels (channels a and b) user break can be requested as either the independent or sequential condition on channels a and b (sequential break setting: channel a and then channel b match with break conditions, but not in the same bus cycle). ? address compares 40 bits configured of the asid and addresses 32 bits: the asid can be selected either all-bit comparison or all- bit mask. comparison bits are mask able in 1-bit units; user can mask addresses at lower 12 bits (4-k page), lower 10 bits (1-k page), or any size of page, etc. one of the four address buses (logic address bus (lab), internal address bus (iab), one of the four data buses (l-bus data (ldb), i-bus data (idb), x-memory data bus (xdb) and y-memory data bus (ydb)) can be selected. ? data only on channel b, 32-bit maskable. one of the four data buses (l-bus data (ldb), i-bus data (idb), x-memory data bus (xdb) and y-memory data bus (ydb)) can be selected. ? bus cycle instruction fetch or data access ? read/write ? operand size byte, word, and longword 2. a user-designed user-break condition exception processing routine can be run. 3. in an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. 4. maximum repeat times for the break condition (only for channel b): 2 12 ? 1 times. 5. eight pairs of branch source/destination buffers. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1112 of 1458 rej09b0033-0300 figure 33.1 shows a block diagram of the ubc. bbra bara bamra cpu state signals xab/yab iab lab mdb access comparator address comparator channel a access comparator address comparator data comparator pc trace control channel b bbrb betr basra basrb barb bamrb bbrb bdmrb brsr brdr brcr user break request ubc location ccn location ldb/idb/ xdb/ydb access control [legend] bbra: break bus cycle register a bara: break address register a bamra: break address mask register a basra: break asid register a bbrb: break bus cycle register b barb: break address register b bamrb: break address mask register b basrb: break asid register b bdrb: break data register b bdmrb: break data mask register b betr: execution times break register brsr: branch source register brdr: branch destination register brcr: break control register asid comparator asid comparator asid figure 33.1 block diagram of ubc section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1113 of 1458 rej09b0033-0300 33.2 register descriptions the user break controller has the following registers. refer to section 37, list of registers, for more details on the addresses an d access size of these registers. ? break address register a (bara) ? break address mask register a (bamra) ? break bus cycle register a (bbra) ? break address register b (barb) ? break address mask register b (bamrb) ? break bus cycle register b (bbrb) ? break data register b (bdrb) ? break data mask register b (bdmrb) ? break control register (brcr) ? execution times break register (betr) ? branch source register (brsr) ? branch destination register (brdr) ? break asid register a (basra) ? break asid register b (basrb) 33.2.1 break address register a (bara) bara is a 32-bit readable/writable register. bara specifies the address used as a break condition in channel a. bit bit name initial value r/w description 31 to 0 baa31 to baa0 all 0 r/w break address a store the address on the la b or iab specifying break conditions of channel a. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1114 of 1458 rej09b0033-0300 33.2.2 break address ma sk register a (bamra) bamra is a 32-bit readable/writable register. bamr a specifies bits masked in the break address specified by bara. bit bit name initial value r/w description 31 to 0 bama31 to bama 0 all 0 r/w break address mask a specify bits masked in the channel a break address bits specified by bara (baa31 to baa0). 0: break address bit baan of channel a is included in the break condition 1: break address bit baan of channel a is masked and is not included in the break condition note: n = 31 to 0 33.2.3 break bus cycl e register a (bbra) bbra is a 16-bit readable/writable register, which specifies (1) l bus cycle or i bus cycle, (2) instruction fetch or data access, (3) read or write , and (4) operand size as the break conditions of channel a. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 cda1 cda0 0 0 r/w r/w l bus cycle/i bus cycle select a select the l bus cycle or i bus cycle as the bus cycle of the channel a break condition. 00: condition comparison is not performed 01: the break condition is the l bus cycle 10: the break condition is the i bus cycle 11: the break condition is the l bus cycle section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1115 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 4 ida1 ida0 0 0 r/w r/w instruction fetch/data access select a select the instruction fetch cycle or data access cycle as the bus cycle of the c hannel a break condition. 00: condition comparison is not performed 01: the break condition is the instruction fetch cycle 10: the break condition is the data access cycle 11: the break condition is the instruction fetch cycle or data access cycle 3 2 rwa1 rwa0 0 0 r/w r/w read/write select a select the read cycle or write cycle as the bus cycle of the channel a break condition. 00: condition comparison is not performed 01: the break condition is the read cycle 10: the break condition is the write cycle 11: the break condition is the read cycle or write cycle 1 0 sza1 sza0 0 0 r/w r/w operand size select a select the operand size of the bus cycle for the channel a break condition. 00: the break condition does not include operand size 01: the break condition is byte access 10: the break condition is word access 11: the break condition is longword access section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1116 of 1458 rej09b0033-0300 33.2.4 break address register b (barb) barb is a 32-bit readable/writable register. barb sp ecifies the address used as a break condition in channel b. control bits cdb1, cdb0, xye, and xys in bbrb select one of the four address buses for break condition b. bit bit name initial value r/w description 31 to 0 bab31 to bab0 all 0 r/w break address b stores an address which specifies a break condition in channel b. if the i bus or l bus is selected in bbrb, an iab or lab address is set in bab31 to bab0. if the x memory is selected in bbrb, the values in bits 15 to 1 in xab are set in bab31 to bab17. in this case, the values in bab16 to bab0 are arbitrary. if the y memory is selected in bbrb, the values in bits 15 to 1 in yab are set in bab 15 to bab1. in this case, the values in bab31 to bab16 are arbitrary. table 33.1 specifying break address register bus selection in bbrb bab31 to bab17 bab16 bab15 to bab1 bab0 l bus lab31 to lab0 i bus iab31 to iab0 x bus xab15 to xab1 don?t care don?t care don?t care y bus don?t care don?t care yab15 to yab1 don?t care section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1117 of 1458 rej09b0033-0300 33.2.5 break address ma sk register b (bamrb) bamrb is a 32-bit readable/writable register. ba mrb specifies bits masked in the break address specified by barb. bit bit name initial value r/w description 31 to 0 bamb31 to bamb0 all 0 r/w break address mask b specifies bits masked in the break address of channel b specified by barb (bab31 to bab0). 0: break address babn of channel b is included in the break condition 1: break address babn of channel b is masked and is not included in the break condition note: n = 31 to 0 33.2.6 break data register b (bdrb) bdrb is a 32-bit readable/writable register. the control bits cdb1, cdb0, xye, and xys in the break bus cycle register (bbrb) select one of the four data buses for break condition b. bit bit name initial value r/w description 31 to 0 bdb31 to bdb0 all 0 r/w break data bit b stores data which specifies a break condition in channel b. if the i bus is selected in bbrb, the break data on idb is set in bdb31 to bdb0. if the l bus is selected in bbrb, the break data on ldb is set in bdb31 to bdb0. if the x memory is selected in bbrb, the break data in bits 15 to 0 in xdb is set in bdb31 to bdb16. in this case, the values in bdb15 to bdb0 are arbitrary. if the y memory is selected in bbrb, the break data in bits 15 to 0 in ydb are set in bdb15 to bdb0. in this case, the values in bdb31 to bdb16 are arbitrary. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1118 of 1458 rej09b0033-0300 table 33.2 specifying break data register bus selection in bbrb bdb31 to bdb16 bdb15 to bdb0 l bus ldb31 to ldb0 i bus idb31 to idb0 x bus xdb15 to xdb0 don?t care y bus don?t care ydb15 to ydb0 notes: 1. specify an operand size when includin g the value of the data bus in the break condition. 2. when the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in bdrb as the break data. 3. set the data in bits 31 to 16 when includin g the value of the data bus as an l-bus break condition for the movs.w @-as,ds, mo vs.w @as,ds, movs.w @as+,ds, or movs.w @as+ix,ds instruction. 33.2.7 break data mask register b (bdmrb) bdmrb is a 32-bit readable/writable register. bd mrb specifies bits masked in the break data specified by bdrb. bit bit name initial value r/w description 31 to 0 bdmb31 to bdmb0 all 0 r/w break data mask b specifies bits masked in the break data of channel b specified by bdrb (bdb31 to bdb0). 0: break data bdbn of channel b is included in the break condition 1: break data bdbn of channel b is masked and is not included in the break condition note: n = 31 to 0 notes: 1. specify an operand size when includin g the value of the data bus in the break condition. 2. when the byte size is selected as a break condition, the same byte data must be set in bits 15 to 8 and 7 to 0 in bdrb as the break mask data in bdmrb. 3. set the mask data in bits 31 to 16 when in cluding the value of the data bus as an l-bus break condition for the movs.w @-as,ds, movs.w @as,ds, movs.w @as+,ds, or movs.w @as+ix,ds instruction. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1119 of 1458 rej09b0033-0300 33.2.8 break bus cycl e register b (bbrb) bbrb is a 16-bit readable/writable register, which specifies (1) x bus or y bus, (2) l bus cycle or i bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size as the break conditions of channel b. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 xye 0 r/w selects the x memory bus or y memory bus as the channel b break condition. note that this bit setting is enabled only when the l bus is selected in the cdb1 and cdb0 bits. selection between the x memory bus and y memory bus is done by the xys bit. 0: selects l bus for the channel b break condition 1: selects x/y memory bus for the channel b break condition 8 xys 0 r/w selects the x bus or the y bus as the bus of the channel b break condition. 0: selects the x bus for the channel b break condition 1: selects the y bus for the channel b break condition 7 6 cdb1 cdb0 0 0 r/w r/w l bus cycle/i bus cycle select b select the l bus cycle or i bus cycle as the bus cycle of the channel b break condition. 00: condition comparison is not performed 01: the break condition is the l bus cycle 10: the break condition is the i bus cycle 11: the break condition is the l bus cycle 5 4 idb1 idb0 0 0 r/w r/w instruction fetch/data access select b select the instruction fetch cycle or data access cycle as the bus cycle of the c hannel b break condition. 00: condition comparison is not performed 01: the break condition is the instruction fetch cycle 10: the break condition is the data access cycle 11: the break condition is the instruction fetch cycle or data access cycle section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1120 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 2 rwb1 rwb0 0 0 r/w r/w read/write select b select the read cycle or write cycle as the bus cycle of the channel b break condition. 00: condition comparison is not performed 01: the break condition is the read cycle 10: the break condition is the write cycle 11: the break condition is the read cycle or write cycle 1 0 szb1 szb0 0 0 r/w r/w operand size select b select the operand size of the bus cycle for the channel b break condition. 00: the break condition does not include operand size 01: the break condition is byte access 10: the break condition is word access 11: the break condition is longword access 33.2.9 break control register (brcr) brcr sets the following conditions: 1. channels a and b are used in two independent channel conditions or under the sequential condition. 2. a break is set before or after instruction execution. 3. specify whether to include the number of execution times on channel b in comparison conditions. 4. determine whether to include data bus on channel b in comparison conditions. 5. enable pc trace. 6. enable asid check. brcr is a 32-bit readable/writable register that has break conditions match flags and bits for setting a variety of break conditions. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1121 of 1458 rej09b0033-0300 bit bit name initial value r/w description 31 to 22 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 21 basma 0 r/w break asid mask a specifies whether bits in channel a break asid7 to asid0 (basa7 to basa0) which are set in basra are masked or not. 0: all basra bits are included in the break conditions and the asid is checked 1: all basra bits are not included in the break conditions and the asid is not checked 20 basmb 0 r/w break asid mask b specifies whether bits in channel b break asid7 to asid0 (basb7 to basb0) which are set in basrb are masked or not. 0: all basrb bits are included in the break conditions and the asid is checked 1: all basrb bits are not included in the break conditions and the asid is not checked 19 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 scmfca 0 r/w l bus cycle condition match flag a when the l bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1. in order to clear this flag, write 0 into this bit. 0: the l bus cycle conditio n for channel a does not match 1: the l bus cycle conditio n for channel a matches 14 scmfcb 0 r/w l bus cycle condition match flag b when the l bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1. in order to clear this flag, write 0 into this bit. 0: the l bus cycle conditio n for channel b does not match 1: the l bus cycle conditio n for channel b matches section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1122 of 1458 rej09b0033-0300 bit bit name initial value r/w description 13 scmfda 0 r/w i bus cycle condition match flag a when the i bus cycle condition in the break conditions set for channel a is satisfied, this flag is set to 1 (not cleared to 0). in order to clea r this flag, write 0 into this bit. 0: the i bus cycle condition for channel a does not match 1: the i bus cycle condition for channel a matches 12 scmfdb 0 r/w i bus cycle condition match flag b when the i bus cycle condition in the break conditions set for channel b is satisfied, this flag is set to 1. in order to clear this flag, write 0 into this bit. 0: the i bus cycle condition for channel b does not match 1: the i bus cycle condition for channel b matches 11 pcte 0 r/w pc trace enable 0: disables pc trace 1: enables pc trace 10 pcba 0 r/w pc break select a selects the break timing of the instruction fetch cycle for channel a as before or after instruction execution. 0: pc break of channel a is set before instruction execution 1: pc break of channel a is set after instruction execution 9, 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 dbeb 0 r/w data break enable b selects whether or not the data bus condition is included in the break condition of channel b. 0: no data bus condition is included in the condition of channel b 1: the data bus condition is included in the condition of channel b section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1123 of 1458 rej09b0033-0300 bit bit name initial value r/w description 6 pcbb 0 r/w pc break select b selects the break timing of the instruction fetch cycle for channel b as before or after instruction execution. 0: pc break of channel b is set before instruction execution 1: pc break of channel b is set after instruction execution 5, 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 seq 0 r/w sequence condition select selects two conditions of channels a and b as independent or sequential conditions. 0: channels a and b are compared under independent conditions 1: channels a and b are compared under sequential conditions (channel a, then channel b) 2, 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 etbe 0 r/w number of execution times break enable enables the execution-times break condition only on channel b. if this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by betr. 0: the execution-times break condition is disabled on channel b 1: the execution-times break condition is enabled on channel b section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1124 of 1458 rej09b0033-0300 33.2.10 execution times break register (betr) betr is a 16-bit readable/writable register. when the execution-times break condition of channel b is enabled, this register specifies the numb er of execution times to make the break. the maximum number is 2 12 ? 1 times. when a break condition is satisfied, it decreases betr. a break is issued when the break condition is satisfied after betr becomes h'0001. bit bit name initial value r/w description 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 to 0 bet11 to bet0 all 0 r/w number of execution times 33.2.11 branch source register (brsr) brsr is a 32-bit read-only register. brsr stores bits 27 to 0 in the address of the branch source instruction. brsr has the flag bit that is set to 1 when a branch occurs. this flag bit is cleared to 0 when brsr is read, the setting to enable pc trace is made, or brsr is initialized by a power-on reset. other bits are not initialized by a power-on reset. the eight brsr registers have a queue structure and a stored register is shifted at every branch. bit bit name initial value r/w description 31 svf 0 r brsr valid flag indicates whether the branch source address is stored. when a branch source address is fetched, this flag is set to 1. this flag is cleared to 0 by reading from brsr. 0: the value of brsr register is invalid 1: the value of brsr register is valid 30 to 28 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 27 to 0 bsa27 to bsa0 ? r branch source address store bits 27 to 0 of the branch source address. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1125 of 1458 rej09b0033-0300 33.2.12 branch destination register (brdr) brdr is a 32-bit read-only register. brdr stores bits 27 to 0 in the address of the branch destination instruction. brdr has the flag bit that is set to 1 when a branch occurs. this flag bit is cleared to 0 when brdr is read, the setting to enab le pc trace is made, or brdr is initialized by a power-on reset. other bits are not initialized by a power-on reset. the eight brdr registers have a queue structure and a stored register is shifted at every branch. bit bit name initial value r/w description 31 dvf 0 r brdr valid flag indicates whether a branch destination address is stored. when a branch destin ation address is fetched, this flag is set to 1. this flag is cleared to 0 by reading brdr. 0: the value of brdr register is invalid 1: the value of brdr register is valid 30 to 28 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 27 to 0 bda27 to bda0 ? r branch destination address store bits 27 to 0 of the branch destination address. 33.2.13 break asid register a (basra) basra is an 8-bit readable/writable register that specifies asid wh ich becomes the break condition for channel a. basra is in ccn. bit bit name initial value r/w description 7 to 0 basa7 to basa0 ? r/w break asid a store asid (bits 7 to 0) which is the break condition for channel a. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1126 of 1458 rej09b0033-0300 33.2.14 break asid register b (basrb) basrb is an 8-bit readable/wr itable register that specifies asid which becomes the break condition for channel b. basrb is in ccn. bit bit name initial value r/w description 7 to 0 basb7 to basb0 ? r/w break asid b store asid (bits 7 to 0) which is the break condition for channel b. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1127 of 1458 rej09b0033-0300 33.3 operation 33.3.1 flow of the user break operation the flow from setting of break conditions to user break exception processing is described below: 1. the break addresses and corresponding asid are set in the break address registers (bara or barb) and break asid registers (basra or ba srb in cnn). the masked addresses are set in the break address mask regi sters (bamra or bamrb). the break data is set in the break data register (bdrb). the masked data is set in the break data mask register (bdmrb). the bus break conditions are set in the break bus cycle registers (bbra or bbrb). three groups of bbra or bbrb (l bus cycle/i bus cycle select, instruction fetch/data access select, and read/write select) are each set. no user break will be generated if even one of these groups is set with 00. the respective conditions are set in the bits of the break control register (brcr). make sure to set all registers related to breaks before setting bbra or bbrb. 2. when the break conditions are satisfied, the ubc sends a user break request to the cpu and sets the l bus condition match flag (scmfca or scmfcb) and the i bus condition match flag (scmfda or scmfdb) for the appropriat e channel. when the x/y memory bus is specified for channel b, scmfcb is used for the condition match flag. 3. the appropriate condition match flags (s cmfca, scmfda, scmfcb, and scmfdb) can be used to check if the set conditions match or not. the matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 4. there is a chance that the break set in channe l a and the break set in channel b occur around the same time. in this case, there will be only one break request to the cpu, but these two break channel match flags could be both set. 5. when selecting the i bus as the break condition, note the following: ? several bus masters, including the cpu and dmac, are connected to the i bus. the ubc monitors bus cycles generated by all bus masters, and determines the condition match. ? physical addresses are used for the i bus. set a physical address in break address registers (bara and barb). the bus cycles for virtual addresses issued on the l bus by the cpu are converted to physical addresses before being output to the i bus. (if the address translation function is enabled, address translation by the mmu is carried out.) ? for data access cycles issued on the l bus by th e cpu, if their virtual addresses are not to be cached, they are issued with the data size specified on the l bus and their addresses are not rounded. ? for instruction fetch cycles issued on the l bus by the cpu, even though their virtual addresses are not to be cache d, they are issued in longwords and their addresses are rounded to match longword boundaries. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1128 of 1458 rej09b0033-0300 ? if a virtual address issued on the l bus by th e cpu is an address to be cached and a cache miss occurs, its bus cycle is issued as a cache fill cy cle on the i bus. in this case, it is issued in longwords and its address is rounded to match longword boundaries. however note that cache fill is not performed for a write miss in write through mode. in this case, the bus cycle is issued with the data size specified on the l bus and it s address is not rounded. in write back mode, a write back cycle may be issued in addition to a read fill cycle. it is a longword bus cycle whose address is rounded to match longword boundaries. ? i bus cycles (including read fill cycles) resulting from instruction fetches on the l bus by the cpu are defined as instruction fetch cycles on the i bus, while other bus cycles are defined as data access cycles. ? the dmac only issues data access cycles for i bus cycles. ? if a break condition is specified for the i bus, even when the condition matches in an i bus cycle resulting from an instruction executed by the cpu, at which instruction the break is to be accepted cannot be clearly defined. 6. while the block bit (bl) in the cpu status register (sr) is set to 1, no breaks can be accepted. however, condition determination will be carried out, and if the condition matches, the corresponding condition match flag is set to 1. 33.3.2 break on inst ruction fetch cycle 1. when l bus/instruction fetch/read/word or lo ngword is set in the break bus cycle register (bbra or bbrb), the break condition becomes the l bus instruction fetch cycle. whether it breaks before or after the execution of the inst ruction can then be sel ected with the pcba or pcbb bit in the break control register (brcr) fo r the appropriate channel. if an instruction fetch cycle is set as a break condition, clear lsb in the break address register (bara or barb) to 0. a break cannot be generated as long as this bit is set to 1. 2. an instruction set for a break before execution breaks when it is confir med that the instruction has been fetched and will be executed. this means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). when this kind of break is set for the delay slot of a delayed branch instruction, the break is generated prior to execution of the delayed branch instruction. note: if a branch does not occur at a delay condition branch instruction, the subsequent instruction is not recognized as a delay slot. 3. when the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. as with pre-execution breaks, this cannot be used with overrun fetch instructions. when this kind of break is set for a delayed branch instruction and its delay slot, a break is not generated until the first instruction at the branch destination. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1129 of 1458 rej09b0033-0300 4. when an instruction fetch cycle is set for channel b, the break data register b (bdrb) is ignored. therefore, break data cannot be set for the break of the instruction fetch cycle. 5. if the i bus is set for a break of an instructi on fetch cycle, the condition is determined for the instruction fetch cycles on the i bus. for details , see no.5 in section 33.3.1, flow of the user break operation. 33.3.3 break on data access cycle 1. if the l bus is specified as a break conditi on for data access break, c ondition comparison is performed for the virtual addresses (and data ) accessed by the executed instructions, and a break occurs if the condition is satisfied. if the i bus is specified as a break condition, condition comparison is performed for the physical addresses (and data) of the data access cycles that are issued on the i bus by all bus masters including the cpu, and a break occurs if the condition is satisfied. for details on the cpu bus cycles issued on the i bus, see no.5 in section 33.3.1, flow of the user break operation. 2. the relationship between the data access cycle address and the comparison condition for each operand size is listed in table 33.3. table 33.3 data access cycle addresses and operand size comparison conditions access size address compared longword compares break address register bits 31 to 2 to address bus bits 31 to 2 word compares break address register bits 31 to 1 to address bus bits 31 to 1 byte compares break address register bits 31 to 0 to address bus bits 31 to 0 this means that when address h'00001003 is set in the break address register (bara or barb), for example, the bus cycle in which th e break condition is satisfied is as follows (where other conditions are met). longword access at h'00001000 word access at h'00001002 byte access at h'00001003 section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1130 of 1458 rej09b0033-0300 3. when the data value is included in the break conditions on channel b: when the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle register b (bbrb). when data values are included in break conditions, a break is genera ted when the address conditions and data conditions both match. to specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register b (bdrb) and break data mask register b (bdmrb). when word or byte is set, bits 31 to 16 of bdrb and bdmrb are ignored. set the word data in bits 31 to 16 in bdrb and bdmrb when including the value of the data bus as a break condition for the movs.w @-as,ds, movs.w @as,ds, movs.w @as+,ds, or movs.w @as+ix,ds instruction (bits 15 to 0 are ignored). 4. access by a pref instruction is handled as read access in long word units without access data. therefore, if including the value of the data bus when a pref instruction is specified as a break condition, a break will not occur. 5. if the l bus is selected, a break occurs on en ding execution of the instruction that matches the break condition, and immediately before the next instruction is executed. however, when data is also specified as the brea k condition, the break may occur on ending execution of the instruction following the instruction that matche s the break condition. if the i bus is selected, the instruction at which the break will occur cannot be determined. when this kind of break occurs at a delayed branch inst ruction or its delay slot, the break may not actually take place until the first instruction at the branch destination. 33.3.4 break on x/y-memory bus cycle 1. the break condition on an x/y-memory bus cycl e is specified only in channel b. if the xye bit in bbrb is set to 1, the break address and br eak data on x/y-memory bus are selected. at this time, select the x-memory bus or y-memory bus by specifying the xys bit in bbrb. the break condition cannot include both x-memory and y-memory at the same time. the break condition is applied to an x/ y-memory bus cycle by specify ing l bus/data access/read or write/word or no specified operand size in the break bus cycle register b (bbrb). 2. when an x-memory address is selected as the break conditio n, specify an x-memory address in the upper 16 bits in barb and bamrb. when a y-memory address is selected, specify a y-memory address in the lower 16 bits. specif ication of x/y-memory data is the same for bdrb and bdmrb. 3. the timing of a data access break for the x memory or y memory bus to occur is the same as a data access break of the l bus. for details, see no.5 in sectio n 33.3.3, break on data access cycle. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1131 of 1458 rej09b0033-0300 33.3.5 sequential break 1. by setting the seq bit in brcr to 1, the sequential break is issued when a channel b break condition matches after a channel a break conditio n matches. a user break is not generated even if a channel b break condition matches before a channel a break condition matches. when channels a and b conditions match at the sa me time, the sequential break is not issued. to clear the channel a condition match when a channel a condition match has occurred but a channel b condition match has not yet occurred in a sequential break specification, clear the seq bit in brcr to 0. 2. in sequential break specification, the l/i/x/ y bus can be selected and the execution times break condition can be also specified. for example, when the execution times break condition is specified, the break condition is satisfied when a channel b condition matches with betr = h'0001 after a channel a condition has matched. 33.3.6 value of saved program counter when a break occurs, the address of the instruction fr om where execution is to be resumed is saved in the spc, and the exception handling state is entered. if the l bus is specified as a break condition, the instruction at which the break should occur can be clearly determined (except for when data is included in the break condition). if the i bus is specified as a break condition, the instruction at which the break should occur cannot be clearly determined. 1. when instruction fetch (before instruction execution) is specified as a break condition: the address of the instruction that matched the break condition is saved in the spc. the instruction that matched the condition is not executed, and the break occurs before it. however when a delay slot instruction matches the condition, the address of the delayed branch instruction is saved in the spc. 2. when instruction fetch (after instruction ex ecution) is specified as a break condition: the address of the instruction following the in struction that matched the break condition is saved in the spc. the instruction that matches the condition is executed , and the break occurs before the next instruction is executed. however when a delayed branch instruction or delay slot matches the condition, these instructions are executed, and the branch destination address is saved in the spc. 3. when data access (address only) is specified as a break condition: the address of the inst ruction immediately after the inst ruction that matched the break condition is saved in the spc. the instruction that matches the condition is executed, and the break occurs before the next instruction is executed. however when a delay slot instruction matches the condition, the branch destination address is saved in the spc. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1132 of 1458 rej09b0033-0300 4. when data access (address + data) is specified as a break condition: when a data value is added to the break conditions , the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the spc. at which instruction the break occurs cannot be determined accurately. when a delay slot instruction matches the condition, the branch destination address is saved in the spc. if the instruction following the instru ction that matches the break condition is a branch instruction, the break may occur after the branch instruction or delay slot has finished. in this case, the branch destina tion address is saved in the spc. 33.3.7 pc trace 1. setting pcte in brcr to 1 enables pc traces. when branch (branch instruction, and interrupt exception) is generated, the bran ch source address and branch de stination address are stored in brsr and brdr, respectively. 2. the values stored in brsr and brdr are as given below due to the kind of branch. ? if a branch occurs due to a bran ch instruction, the address of the branch instruction is saved in brsr and the address of the branch de stination instruction is saved in brdr. ? if a branch occurs due to an interrupt or exception, the value saved in spc due to exception occurrence is saved in brsr an d the start address of the ex ception handling routine is saved in brdr. when a repeat loop of the dsp extended function is used, control being transferred from the repeat end instruction to the repeat start inst ruction is not recognized as a branch, and the values are not stored in brsr and brdr. 3. brsr and brdr have eight pairs of queue struct ures. the top of queues is read first when the address stored in the pc trace register is read. brsr and brdr share the read pointer. read brsr and brdr in order, the queue only shif ts after brdr is read. after switching the pcte bit (in brcr) off and on, the values in the queues are invalid. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1133 of 1458 rej09b0033-0300 33.3.8 usage examples (1) break condition specified fo r l bus instruction fetch cycle (example 1-1) ? register specifications bara = h'00000404, bamra = h'00000000, bbra = h'0054, barb = h'00008010, bamrb = h'00000006, bbrb = h'0054, bdrb = h'00000000, bdmrb = h'00000000, brcr = h'00300400 specified conditions: channel a/channel b independent mode section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1134 of 1458 rej09b0033-0300 section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1135 of 1458 rej09b0033-0300 section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1136 of 1458 rej09b0033-0300 bus cycle: l bus/instruction fetch (after inst ruction execution)/read (operand size is not included in the condition) section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1137 of 1458 rej09b0033-0300 section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1138 of 1458 rej09b0033-0300 33.4 usage notes 1. the cpu can read from or wr ite to the ubc registers via the i bus. accordingly, during the period from executing an instruction to rewrite the ubc register till th e new value is actually rewritten, the desired break may not occur. in or der to know the timing when the ubc register is changed, read from the last written register. instructions after then are valid for the newly written register value. 2. ubc cannot monitor access to the l bu s and i bus in the same channel. 3. note on specification of sequential break: a condition match occurs when a b-channel match occurs in a bus cycle after an a-channel match occurs in another bus cycle in sequential break setting. therefore, no break occurs even if a bus cycle, in which an a-channel match and a b-channel match occur simultaneously, is set. 4. when a user break and another exception occu r at the same instruction, which has higher priority is determined according to the priority levels defined in table 7.1 in section 7, exception handling. if an exception with high er priority occurs, the user break is not generated. ? pre-execution break has the highest priority. ? when a post-execution break or data access break occurs simultaneously with a re- execution-type exception (includi ng pre-execution break) that has higher priority, the re- execution-type exception is a ccepted, and the condition match flag is not set (see the exception in the following note). the break will occur and the condition match flag will be set only after the exception source of the re-e xecution-type exception has been cleared by the exception handling routine and re-execution of the same instruction has ended. ? when a post-execution break or data acce ss break occurs simultaneously with a completion-type exception (trapa) that has higher priority, though a break does not occur, the condition match flag is set. 5. note the following ex ception for the above note. if a post-execution break or data access break is satisfied by an instruction that generates a cpu address error (or tlb relate d exception) by data access, the cpu address error (or tlb related exception) is given priority to the break. note that the ubc condition match flag is set in this case. 6. note the following when a break occurs in a delay slot. if a pre-execution break is set at the delay slot instruction of the rte instruction, the break does not occur until the branch destination of the rte instruction. 7. user breaks are disabled during ubc module standby mode. do not read from or write to the ubc registers during ubc module standby mode; the values are not guaranteed. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1139 of 1458 rej09b0033-0300 8. when the repeat loop of the dsp extended function is used, even though a break condition is satisfied during execution of the entire repeat loop or several instructions in the repeat loop, the break may be held. for details, see section 7, exception handling. section 33 user break controller (ubc) rev. 3.00 jan. 18, 2008 page 1140 of 1458 rej09b0033-0300 section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1141 of 1458 rej09b0033-0300 section 34 pin function controller (pfc) the pin function controller (pfc) consists of registers to select the functions and i/o directions of multiplex pins. pin functions and i/o directions can be individually selected for every pin regardless of the lsi operating mode. table 34 .1 lists the multiplex pins of this lsi. note: the signals related to the sdhi should be selected only on the models that include it. table 34.1 multiplexed pins port port function (related module) other function (related module) a pta7 input/output (port) d23 input/output (bsc) pta6 input/output (port) d22 input/output (bsc) pta5 input/output (port) d21 input/output (bsc) pta4 input/output (port) d20 input/output (bsc) pta3 input/output (port) d19 input/output (bsc) pta2 input/output (port) d18 input/output (bsc) pta1 input/output (port) d17 input/output (bsc) pta0 input/output (port) d16 input/output (bsc) b ptb7 input/output (port) d31 input/output (bsc) ptb6 input/output (port) d30 input/output (bsc) ptb5 input/output (port) d29 input/output (bsc) ptb4 input/output (port) d28 input/output (bsc) ptb3 input/output (port) d27 input/output (bsc) ptb2 input/output (port) d26 input/output (bsc) ptb1 input/output (port) d25 input/output (bsc) ptb0 input/output (port) d24 input/output (bsc) c ptc7 input/output (port) lcd_data7 output (lcdc) ptc6 input/output (port) lcd_data6 output (lcdc) ptc5 input/output (port) lcd_data5 output (lcdc) ptc4 input/output (port) lcd_data4 output (lcdc) ptc3 input/output (port) lcd_data3 output (lcdc) ptc2 input/output (port) lcd_data2 output (lcdc) ptc1 input/output (port) lcd_data1 output (lcdc) ptc0 input/output (port) lcd_data0 output (lcdc) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1142 of 1458 rej09b0033-0300 port port function (related module) other function (related module) d ptd7 input/output (port)/ pint15 input (intc) lcd_data15 output (lcdc) ptd6 input/output (port)/ pint14 input (intc) lcd_data14 output (lcdc) ptd5 input/output (port)/ pint13 input (intc) lcd_data13 output (lcdc) ptd4 input/output (port)/ pint12 input (intc) lcd_data12 output (lcdc) ptd3 input/output (port) lcd_data11 output (lcdc) ptd2 input/output (port) lcd_data10 output (lcdc) ptd1 input/output (port) lcd_data9 output (lcdc) ptd0 input/output (port) lcd_data8 output (lcdc) e pte6 input (port) afe_rxin input (afeif)/iic_scl input/output (iic) pte5 input (port) afe_rdet input (afeif)/iic_sda input/output (iic) pte4 input/output (port) lcd_m_disp output (lcdc) pte3 input/output (port) lcd_cl1 output (lcdc) pte2 input/output (port) lcd_cl2 output (lcdc) pte1 input/output (port) lcd_don output (lcdc) pte0 input/output (port) lcd_flm output (lcdc) f ptf6 input (port) da1 output (dac) ptf5 input (port) da0 output (dac) ptf4 input (port) an3 input (adc) ptf3 input (port) an2 input (adc) ptf2 input (port) an1 input (adc) ptf1 input (port) an0 input (adc) ptf0 input (port) adtrg input (adc) g ptg6 input/output (port) usb1d_rcv input (usb)/irq5 input (intc)/ afe_fs input (afeif)/ pcc_reg output (pcc) ptg5 input/output (port) usb1d_txse0 output (usb)/irq4 input (intc)/ afe_txout output (afeif)/ pcc_drv output (pcc) ptg4 input/output (port) usb1d_txdpls output (usb)/ afe_sclk input (afeif)/ iois16 input (bsc)/ pcc_iois16 input (pcc) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1143 of 1458 rej09b0033-0300 port port function (related module) other function (related module) g ptg3 input/output (port)/pint11 input (intc) usb1d_dmns input (usb)/ afe_rlycnt output (afeif)/pcc_bvd2 input (pcc) ptg2 input/output (port)/pint10 input (intc) usb1d_dpls input (usb)/afe_hc1 output (afeif)/ pcc_bvd1 input (pcc) ptg1 input/output (port)/pint9 input (intc) usb1d_speed output (usb)/ pcc_cd2 input (pcc) ptg0 input/output (port)/pint8 input (intc) usb1d_txenl output (usb)/ pcc_cd1 input (pcc) h pth6 input/output (port) ras output (bsc) pth5 input/output (port) cas output (bsc) pth4 input/output (port) cke output (bsc) pth3 input/output (port) status1 output pth2 input/output (port) status0 output pth1 input/output (port) usb2_pwr_en output (usb) pth0 input/output (port) usb1_pwr_en output (usb)/usbf_uplup (usb) j ptj6 input/output (port) audck output (hudi) ptj5 input/output (port) asebrkak output (hudi) ptj4 input/output (port) audata3 output (hudi) ptj3 input/output (port) audata2 output (hudi) ptj2 input/output (port) audata1 output (hudi) ptj1 input/output (port) audata0 output (hudi) ptj0 input/output (port) audsync output (hudi) k ptk3 input/output (port)/pint7 input (intc) pcc_reset output (pcc) ptk2 input/output (port)/pint6 input (intc) pcc_rdy input (pcc) ptk1 input/output (port)/pint5 input (intc) pcc_vs2 input (pcc) ptk0 input/output (port)/pint4 input (intc) pcc_vs1 input (pcc) l ptl7 input/output (port) trst input (hudi) ptl6 input/output (port) tms input (hudi) ptl5 input/output (port) tdo output (hudi) ptl4 input/output (port) tdi input (hudi) ptl3 input/output (port) tck input (hudi) m ptm7 input/output (port) dreq1 input (dmac) ptm6 input/output (port)/pint0 input (intc) dreq0 input (dmac) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1144 of 1458 rej09b0033-0300 port port function (related module) other function (related module) m ptm5 input/output (port) dack1 output (dmac) ptm4 input/output (port)/pint1 input (intc) dack0 output (dmac) ptm3 input/output (port)/pint3 input (intc) tend1 output (dmac) ptm2 input/output (port)/pint2 input (intc) tend0 output (dmac) ptm1 input/output (port) cs5b output (bsc)/ ce1a output (bsc) ptm0 input/output (port) cs6b output (bsc)/ ce1b output (bsc) p ptp4 input/output (port) usb1d_suspend output (usb)/ refout output (bsc)/ irqout output (bsc) ptp3 input/output (port) irq3 input (intc)/ irl3 input (intc) ptp2 input/output (port) irq2 input (intc)/ irl2 input (intc) ptp1 input/output (port) irq1 input (intc)/ irl1 input (intc) ptp0 input/output (port) irq0 input (intc)/ irl0 input (intc) r ptr7 input/output (port) a25 output (bsc) ptr6 input/output (port) a24 output (bsc) ptr5 input/output (port) a23 output (bsc) ptr4 input/output (port) a22 output (bsc) ptr3 input/output (port) a21 output (bsc) ptr2 input/output (port) a20 output (bsc) ptr1 input/output (port) a19 output (bsc) ptr0 input/output (port) a0 output (bsc) s pts4 input/output (port) siof0_sync input/output (siof) pts3 input/output (port) siof0_mclk input (siof) pts2 input/output (port) siof0_txd output (siof) pts1 input/output (port) siof0_rxd input (siof) pts0 input/output (port) siof0_sck input/output (siof) t ptt4 input/output (port) scif0_cts input (scif)/tpu_to1 output (tpu) ptt3 input/output (port) scif0_rts output (scif)/tpu_to0 output (tpu) ptt2 input/output (port) scif0_txd output (scif)/irtx output (irda) ptt1 input/output (port) scif0_rxd input (scif)/irrx input (irda) ptt0 input/output (port) scif0_sck input/output (scif) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1145 of 1458 rej09b0033-0300 port port function (related module) other function (related module) u ptu4 input/output (port) siof1_sync input/output (siof)/sd_dat2 input/output (sdhi) ptu3 input/output (port) siof1_mclk input (siof)/sd_dat1 input/output (sdhi)/ tpu_ti3b input (tpu) ptu2 input/output (port) mmc_dat input/output (mmc)/ siof1_txd output (siof)/sd_dat0 input/output (sdhi)/ tpu_ti3a input (tpu) ptu1 input/output (port) mmc_cmd input/output (mmc)/ siof1_rxd input (siof)/sd_ cmd input/output (sdhi)/ tpu_ti2b input (tpu) ptu0 input/output (port) mmc_clk output (mmc)/ siof1_sck input/output (siof)/sd_clk output (sdhi)/ tpu_ti2a input (tpu) v ptv4 input/output (port) mmc_vddon output (mmc)/ scif1_cts input (scif)/ lcd_vepwc output (lcdc)/tpu_to3 output (tpu) ptv3 input/output (port) mmc_odmod output (mmc)/ scif1_rts output (scif)/ lcd_vcpwc output (lcdc)/tpu_to2 output (tpu) ptv2 input/output (port) sim_d input/output (sim)/scif1_txd output (scif)/ sd_cd input (sdhi) ptv1 input/output (port) sim_rst output (sim)/scif1_rxd input (scif)/ sd_wp input (sdhi) ptv0 input/output (port) sim_clk output (sim)/scif1_sck input/output (scif)/ sd_dat3 input/output (sdhi) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1146 of 1458 rej09b0033-0300 34.1 register descriptions the pfc has the following registers. refer to section 37, list of registers, for more details on the addresses and access size of these registers. ? port a control register (pacr) ? port b control register (pbcr) ? port c control register (pccr) ? port d control register (pdcr) ? port e control register (pecr) ? port f control register (pfcr) ? port g control register (pgcr) ? port h control register (phcr) ? port j control register (pjcr) ? port k control register (pkcr) ? port l control register (plcr) ? port m control register (pmcr) ? port p control register (ppcr) ? port r control register (prcr) ? port s control register (pscr) ? port t control register (ptcr) ? port u control register (pucr) ? port v control register (pvcr) ? pin select register a (psela) ? pin select register b (pselb) ? pin select register c (pselc) ? pin select register d (pseld) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1147 of 1458 rej09b0033-0300 34.1.1 port a control register (pacr) pacr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pa7md1 pa7md0 0 0 r/w r/w pa7 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pa6md1 pa6md0 0 0 r/w r/w pa6 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pa5md1 pa5md0 0 0 r/w r/w pa5 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pa4md1 pa4md0 0 0 r/w r/w pa4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pa3md1 pa3md0 0 0 r/w r/w pa3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1148 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 4 pa2md1 pa2md0 0 0 r/w r/w pa2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pa1md1 pa1md0 0 0 r/w r/w pa1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pa0md1 pa0md0 0 0 r/w r/w pa0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 34.1.2 port b control register (pbcr) pbcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pb7md1 pb7md0 0 0 r/w r/w pb7 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pb6md1 pb6md0 0 0 r/w r/w pb6 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1149 of 1458 rej09b0033-0300 bit bit name initial value r/w description 11 10 pb5md1 pb5md0 0 0 r/w r/w pb5 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pb4md1 pb4md0 0 0 r/w r/w pb4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pb3md1 pb3md0 0 0 r/w r/w pb3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pb2md1 pb2md0 0 0 r/w r/w pb2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pb1md1 pb1md0 0 0 r/w r/w pb1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pb0md1 pb0md0 0 0 r/w r/w pb0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1150 of 1458 rej09b0033-0300 34.1.3 port c control register (pccr) pccr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pc7md1 pc7md0 1 0 r/w r/w pc7 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pc6md1 pc6md0 1 0 r/w r/w pc6 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pc5md1 pc5md0 1 0 r/w r/w pc5 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pc4md1 pc4md0 1 0 r/w r/w pc4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pc3md1 pc3md0 1 0 r/w r/w pc3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1151 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 4 pc2md1 pc2md0 1 0 r/w r/w pc2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pc1md1 pc1md0 1 0 r/w r/w pc1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pc0md1 pc0md0 1 0 r/w r/w pc0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 34.1.4 port d control register (pdcr) pdcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pd7md1 pd7md0 1 0 r/w r/w pd7 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pd6md1 pd6md0 1 0 r/w r/w pd6 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1152 of 1458 rej09b0033-0300 bit bit name initial value r/w description 11 10 pd5md1 pd5md0 1 0 r/w r/w pd5 mode 00: other functions (see table 34.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pd4md1 pd4md0 1 0 r/w r/w pd4 mode 00: other functions (see table 34.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pd3md1 pd3md0 1 0 r/w r/w pd3 mode 00: other functions (see table 34.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pd2md1 pd2md0 1 0 r/w r/w pd2 mode 00: other functions (see table 34.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pd1md1 pd1md0 1 0 r/w r/w pd1 mode 00: other functions (see table 34.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pd0md1 pd0md0 1 0 r/w r/w pd0 mode 00: other functions (see table 34.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1153 of 1458 rej09b0033-0300 34.1.5 port e control register (pecr) pecr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 pe6md1 1 r/w pe6 mode 0: other functions (see table 34.1.) 1: port input (pull-up mos: off) 12 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 11 pe5md1 1 r/w pe5 mode 0: other functions (see table 34.1.) 1: port input (pull-up mos: off) 10 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 9 8 pe4md1 pe4md0 1 0 r/w r/w pe4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pe3md1 pe3md0 1 0 r/w r/w pe3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1154 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 4 pe2md1 pe2md0 1 0 r/w r/w pe2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pe1md1 pe1md0 1 0 r/w r/w pe1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pe0md1 pe0md0 1 0 r/w r/w pe0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 34.1.6 port f control register (pfcr) pfcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 pf6md1 pf6md0 0 0 r/w r/w pf6 mode 00: other functions (see table 34.1.) 01: reserved 1x: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1155 of 1458 rej09b0033-0300 bit bit name initial value r/w description 11 10 pf5md1 pf5md0 0 0 r/w r/w pf5 mode 00: other functions (see table 34.1.) 01: reserved 1x: port input (pull-up mos: off) 9 8 pf4md1 pf4md0 0 0 r/w r/w pf4 mode 00: other functions (see table 34.1.) 01: reserved 1x: port input (pull-up mos: off) 7 6 pf3md1 pf3md0 0 0 r/w r/w pf3 mode 00: other functions (see table 34.1.) 01: reserved 1x: port input (pull-up mos: off) 5 4 pf2md1 pf2md0 0 0 r/w r/w pf2 mode 00: other functions (see table 34.1.) 01: reserved 1x: port input (pull-up mos: off) 3 2 pf1md1 pf1md0 0 0 r/w r/w pf1 mode 00: other functions (see table 34.1.) 01: reserved 1x: port input (pull-up mos: off) 1 0 pf0md1 pf0md0 1 0 r/w r/w pf0 mode 00: other functions (see table 34.1.) 01: reserved 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) note: x: don't care section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1156 of 1458 rej09b0033-0300 34.1.7 port g control register (pgcr) pgcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 pg6md1 pg6md0 1 1 r/w r/w pg6 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pg5md1 pg5md0 1 1 r/w r/w pg5 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pg4md1 pg4md0 1 1 r/w r/w pg4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pg3md1 pg3md0 1 1 r/w r/w pg3 mode 00: other functions (see table 34.1) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pg2md1 pg2md0 1 1 r/w r/w pg2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1157 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 2 pg1md1 pg1md0 1 1 r/w r/w pg1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pg0md1 pg0md0 1 1 r/w r/w pg0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 34.1.8 port h control register (phcr) phcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 ph6md1 ph6md0 0 0 r/w r/w ph6 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 ph5md1 ph5md0 0 0 r/w r/w ph5 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1158 of 1458 rej09b0033-0300 bit bit name initial value r/w description 9 8 ph4md1 ph4md0 0 0 r/w r/w ph4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 ph3md1 ph3md0 0 0 r/w r/w ph3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 ph2md1 ph2md0 0 0 r/w r/w ph2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 ph1md1 ph1md0 1 1 r/w r/w ph1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 ph0md1 ph0md0 1 1 r/w r/w ph0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1159 of 1458 rej09b0033-0300 34.1.9 port j control register (pjcr) pjcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15, 14 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 13 12 pj6md1 pj6md0 0/1 * 0 r/w r/w pj6 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pj5md1 pj5md0 0/1 * 0 r/w r/w pj5 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pj4md1 pj4md0 0/1 * 0 r/w r/w pj4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pj3md1 pj3md0 0/1 * 0 r/w r/w pj3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pj2md1 pj2md0 0/1 * 0 r/w r/w pj2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1160 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 2 pj1md1 pj1md0 0/1 * 0 r/w r/w pj1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pj0md1 pj0md0 0/1 * 0 r/w r/w pj0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) note: * when asemd0 = 1 (normal mode) at power-on reset, initial value is 1. when asemd0 = 0 (ase mode) at power-on reset, initial value is 0. 34.1.10 port k control register (pkcr) pkcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 pk3md1 pk3md0 1 0 r/w r/w pk3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pk2md1 pk2md0 1 0 r/w r/w pk2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1161 of 1458 rej09b0033-0300 bit bit name initial value r/w description 3 2 pk1md1 pk1md0 1 0 r/w r/w pk1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pk0md1 pk0md0 1 0 r/w r/w pk0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 34.1.11 port l control register (plcr) plcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pl7md1 pl7md0 0 0 r/w r/w pl7 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pl6md1 pl6md0 0 0 r/w r/w pl6 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pl5md1 pl5md0 0 0 r/w r/w pl5 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1162 of 1458 rej09b0033-0300 bit bit name initial value r/w description 9 8 pl4md1 pl4md0 0 0 r/w r/w pl4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pl3md1 pl3md0 0 0 r/w r/w pl3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 34.1.12 port m control register (pmcr) pmcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pm7md1 pm7md0 1 0 r/w r/w pm7 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pm6md1 pm6md0 1 0 r/w r/w pm6 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1163 of 1458 rej09b0033-0300 bit bit name initial value r/w description 11 10 pm5md1 pm5md0 1 0 r/w r/w pm5 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pm4md1 pm4md0 1 0 r/w r/w pm4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pm3md1 pm3md0 1 0 r/w r/w pm3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pm2md1 pm2md0 1 0 r/w r/w pm2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pm1md1 pm1md0 0 0 r/w r/w pm1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pm0md1 pm0md0 0 0 r/w r/w pm0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1164 of 1458 rej09b0033-0300 34.1.13 port p control register (ppcr) ppcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 pp4md1 pp4md0 1 1 r/w r/w pp4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pp3md1 pp3md0 1 0 r/w r/w pp3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pp2md1 pp2md0 1 0 r/w r/w pp2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pp1md1 pp1md0 1 0 r/w r/w pp1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pp0md1 pp0md0 1 0 r/w r/w pp0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1165 of 1458 rej09b0033-0300 34.1.14 port r control register (prcr) prcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 14 pr7md1 pr7md0 0 0 r/w r/w pr7 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 13 12 pr6md1 pr6md0 0 0 r/w r/w pr6 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 11 10 pr5md1 pr5md0 0 0 r/w r/w pr5 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 9 8 pr4md1 pr4md0 0 0 r/w r/w pr4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pr3md1 pr3md0 0 0 r/w r/w pr3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1166 of 1458 rej09b0033-0300 bit bit name initial value r/w description 5 4 pr2md1 pr2md0 0 0 r/w r/w pr2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pr1md1 pr1md0 0 0 r/w r/w pr1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pr0md1 pr0md0 0 0 r/w r/w pr0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1167 of 1458 rej09b0033-0300 34.1.15 port s cont rol register (pscr) pscr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 ps4md1 ps4md0 1 0 r/w r/w ps4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 ps3md1 ps3md0 1 0 r/w r/w ps3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 ps2md1 ps2md0 1 0 r/w r/w ps2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 ps1md1 ps1md0 1 0 r/w r/w ps1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 ps0md1 ps0md0 1 0 r/w r/w ps0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1168 of 1458 rej09b0033-0300 34.1.16 port t control register (ptcr) ptcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 pt4md1 pt4md0 1 0 r/w r/w pt4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pt3md1 pt3md0 1 0 r/w r/w pt3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pt2md1 pt2md0 1 0 r/w r/w pt2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pt1md1 pt1md0 1 0 r/w r/w pt1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pt0md1 pt0md0 1 0 r/w r/w pt0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1169 of 1458 rej09b0033-0300 34.1.17 port u control register (pucr) pucr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 pu4md1 pu4md0 1 1 r/w r/w pu4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pu3md1 pu3md0 1 1 r/w r/w pu3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pu2md1 pu2md0 1 1 r/w r/w pu2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pu1md1 pu1md0 1 1 r/w r/w pu1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pu0md1 pu0md0 1 1 r/w r/w pu0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1170 of 1458 rej09b0033-0300 34.1.18 port v control register (pvcr) pvcr is a 16-bit readable/writable register that selects the pin function and input pull-up mos control. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 pv4md1 pv4md0 0 0 r/w r/w pv4 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 7 6 pv3md1 pv3md0 0 0 r/w r/w pv3 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 5 4 pv2md1 pv2md0 1 1 r/w r/w pv2 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 3 2 pv1md1 pv1md0 1 1 r/w r/w pv1 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 1 0 pv0md1 pv0md0 1 1 r/w r/w pv0 mode 00: other functions (see table 34.1.) 01: port output 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1171 of 1458 rej09b0033-0300 34.1.19 pin select register a (psela) psela is a 16-bit readable/writabl e register that selects the pin functions multiplexing two or more other functions. to use one of other functions in the pin multiplexing two or more other functions, the port control register should be set as other functions after setting the corresponding bit in psela. bit bit name initial value r/w description 15 14 psela15 psela14 1 0 r/w r/w usb1d_txenl/ pcc_cd1 select as ptg0 other functions 00: select usb1d_txenl 01: reserved 10: select pcc_cd1 11: reserved 13 12 psela13 psela12 1 0 r/w r/w usb1d_speed/ pcc_cd2 select as ptg1 other functions 00: select usb1d_speed 01: reserved 10: select pcc_cd2 11: reserved 11 10 psela11 psela10 1 0 r/w r/w usb1d_dpls/afe_hc1/pcc_bvd1 select as ptg2 other functions 00: select usb1d_dpls 01: select afe_hc1 10: select pcc_bvd1 11: reserved 9 8 psela9 psela8 1 0 r/w r/w usb1d_dmns/afe_rlycnt/pcc_bvd2 select as ptg3 other functions 00: select usb1d_dmns 01: select afe_rlycnt 10: select pcc_bvd2 11: reserved section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1172 of 1458 rej09b0033-0300 bit bit name initial value r/w description 7 6 psela7 psela6 1 0 r/w r/w usb1d_txdpls/afe_sclk/ iois16 / pcc_iois16 select as ptg4 other functions 00: select usb1d_txdpls 01: select afe_sclk 10: select iois16 / pcc_iois16 11: reserved 5 4 psela5 psela4 1 0 r/w r/w usb1d_txse0/afe_txout/ pcc_drv /irq4 select as ptg5 other functions 00: select usb1d_txse0 01: select afe_txout 10: select pcc_drv 11: select irq4 3 2 psela3 psela2 1 0 r/w r/w usb1d_rcv/afe_fs/ pcc_reg /irq5 select as ptg5 other functions 00: select usb1d_rcv 01: select afe_fs 10: select pcc_reg 11: select irq5 1 0 psela1 psela0 0 0 r/w r/w usb1d_suspend/ refout / irqout select as ptp4 other functions 00: select usb1d_suspend 01: select refout / irqout ; select refout as refout / irqout output source 10: select refout / irqout ; select irqout as refout / irqout output source 11: select refout / irqout ; select or of refout and irqout as refout / irqout output source section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1173 of 1458 rej09b0033-0300 34.1.20 pin select register b (pselb) pselb is a 16-bit readable/writabl e register that selects the pin functions multiplexing two or more other functions. to use one of other functions in the pin multiplexing two or more other functions, the port control register should be set as other functions after setting the corresponding bit in pselb. bit bit name initial value r/w description 15 pselb15 0 r/w scif0_rts /tpu_to0 select as ptt3 other functions 0: select scif0_rts 1: select tpu_to0 14 pselb14 0 r/w scif0_cts /tpu_to1 select as ptt4 other functions 0: select scif0_cts 1: select tpu_to1 13 12 pselb13 pselb12 1 1 r/w r/w mmc_odmod / scif1_rts /lcd_vcpwc/tpu_to2 select as ptv3 other functions 00: select scif1_rts 01: select tpu_to2 10: select mmc_odmod 11: select lcd_vcpwc 11 10 pselb11 pselb10 1 1 r/w r/w mmc_vddon/ scif1_cts /lcd_vepwc/tpu_to3 select as ptv4 other functions 00: select scif1_cts 01: select tpu_to3 10: select mmc_vddon 11: select lcd_vepwc 9 pselb9 0 r/w afe_rdet /iic_sda select as pte5 other functions 0: select iic_sda 1: select afe_rdet 8 pselb8 0 r/w afe_rxin/iic_scl se lect as pte6 other functions 0: select iic_scl 1: select afe_rxin 7 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1174 of 1458 rej09b0033-0300 bit bit name initial value r/w description 1 ? 0 r reserved these bits are always read as 0. the write value should always be 0. 0 pselb0 0 r/w sd host interface sele ct as ptu4 to ptu0 and ptv2 to ptv0 other functions 0: not select sd host interface 1: select sd host interface 34.1.21 pin select register c (pselc) pselc is a 16-bit readable/writabl e register that selects the pin functions multiplexing two or more other functions. to use one of other functions in the pin multiplexing two or more other functions, the port control register should be set as other functions after setting the corresponding bit in pselc. bit bit name initial value r/w description 15 14 pselc15 pselc14 0 0 r/w r/w mmc_clk/siof1_sck/sd_clk/tpu_ti2a select as ptu0 other functions 00: select siof1_sck 01: select tpu_ti2a 10: select mmc_clk 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_clk when pselb0 = 1 13 12 pselc13 pselc12 0 0 r/w r/w mmc_cmd/siof1_rxd/sd_cmd/tpu_ti2b select as ptu1 other functions 00: select siof1_rxd 01: select tpu_ti2b 10: select mmc_cmd 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_cmd when pselb0 = 1 section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1175 of 1458 rej09b0033-0300 bit bit name initial value r/w description 11 10 pselc11 pselc10 0 0 r/w r/w sim_rst/scif1_rxd/sd_wp select as ptv1 other functions 00: select scif1_rxd 01: reserved 10: select sim_rst 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_wp when pselb0 = 1 9 8 pselc9 pselc8 0 0 r/w r/w sim_d/scif1_txd/sd_cd se lect as ptv2 other functions 00: select scif1_txd 01: reserved 10: select sim_d 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_cd when pselb0 = 1 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1176 of 1458 rej09b0033-0300 34.1.22 pin select register d (pseld) pseld is a 16-bit readable/writable register that selects the pin functions multiplexing two or more other functions. to use one of other functions in the pin multiplexing two or more other functions, the port control register should be set as other functions after setting the corresponding bit in pseld. bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 13 pseld14 pseld13 0 0 r/w r/w mmc_dat/siof1_txd/sd_dat0/tpu_ti3a select as ptu2 other functions 00: select siof1_txd 01: select tpu_ti3a 10: select mmc_dat 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_dat0 when pselb0 = 1 12 pseld12 0 r/w pin sd_dat0 control when pseld[14:13] = b'11 0: pins are not controlled 1: pins are controlled sd_dat0: pulled up 11 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1177 of 1458 rej09b0033-0300 bit bit name initial value r/w description 10 9 pseld10 pseld9 0 0 r/w r/w siof1_mclk/sd_dat1/tpu_ti3b select as ptu3 other functions 00: select siof1_mclk 01: select tpu_ti3b 10: reserved 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_dat1 when pselb0 = 1 8 pseld8 0 r/w pin sd_dat1 control wh en pseld[10:9] = b'11 0: pins are not controlled 1: pins are controlled sd_dat1: pulled up 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 5 pseld6 pseld5 0 0 r/w r/w siof1_sync/sd_dat2 sele ct as ptu4 other functions 00: select siof1_sync 01: reserved 10: reserved 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_dat2 when pselb0 = 1 4 pseld4 0 r/w pin sd_dat2 control wh en pseld[6:5] = b'11 0: pins are not controlled 1: pins are controlled sd_dat2: pulled up 3 ? 0 r reserved this bit is always read as 0. the write value should always be 0. section 34 pin function controller (pfc) rev. 3.00 jan. 18, 2008 page 1178 of 1458 rej09b0033-0300 bit bit name initial value r/w description 2 1 pseld2 pseld1 0 0 r/w r/w sim_clk/scif1_sck/sd_dat3 select as ptv0 other functions 00: select scif1_sck 01: reserved 10: select sim_clk 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_dat3 when pselb0 = 1 0 pseld0 0 r/w pin sd_dat3 control wh en pseld[2:1] = b'11 0: pins are not controlled 1: pins are controlled sd_dat3: pulled up 34.1.23 usb transceiver co ntrol register (utrctl) utrctl controls 1.8 v/3.3 v i/o buffer drivability. bit bit name initial value r/w description 15 to 9 ? all 0 r reserved 8 drv 0 r/w i/o buffer drive control 0: 1.8 v/3.3 v i/o buffer high drivability 1: 1.8 v/3.3 v i/o buffer low drivability power supply pin, vccq1, can be applied 1.65 to 1.95 v or 2.7 to 3.6 v. when 1.65 to 1.95 v is applied to vccq1, setting the drivability high (drv = 0) is recommended. when 2.7 to 3.6 v is applied to vccq1, setting the drivability low (drv = 1) is recommended. 7 to 2 ? all 0 r/w reserved 1 usb_ trans 0 r/w 0 usb_sel 1 r/w see section 23, usb pin multiplex controller. section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1179 of 1458 rej09b0033-0300 section 35 i/o ports this lsi has 18 i/o ports (ports a to h, j to m, and r to v). all i/o po rt pins are multiplexed with other pin functions (the pin function controller (pfc) handles the selection of pin functions and pull-up mos control). each i/o port has a data register, which stores data for the pins. 35.1 port a port a is an input/output port with the pin configuration shown in figure 35.1. each pin has an input pull-up mos, which is controlled by the port a control register (pacr) in the pfc. port a pta7 (input/output) / d23 (input/output) pta6 (input/output) / d22 (input/output) pta5 (input/output) / d21 (input/output) pta4 (input/output) / d20 (input/output) pta3 (input/output) / d19 (input/output) pta2 (input/output) / d18 (input/output) pta1 (input/output) / d17 (input/output) pta0 (input/output) / d16 (input/output) figure 35.1 port a 35.1.1 register description port a has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port a data register (padr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1180 of 1458 rej09b0033-0300 35.1.2 port a data register (padr) padr is a register that stores data for pins pt a7 to pta0. bits pa7dt to pa0dt correspond to pins pta7 to pta0. when the pin function is general output port, if the port is read, the value of the corresponding padr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 pa7dt 0 r/w 6 pa6dt 0 r/w 5 pa5dt 0 r/w 4 pa4dt 0 r/w 3 pa3dt 0 r/w 2 pa2dt 0 r/w 1 pa1dt 0 r/w 0 pa0dt 0 r/w table 35.1 shows the function of padr. table 35.1 port a data register (padr) read/write operations pacr state panmd1 panmd0 pin state read write 0 other function padr value value is written to padr, but does not affect pin state. 0 1 output padr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to padr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to padr, but does not affect pin state. note: n = 7 to 0 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1181 of 1458 rej09b0033-0300 35.2 port b port b is an input/output port with the pin configuration shown in figure 35.2. each pin has an input pull-up mos, which is controlled by the port b control register (pbcr) in the pfc. port b ptb7 (input/output) / d31 (input/output) ptb6 (input/output) / d30 (input/output) ptb5 (input/output) / d29 (input/output) ptb4 (input/output) / d28 (input/output) ptb3 (input/output) / d27 (input/output) ptb2 (input/output) / d26 (input/output) ptb1 (input/output) / d25 (input/output) ptb0 (input/output) / d24 (input/output) figure 35.2 port b 35.2.1 register description port b has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port b data register (pbdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1182 of 1458 rej09b0033-0300 35.2.2 port b data register (pbdr) pbdr is a register that stores data for pins ptb7 to ptb0. bits pb7dt to pb0dt correspond to pins ptb7 to ptb0. when the pin function is general output port, if the port is read, the value of the corresponding pbdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 pb7dt 0 r/w 6 pb6dt 0 r/w 5 pb5dt 0 r/w 4 pb4dt 0 r/w 3 pb3dt 0 r/w 2 pb2dt 0 r/w 1 pb1dt 0 r/w 0 pb0dt 0 r/w table 35.2 shows the function of pbdr. table 35.2 port b data regist er (pbdr) read/write operations pbcr state pbnmd1 pbnmd0 pin state read write 0 other function pbdr value value is written to pbdr, but does not affect pin state. 0 1 output pbdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to pbdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pbdr, but does not affect pin state. note: n = 7 to 0 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1183 of 1458 rej09b0033-0300 35.3 port c port c is an input/output port with the pin configuration shown in figure 35.3. each pin has an input pull-up mos, which is controlled by the port c control register (pccr) in the pfc. port c ptc7 (input/output) / ldc_data7 (output) ptc6 (input/output) / ldc_data6 (output) ptc5 (input/output) / ldc_data5 (output) ptc4 (input/output) / ldc_data4 (output) ptc3 (input/output) / ldc_data3 (output) ptc2 (input/output) / ldc_data2 (output) ptc1 (input/output) / ldc_data1 (output) ptc0 (input/output) / ldc_data0 (output) figure 35.3 port c 35.3.1 register description port c has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port c data register (pcdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1184 of 1458 rej09b0033-0300 35.3.2 port c data register (pcdr) pcdr is a register that stores data for pins ptc7 to ptc0. bits pc7dt to pc0dt correspond to pins ptc7 to ptc0. when the pin function is general output port, if the port is read, the value of the corresponding pcdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 pc7dt 0 r/w 6 pc6dt 0 r/w 5 pc5dt 0 r/w 4 pc4dt 0 r/w 3 pc3dt 0 r/w 2 pc2dt 0 r/w 1 pc1dt 0 r/w 0 pc0dt 0 r/w table 35.3 shows the function of pcdr. table 35.3 port c data register (pcdr) read/write operations pccr state pcnmd1 pcnmd0 pin state read write 0 other function pcdr value value is written to pcdr, but does not affect pin state. 0 1 output pcdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to pcdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pcdr, but does not affect pin state. note: n = 0 to 7 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1185 of 1458 rej09b0033-0300 35.4 port d port d is an input/output port with the pin configuration shown in figure 35.4. each pin has an input pull-up mos, which is controlled by the port d control register (pdcr) in the pfc. port d ptd7 (input/output) / ldc_data15 (output) / pint15 (input) ptd6 (input/output) / ldc_data14 (output) / pint14 (input) ptd5 (input/output) / ldc_data13 (output) / pint13 (input) ptd4 (input/output) / ldc_data12 (output) / pint12 (input) ptd3 (input/output) / ldc_data11 (output) ptd2 (input/output) / ldc_data10 (output) ptd1 (input/output) / ldc_data9 (output) ptd0 (input/output) / ldc_data8 (output) figure 35.4 port d 35.4.1 register description port d has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port d data register (pddr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1186 of 1458 rej09b0033-0300 35.4.2 port d data register (pddr) pddr is a register that stores data for pins pt d7 to ptd0. bits pd7dt to pd0dt correspond to pins ptd7 to ptd0. when the pin function is general output port, if the port is read, the value of the corresponding pddr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 pd7dt 0 r/w 6 pd6dt 0 r/w 5 pd5dt 0 r/w 4 pd4dt 0 r/w 3 pd3dt 0 r/w 2 pd2dt 0 r/w 1 pd1dt 0 r/w 0 pd0dt 0 r/w table 35.4 shows the function of pddr. table 35.4 port d data register (pddr) read/write operations pdcr state pdnmd1 pdnmd0 pin state read write 0 other function pddr value value is written to pddr, but does not affect pin state. 0 1 output pddr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to pddr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pddr, but does not affect pin state. note: n = 6 and 7 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1187 of 1458 rej09b0033-0300 35.5 port e port e is an input/output port with the pin configuration shown in figure 35.5. each pin has an input pull-up mos, which is controlled by the port e control register (pecr) in the pfc. port e pte6 (input)/afe_rxin (input)/iic_scl (input/output) pte5 (input)/ afe_rdet (input)/iic_sda (input/output) pte4 (input/output) / ldc_m_disp (output) pte3 (input/output) / ldc_cl1 (output) pte2 (input/output) / ldc_cl2 (output) pte1 (input/output) / ldc_don (output) pte0 (input/output) / ldc_flm (output) figure 35.5 port e 35.5.1 register description port e has the following register. refer to section 37, list of re gisters, for the address and access size for this register. ? port e data register (pedr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1188 of 1458 rej09b0033-0300 35.5.2 port e data register (pedr) pedr is a register that stores data for pins pte6 to pte0. bits pe6dt to pe0dt correspond to pins pte6 to pte0. when the pin function is genera l output port, if the port is read, the value of the corresponding pedr bit is returned directly. when the function is general input port, if the port is read the corresponding pin level is read. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 pe6dt 0 r/w 5 pe5dt 0 r/w 4 pe4dt 0 r/w 3 pe3dt 0 r/w 2 pe2dt 0 r/w 1 pe1dt 0 r/w 0 pe0dt 0 r/w table 35.5 shows the function of pedr. table 35.5 port e data regist er (pedr) read/write operations pecr state penmd1 penmd0 pin state read write 0 other function pedr value value is written to pedr, but does not affect pin state. 0 1 output pedr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to pedr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pedr, but does not affect pin state. note: n= 0 to 4 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1189 of 1458 rej09b0033-0300 pecr state penmd1 pin state read write 0 other function pedr value value is written to pedr, but does not affect pin state. 1 input (pull-up mos off) pin state value is written to pedr, but does not affect pin state. note: n= 5 or 6 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1190 of 1458 rej09b0033-0300 35.6 port f port f is an input/output port with the pin configuration shown in figure 35.6. each pin has an input pull-up mos, which is controlled by the port f control register (pfcr) in the pfc. port f ptf6 (input) / da1 (output) ptf5 (input) / da0 (output) ptf4 (input) / an3 (input) ptf3 (input) / an2 (input) ptf2 (input) / an1 (input) ptf1 (input) / an0 (input) ptf0 (input)/ adtrg (input) figure 35.6 port f 35.6.1 register description port f has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port f data register (pfdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1191 of 1458 rej09b0033-0300 35.6.2 port f data register (pfdr) pfdr is a register that stores data for pins ptf6 to ptf0. bits pf6dt to pf0dt correspond to pins ptf6 to ptf0. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 pf6dt 0 r 5 pf5dt 0 r 4 pf4dt 0 r 3 pf3dt 0 r 2 pf2dt 0 r 1 pf1dt 0 r 0 pf0dt 0 r table 35.6 shows the function of pfdr. table 35.6 port f data register (pfdr) read/write operations pfcr state pfnmd1 pfnmd0 pin state read write 0 other function pfdr value value is written to pfdr, but does not affect pin state. 0 1 reserved ? ? 1 ? input (pull-up mos off) pin state value is written to pfdr, but does not affect pin state. note: n = 1 to 6 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1192 of 1458 rej09b0033-0300 pfcr state pfnmd1 pfnmd0 pin state read write 0 other function pfdr value value is written to pfdr, but does not affect pin state. 0 1 reserved ? ? 0 input (pull-up mos on) pin state value is written to pfdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pfdr, but does not affect pin state. note: n = 0 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1193 of 1458 rej09b0033-0300 35.7 port g port g is an input/output port with the pin configuration shown in figure 35.7. each pin has an input pull-up mos, which is controlled by the port g control register (pgcr) in the pfc. port g ptg6 (input/output) / usb1d_rcv (input) / irq5 (input) / afe_fs (input) / pcc_reg (output) ptg5 (input/output) / usb1d_txse0 (output) / irq4 (input) / afe_txout (output) / pcc_drv (output) ptg4 (input/output) / usb1d_txdpls (output) / afe_sclk (input) / iois16 (input) / pcc_iois16 (input) ptg3 (input/output) / usb1d_dmns (input) / pint11 (input) / afe_rlycnt (output) / pcc_bvd2 (input) ptg2 (input/output) / usb1d_dpls (input) / pint10 (input) / afe_hc1 (output) / pcc_bvd1 (input) ptg1 (input/output) / usb1d_speed (output) / pint9 (input) pcc_cd2 (input) ptg0 (input/output) / usb1d_txenl (output) / pint8 (input) pcc_cd1 (input) figure 35.7 port g 35.7.1 register description port g has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port g data register (pgdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1194 of 1458 rej09b0033-0300 35.7.2 port g data register (pgdr) pgdr is a register that stores data for pins pt g6 to ptg0. bits pg6dt to pg0dt correspond to pins ptg6 to ptg0. when the pin function is general output port, if the port is read, the value of the corresponding pgdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 pg6dt 0 r/w 5 pg5dt 0 r/w 4 pg4dt 0 r/w 3 pg3dt 0 r/w 2 pg2dt 0 r/w 1 pg1dt 0 r/w 0 pg0dt 0 r/w table 35.7 shows the function of pgdr. table 35.7 port g data register (pgdr) read/write operations pgcr state pgnmd1 pgnmd0 pin state read write 0 other function pgdr value value is written to pgdr, but does not affect pin state. 0 1 output pgdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to pgdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pgdr, but does not affect pin state. note: n = 0 to 6 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1195 of 1458 rej09b0033-0300 35.8 port h port h is an input/output port with the pin configuration shown in figure 35.8. each pin has an input pull-up mos, which is controlled by the port h control register (phcr) in the pfc. port h pth6 (input/output) / ras (output) pth5 (input/output) / cas (output) pth4 (input/output) / cke (output) pth3 (input/output) / status1 (output) pth2 (input/output) / status0 (output) pth1 (input/output) / usb2_pwr_en (output) pth0 (input/output) / usb1_pwr_en (output) figure 35.8 port h 35.8.1 register description port h has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port h data register (phdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1196 of 1458 rej09b0033-0300 35.8.2 port h data register (phdr) phdr is a register that stores data for pins pt h6 to pth0. bits ph6dt to ph0dt correspond to pins pth6 to pth0. when the pin function is general output port, if the port is read, the value of the corresponding phdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 ph6dt 0 r/w 5 ph5dt 0 r/w 4 ph4dt 0 r/w 3 ph3dt 0 r/w 2 ph2dt 0 r/w 1 ph1dt 0 r/w 0 ph0dt 0 r/w table 35.8 shows the function of phdr. table 35.8 port h data register (phdr) read/write operations phcr state phnmd1 phnmd0 pin state read write 0 other function phdr value value is written to phdr, but does not affect pin state. 0 1 output phdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to phdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to phdr, but does not affect pin state. note: n = 0 to 6 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1197 of 1458 rej09b0033-0300 35.9 port j port j is an input/output port with the pin configuration shown in figure 35.9. each pin has an input pull-up mos, which is controlled by the port j control register (pjcr) in the pfc. port j ptj6 (input/output) / audck (output) ptj5 (input/output) / asebrkak (output) ptj4 (input/output) / audata3 (output) ptj3 (input/output) / audata2 (output) ptj2 (input/output) / audata1 (output) ptj1 (input/output) / audata0 (output) ptj0 (input/output) / audsync (output) figure 35.9 port j 35.9.1 register description port j has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port j data register (pjdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1198 of 1458 rej09b0033-0300 35.9.2 port j data register (pjdr) pjdr is a register that stores data for pins ptj6 to ptj0. bits pj6dt to pj0dt correspond to pins ptj6 to ptj0. when the pin function is general output port, if the port is read, the value of the corresponding pjdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 pj6dt 0 r/w 5 pj5dt 0 r/w 4 pj4dt 0 r/w 3 pj3dt 0 r/w 2 pj2dt 0 r/w 1 pj1dt 0 r/w 0 pj0dt 0 r/w table 35.9 shows the function of pjdr. table 35.9 port j data regist er (pjdr) read/write operations pjcr state pjnmd1 pjnmd0 pin state read write 0 other function pjdr value value is written to pjdr, but does not affect pin state. 0 1 output pjdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to pjdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pjdr, but does not affect pin state. note: n = 0 to 6 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1199 of 1458 rej09b0033-0300 35.10 port k port k is an input/output port with the pin configuration shown in figure 35.10. each pin has an input pull-up mos, which is controlled by the port k control register (pkcr) in the pfc. port k ptk3 (input/output) / pint7 (input) / pcc_reset (output) ptk2 (input/output) / pint6 (input) / pcc_rdy (input) ptk1 (input/output) / pint5 (input) / pcc_vs2 (input) ptk0 (input/output) / pint4 (input) / pcc_vs1 (input) figure 35.10 port k 35.10.1 register description port k has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port k data register (pkdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1200 of 1458 rej09b0033-0300 35.10.2 port k data register (pkdr) pkdr is a register that stores data for pins pt k3 to ptk0. bits pk3dt to pk0dt correspond to pins ptk3 to ptk0. when the pin function is general output port, if the port is read, the value of the corresponding pkdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 pk3dt 0 r/w 2 pk2dt 0 r/w 1 pk1dt 0 r/w 0 pk0dt 0 r/w table 35.10 shows the function of pkdr. table 35.10 port k data register (pkdr) read/write operations pkcr state pknmd1 pknmd0 pin state read write 0 other function pkdr value value is written to pkdr, but does not affect pin state. 0 1 output pkdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to pkdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pkdr, but does not affect pin state. note: n = 0 to 3 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1201 of 1458 rej09b0033-0300 35.11 port l port l is an input/output port with the pin configuration shown in figure 35.11. each pin has an input pull-up mos, which is controlled by the port l control register (plcr) in the pfc. port l ptl7 (input/output) / trst (input) ptl6 (input/output) / tms (input) ptl5 (input/output) / tdo (output) ptl4 (input/output) / tdi (input) ptl3 (input/output) / tck (input) figure 35.11 port l 35.11.1 register description port l has the following register. refer to section 37, list of re gisters, for the address and access size for this register. ? port l data register (pldr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1202 of 1458 rej09b0033-0300 35.11.2 port l data register (pldr) pldr is a register that stores data for pins ptl7 to ptl3. bits pl7dt to pl3dt correspond to pins ptl7 to ptl3. when the function is general output port, if the port is read, the value of the corresponding pldr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 pl7dt 0 r/w 6 pl6dt 0 r/w 5 pl5dt 0 r/w 4 pl4dt 0 r/w 3 pl3dt 0 r/w table 35.11 shows the function of pldr. 2 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. table 35.11 port l data regist er (pldr) read/write operations plcr state plnmd1 plnmd0 pin state read write 0 other function pldr value value is written to pldr, but does not affect pin state. 0 1 output pldr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to pldr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pldr, but does not affect pin state. note: n = 3 to 7 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1203 of 1458 rej09b0033-0300 35.12 port m port m is an input/output port with the pin configuration shown in figure 35.12. each pin has an input pull-up mos, which is controlled by the port m control register (pmcr) in the pfc. port m ptm7 (input/output) / dreq1 (input) ptm6 (input/output) / dreq0 (input) / pint0 (input) ptm5 (input/output) / dack1 (output) ptm4 (input/output) / dack0 (output) / pint1 (input) ptm3 (input/output) / tend1 (output) / pint3 (input) ptm2 (input/output) / tend0 (output) / pint2 (input) ptm1 (input/output) / cs5b (output) / ce1a (output) ptm0 (input/output) / cs6b (output) / ce1b (output) figure 35.12 port m 35.12.1 register description port m has the following register. refer to section 37, list of re gisters, for the address and access size for this register. ? port m data register (pmdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1204 of 1458 rej09b0033-0300 35.12.2 port m data register (pmdr) pmdr is a register that stores data for pins ptm7 to ptm0. bits pm7dt to pm0dt correspond to pins ptm7 to ptm0. when the pin function is ge neral output port, if the port is read, the value of the corresponding pmdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 pm7dt 0 r/w 6 pm6dt 0 r/w 5 pm5dt 0 r/w 4 pm4dt 0 r/w 3 pm3dt 0 r/w 2 pm2dt 0 r/w 1 pm1dt 0 r/w 0 pm0dt 0 r/w table 35.12 shows the function of pmdr. table 35.12 port m data register (pmdr) read/write operations pmcr state pmnmd1 pmnmd0 pin state read write 0 other function pmdr value value is written to pmdr, but does not affect pin state. 0 1 output pmdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to pmdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pmdr, but does not affect pin state. note: n = 0 to 7 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1205 of 1458 rej09b0033-0300 35.13 port p port p is an input/output port with the pin configuration shown in figure 35.13. each pin has an input pull-up mos, which is controlled by the port p control register (ppcr) in the pfc. port p ptp4 (input/output) / usb1d_suspend(output) / refout (output) / irqout (output) ptp3 (input/output) / irq3 (input) / irl3 (input) ptp2 (input/output) / irq2 (input) / irl2 (input) ptp1 (input/output) / irq1 (input) / irl1 (input) ptp0 (input/output) / irq0 (input) / irl0 (input) figure 35.13 port p 35.13.1 register description port p has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port p data register (ppdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1206 of 1458 rej09b0033-0300 35.13.2 port p data register (ppdr) ppdr is a register that stores data for pins ptp4 to ptp0. bits pp4dt to pp0dt correspond to pins ptp4 to ptp0. when the pin function is general output port, if the port is read, the value of the corresponding ppdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 pp4dt 0 r/w 3 pp3dt 0 r/w 2 pp2dt 0 r/w 1 pp1dt 0 r/w 0 pp0dt 0 r/w table 35.13 shows the function of ppdr. table 35.13 port p data regist er (ppdr) read/write operations ppcr state ppnmd1 ppnmd0 pin state read write 0 other function ppdr value value is written to ppdr, but does not affect pin state. 0 1 output ppdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to ppdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to ppdr, but does not affect pin state. note: n = 0 to 4 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1207 of 1458 rej09b0033-0300 35.14 port r port r is an input/output port with the pin configuration shown in figure 35.14. each pin has an input pull-up mos, which is controlled by the port r control register (prcr) in the pfc. port r ptr7 (input/output) / a25 (output) ptr6 (input/output) / a24 (output) ptr5 (input/output) / a23 (output) ptr4 (input/output) / a22 (output) ptr3 (input/output) / a21 (output) ptr2 (input/output) / a20 (output) ptr1 (input/output) / a19 (output) ptr0 (input/output) / a0 (output) figure 35.14 port r 35.14.1 register description port r has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port r data register (prdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1208 of 1458 rej09b0033-0300 35.14.2 port r data register (prdr) prdr is a register that stores data for pins ptr7 to ptr0. bits pr7dt to pr0dt correspond to pins ptr7 to ptr0. when the pin function is gene ral output port, if the port is read, the value of the corresponding prdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 pr7dt 0 r/w 6 pr6dt 0 r/w 5 pr5dt 0 r/w 4 pr4dt 0 r/w 3 pr3dt 0 r/w 2 pr2dt 0 r/w 1 pr1dt 0 r/w 0 pr0dt 0 r/w table 35.14 shows the function of prdr. table 35.14 port r data register (prdr) read/write operations prcr state prnmd1 prnmd0 pin state read write 0 other function prdr value value is written to prdr, but does not affect pin state. 0 1 output prdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to prdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to prdr, but does not affect pin state. note: n = 0 to 7 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1209 of 1458 rej09b0033-0300 35.15 port s port s is an input/output port with the pin configuration shown in figure 35.15. each pin has an input pull-up mos, which is controlled by the port s control register (pscr) in the pfc. port s pts4 (input/output) / siof0_sync (input/output) pts3 (input/output) / siof0_mclk (input) pts2 (input/output) / siof0_txd (output) pts1 (input/output) / siof0_rxd (input) pts0 (input/output) / siof0_sck (input/output) figure 35.15 port s 35.15.1 register description port s has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port s data register (psdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1210 of 1458 rej09b0033-0300 35.15.2 port s data register (psdr) psdr is a register that stores data for pins pts4 to pts0. bits ps4dt to ps0dt correspond to pins pts4 to pts0. when the pin function is general output port, if the port is read, the value of the corresponding psdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 ps4dt 0 r/w 3 ps3dt 0 r/w 2 ps2dt 0 r/w 1 ps1dt 0 r/w 0 ps0dt 0 r/w table 35.15 shows the function of psdr. table 35.15 port s data regist er (psdr) read/write operations pscr state psnmd1 psnmd0 pin state read write 0 other function psdr value value is written to psdr, but does not affect pin state. 0 1 output psdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to psdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to psdr, but does not affect pin state. note: n = 0 to 4 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1211 of 1458 rej09b0033-0300 35.16 port t port t is an input/output port with the pin configuration shown in figure 35.16. each pin has an input pull-up mos, which is controlled by the port t control register (ptcr) in the pfc. port t ptt4 (input/output) / scif0_cts (input) / tputo1 (output) ptt3 (input/output) / scif0_rts (output) / tputo0 (output) ptt2 (input/output) / scif0_txd (output) / irtx (output) ptt1 (input/output) / scif0_rxd (input) / irrx (input) ptt0 (input/output) / scif0_sck (input/output) figure 35.16 port t 35.16.1 register description port t has the following register. refer to section 37, list of re gisters, for the address and access size for this register. ? port t data register (ptdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1212 of 1458 rej09b0033-0300 35.16.2 port t data register (ptdr) ptdr is a register that stores data for pins ptt4 to ptt0. bits pt4dt to pt0dt correspond to pins ptt4 to ptt0. when the pin function is genera l output port, if the port is read, the value of the corresponding ptdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 pt4dt 0 r/w 3 pt3dt 0 r/w 2 pt2dt 0 r/w 1 pt1dt 0 r/w 0 pt0dt 0 r/w table 35.16 shows the function of ptdr. table 35.16 port t data regist er (ptdr) read/write operations ptcr state ptnmd1 ptnmd0 pin state read write 0 other function ptdr value value is written to ptdr, but does not affect pin state. 0 1 output ptdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to ptdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to ptdr, but does not affect pin state. note: n = 0 to 4 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1213 of 1458 rej09b0033-0300 35.17 port u port u is an input/output port with the pin configuration shown in figure 35.17. each pin has an input pull-up mos, which is controlled by the port u control register (pucr) in the pfc. port u ptu4 (input/output) / siof1_sync (input/output) / sd_dat2 (input/output) ptu3 (input/output) / siof1_mclk (input) / sd_dat1 (input/output) / tpu_ti3b (input) ptu2 (input/output) / mmc_dat (input/output) / siof1_txd (output) / sd_dat0 (input/output) / tpu_ti3a (input) ptu1 (input/output) / mmc_cmd (output) / siof1_rxd (input) / sd_cmd (input/output) / tpu_ti2b (input) ptu0 (input/output) / mmc_clk (output) / siof1_sck (input/output) / sd_clk (output) / tpu_ti2a (input) figure 35.17 port u 35.17.1 register description port u has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port u data register (pudr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1214 of 1458 rej09b0033-0300 35.17.2 port u data register (pudr) pudr is a register that stores data for pins pt u4 to ptu0. bits pu4dt to pu0dt correspond to pins ptu4 to ptu0. when the pin function is general output port, if the port is read, the value of the corresponding pudr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 pu4dt 0 r/w 3 pu3dt 0 r/w 2 pu2dt 0 r/w 1 pu1dt 0 r/w 0 pu0dt 0 r/w table 35.17 shows the function of pudr. table 35.17 port u data register (pudr) read/write operations pucr state punmd1 punmd0 pin state read write 0 other function pudr value value is written to pudr, but does not affect pin state. 0 1 output pudr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to pudr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pudr, but does not affect pin state. note: n = 0 to 4 section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1215 of 1458 rej09b0033-0300 35.18 port v port v is an input/output port with the pin configuration shown in figure 35.18. each pin has an input pull-up mos, which is controlled by the port v control register (pvcr) in the pfc. port v ptv4 (input/output) / mmc_vddon (output) / scif1_cts (input) / ldc_vepwc (output) / tpu_to3 (output) ptv3 (input/output) / mmc_odmod (output) / scif1_rts (output) / ldc_vcpwc (output) / tpu_to2 (output) ptv2 (input/output) / sim_d (input/output) / scif1_txd (output) / sd_cd (input) ptv1 (input/output) / sim_rst (output) / scif1_rxd (input) / sd_wp (input) ptv0 (input/output) / sim_clk (output) / scif1_sck (input/output) / sd_dat3 (input/output) figure 35.18 port v 35.18.1 register description port v has the following register. refer to secti on 37, list of registers, for the address and access size for this register. ? port v data register (pvdr) section 35 i/o ports rev. 3.00 jan. 18, 2008 page 1216 of 1458 rej09b0033-0300 35.18.2 port v data register (pvdr) pvdr is a register that stores data for pins pt v4 to ptv0. bits pv4dt to pv0dt correspond to pins ptv4 to ptv0. when the pin function is general output port, if the port is read, the value of the corresponding pvdr bit is returned directly. when the function is general input port, if the port is read, the corresponding pin level is read. bit bit name initial value r/w description 7 to 5 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 4 pv4dt 0 r/w 3 pv3dt 0 r/w 2 pv2dt 0 r/w 1 pv1dt 0 r/w 0 pv0dt 0 r/w table 35.18 shows the function of pvdr. table 35.18 port v data register (pvdr) read/write operations pvcr state pvnmd1 pvnmd0 pin state read write 0 other function pvdr value value is written to pvdr, but does not affect pin state. 0 1 output pvdr value write va lue is output from pin. 0 input (pull-up mos on) pin state value is written to pvdr, but does not affect pin state. 1 1 input (pull-up mos off) pin state value is written to pvdr, but does not affect pin state. note: n = 0 to 4 section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1217 of 1458 rej09b0033-0300 section 36 user debugging interface (h-udi) this lsi incorporates a user debugging interface (h-udi) and advanced us er debugger (aud) for a boundary scan function and emulator support. this section describes the h-udi. the aud is a function exclusively fo r use by an emulator. refer to the user's manual for the relevant emulator for details of the aud. 36.1 features the h-udi is a serial i/o interface which su pports jtag (joint test action group, ieee standard 1149.1 and ieee standard test access port and boundary-scan architecture) specifications. the h-udi in this lsi supports a boundary scan mode, and is also used for emulator connection. when using an emulator, h-udi functions should not be used. refer to the emulator manual for the method of conn ecting the emulator. figure 36.1 shows a block diagram of the h-udi. section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1218 of 1458 rej09b0033-0300 sdir sdid tck tdo tdi tms trst sdbpr mux sdbsr shift register tap controller decoder local bus [legend] sdbpr: bypass register sdbsr: boundary scan register sdir: instruction register sdid: id register figure 36.1 block diagram of h-udi 36.2 input/output pins table 36.1 shows the pin configuration of the h-udi. section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1219 of 1458 rej09b0033-0300 table 36.1 pin configuration pin name i/o description tck input serial data input/output clock pin data is serially supplied to the h- udi from the data input pin (tdi), and output from the data output pin (tdo), in synchronizati on with this clock. tms input mode select input pin the state of the tap c ontrol circuit is determined by changing this signal in synchronization with tck. the protocol supports the jtag standard (ieee std.1149.1). trst input reset input pin input is accepted asynchronously with respect to tck, and when low, the h-udi is reset. trst must be low for a constant period when power is turned on regardless of using the h-udi function. this is different from the jtag standard. see section 36.4.2, reset confi guration, for more information. tdi input serial data input pin data transfer to the h-udi is executed by changing this signal in synchronization with tck. tdo output serial data output pin data read from the h-udi is executed by reading this pin in synchronization with tck. the data output timing depends on the command type set in the sdir. s ee section 36.4.3, tdo output timing, for more information. asemd0 input ase mode select pin if a low level is input at the asemd0 pin while the resetp pin is asserted, ase mode is entered; if a high level is input, normal mode is entered. when the asemd0 pin is used by the user system alone without using the emulator and h-udi, fix the asemd0 pin high. in ase mode, dedicated emulator function ca n be used. the input level at the asemd0 pin should be held for at least one cycle after resetp negation. asebrkak audsync audata3 to audata0 audck output dedicated emulator pin section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1220 of 1458 rej09b0033-0300 36.3 register descriptions the h-udi has the following registers. refer to s ection 37, list of registers, for more details on the addresses and states of these registers in each operating mode. ? bypass register (sdbpr) ? instruction register (sdir) ? boundary scan register (sdbsr) ? id register (sdid) ? shift register 36.3.1 bypass register (sdbpr) sdbpr is a 1-bit register that cannot be accessed by the cpu. when sdir is set to the bypass mode, sdbpr is connected between h-udi pins tdi and tdo. the initial value is undefined. 36.3.2 instruction register (sdir) sdir is a 16-bit read-only register . the register is in jtag idcode in its initial state. it is initialized by trst assertion or in the tap test-logic-reset state, and can be written to by the h- udi irrespective of the cpu mode. operation is not guaranteed if a reserved command is set in this register. bit bit name initial value r/w description 15 to 13 ti7 to ti5 all 1 r 12 ti4 0 r 11 to 8 ti3 to ti0 all 1 r test instruction 7 to 0 the h-udi instruction is transferred to sdir by a serial input from tdi. for commands, see table 36.2. 7 to 2 ? all 1 r reserved these bits are always read as 1. 1 ? 0 r reserved this bit is always read as 0. 0 ? 1 r reserved this bit is always read as 1. section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1221 of 1458 rej09b0033-0300 table 36.2 h-udi commands bits 15 to 8 ti7 ti6 ti5 ti4 ti3 ti 2 ti1 ti0 description 0 0 0 0 ? ? ? ? jtag extest 0 0 1 0 ? ? ? ? jtag clamp 0 0 1 1 ? ? ? ? jtag highz 0 1 0 0 ? ? ? ? jtag sample/preload 0 1 1 0 ? ? ? ? h-udi reset, negate 0 1 1 1 ? ? ? ? h-udi reset, assert 1 0 1 ? ? ? ? ? h-udi interrupt 1 1 1 0 ? ? ? ? jtag idcode (initial value) 1 1 1 1 ? ? ? ? jtag bypass other than the above reserved 36.3.3 shift register shift register is a 32-bit register. the uppe r 16 bits are set in sdir at update-ir. if shifted in, the shift-in value is shift-out after th e value of the 32-bit shift register is shifted out. 36.3.4 boundary scan register (sdbsr) sdbsr is a 434-bit shift register, located on the pa d, for controlling the input/output pins of this lsi. the initial value is undefined. this register cannot be accessed by the cpu. using the extest, sample/preload, clamp, and highz commands, a boundary scan test supporting the jtag standard can be carried out. table 36.3 shows the correspondence between this lsi's pins and boundary scan register bits. section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1222 of 1458 rej09b0033-0300 table 36.3 pins and boundary scan register bits bit pin name i/o bit pin name i/o from tdi 404 d24/ptb0 out 433 md2 in 403 d23/pta7 out 432 md1 in 402 d22/pta6 out 431 md0 in 401 d21/pta5 out 430 d31/ptb7 in 400 d20/pta4 out 429 d30/ptb6 in 399 d19/pta3 out 428 d29/ptb5 in 398 d18/pta2 out 427 d28/ptb4 in 397 d17/pta1 out 426 d27/ptb3 in 396 d16/pta0 out 425 d26/ptb2 in 395 rd/ wr out 424 d25/ptb1 in 394 cas /pth5 out 423 d24/ptb0 in 393 we3 /dqmuu/ iciowr out 422 d23/pta7 in 392 we2 /dqmul/ iciord out 421 d22/pta6 in 391 cke/pth4 out 420 d21/pta5 in 390 ras /pth6 out 419 d20/pta4 in 389 we1 / dqmlu / we out 418 d19/pta3 in 388 we0 /dqmll out 417 d18/pta2 in 387 cs2 out 416 d17/pta1 in 386 cs3 out 415 d16/pta0 in 385 a17 out 414 cas /pth5 in 384 a16 out 413 cke/pth4 in 383 a15 out 412 ras /pth6 in 382 a14 out 411 d31/ptb7 out 381 a13 out 410 d30/ptb6 out 380 a12 out 409 d29/ptb5 out 379 a11 out 408 d28/ptb4 out 378 a10 out 407 d27/ptb3 out 377 a9 out 406 d26/ptb2 out 376 a8 out 405 d25/ptb1 out 375 a7 out section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1223 of 1458 rej09b0033-0300 bit pin name i/o bit pin name i/o 374 a6 out 342 a15 control 373 a5 out 341 a14 control 372 a4 out 340 a13 control 371 a3 out 339 a12 control 370 d31/ptb7 control 338 a11 control 369 d30/ptb6 control 337 a10 control 368 d29/ptb5 control 336 a9 control 367 d28/ptb4 control 335 a8 control 366 d27/ptb3 control 334 a7 control 365 d26/ptb2 control 333 a6 control 364 d25/ptb1 control 332 a5 control 363 d24/ptb0 control 331 a4 control 362 d23/pta7 control 330 a3 control 361 d22/pta6 control 329 a0/ptr0 in 360 d21/pta5 control 328 d15 in 359 d20/pta4 control 327 d14 in 358 d19/pta3 control 326 d13 in 357 d18/pta2 control 325 d12 in 356 d17/pta1 control 324 d11 in 355 d16/pta0 control 323 d10 in 354 rd/ wr control 322 d9 in 353 cas /pth5 control 321 d8 in 352 we3 /dqmuu/ iciowr control 320 d7 in 351 we2 /dqmul/ iciord control 319 d6 in 350 cke/pth4 control 318 d5 in 349 ras /pth6 control 317 d4 in 348 we1 / dqmlu / we control 316 d3 in 347 we0 /dqmll control 315 d2 in 346 cs2 control 314 d1 in 345 cs3 control 313 d0 in 344 a17 control 312 cs6b / ce1b /ptm0 in 343 a16 control 311 cs5b / ce1a /ptm1 in section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1224 of 1458 rej09b0033-0300 bit pin name i/o bit pin name i/o 310 breq in 278 d1 out 309 wait / pcc_wait in 277 d0 out 308 a19/ptr1 in 276 cs6b / ce1b /ptm0 out 307 a20/ptr2 in 275 cs6a / ce2b out 306 a21/ptr3 in 274 cs5b / ce1a /ptm1 out 305 a22/ptr4 in 273 cs5a / ce2a out 304 a23/ptr5 in 272 back out 303 a24/ptr6 in 271 cs0 out 302 a25/ptr7 in 270 cs4 out 301 dreq0 /pint0/ptm6 in 269 bs out 300 dack0 /pint1/ptm4 in 268 rd out 299 tend0/pint2/ptm2 in 267 a18 out 298 dreq1 /ptm7 in 266 a19/ptr1 out 297 dack1 /ptm5 in 265 a20/ptr2 out 296 tend1/pint3/ptm3 in 264 a21/ptr3 out 295 a2 out 263 a22/ptr4 out 294 a1 out 262 a23/ptr5 out 293 a0/ptr0 out 261 a24/ptr6 out 292 d15 out 260 a25/ptr7 out 291 d14 out 259 dreq0 /pint0/ptm6 out 290 d13 out 258 dack0 /pint1/ptm4 out 289 d12 out 257 tend0/pint2/ptm2 out 288 d11 out 256 dreq1 /ptm7 out 287 d10 out 255 dack1 /ptm5 out 286 d9 out 254 tend1/pint3/ptm3 out 285 d8 out 253 a2 control 284 d7 out 252 a1 control 283 d6 out 251 a0/ptr0 control 282 d5 out 250 d15 control 281 d4 out 249 d14 control 280 d3 out 248 d13 control 279 d2 out 247 d12 control section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1225 of 1458 rej09b0033-0300 bit pin name i/o bit pin name i/o 246 d11 control 216 dack0 /pint1/ptm4 control 245 d10 control 215 tend0/pint2/ptm2 control 244 d9 control 214 dreq1 /ptm7 control 243 d8 control 213 dack1 /ptm5 control 242 d7 control 212 tend1/pint3/ptm3 control 241 d6 control 211 pcc_vs1 /pint4/ptk0 in 240 d5 control 210 pcc_vs2 /pint5/ptk1 in 239 d4 control 209 pcc_rdy/pint6/ptk2 in 238 d3 control 208 pcc_reset/pint7/ptk3 in 237 d2 control 207 asebrkak /ptj5 in 236 d1 control 206 audsync /ptj0 in 235 d0 control 205 audck/ptj6 in 234 cs6b / ce1b /ptm0 control 204 audata0/ptj1 in 233 cs6a / ce2b control 203 audata1/ptj2 in 232 cs5b / ce1a /ptm1 control 202 audata2/ptj3 in 231 cs5a / ce2a control 201 audata3/ptj4 in 230 back control 200 nmi in 229 cs0 control 199 irq0/ irl0 /ptp0 in 228 cs4 control 198 irq1/ irl1 /ptp1 in 227 bs control 197 irq2/ irl2 /ptp2 in 226 rd control 196 irq3/ irl3 /ptp3 in 225 a18 control 195 scif0_sck/ptt0 in 224 a19/ptr1 control 194 scif0_rxd/irrx/ptt1 in 223 a20/ptr2 control 193 scif0_txd/irtx/ptt2 in 222 a21/ptr3 control 192 scif0_rts /tpu_to0/ptt3 in 221 a22/ptr4 control 191 scif0_cts /tpu_to1/ptt4 in 220 a23/ptr5 control 190 mmc_clk/siof1_sck/sd_clk/ tpu_ti2a/ptu0 in 219 a24/ptr6 control 189 mmc_cmd/siof1_rxd/sd_cmd/ tpu_ti2b/ptu1 in 218 a25/ptr7 control 217 dreq0 /pint0/ptm6 control 188 mmc_dat/siof1_txd/sd_dat0/ tpu_ti3a/ptu2 in section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1226 of 1458 rej09b0033-0300 bit pin name i/o bit pin name i/o 187 siof1_mclk/sd_dat1/tpu_ti3b/ ptu3 in 168 pcc_reset/pint7/ptk3 out 186 siof1_sync/sd_dat2/ptu4 in 167 asebrkak /ptj5 out 185 sim_clk/scif1_sck/sd_dat3/ ptv0 in 166 audsync /ptj0 out 184 sim_rst/scif1_rxd/sd_wp/ptv1 in 165 audck/ptj6 out 183 sim_d/scif1_txd/sd_cd/ptv2 in 164 audata0/ptj1 out 182 mmc_odmod / scif1_rts / lcd_vcpwc/tpu_to2/ptv3 in 163 audata1/ptj2 out 181 mmc_vddon/ scif1_cts / lcd_vepwc/tpu_to3/ptv4 in 162 audata2/ptj3 out 180 usb1d_txenl/pint8/ pcc_cd1 /ptg0 in 161 audata3/ptj4 out 179 usb1d_speed/pint9/ pcc_cd2 /ptg1 in 160 irq0/ irl0 /ptp0 out 178 usb1d_dpls/pint10/afe_hc1/ pcc_bvd1/ptg2 in 159 irq1/ irl1 /ptp1 out 177 usb1d_dmns/pint11/afe_rlycnt/ pcc_bvd2/ptg3 in 158 irq2/ irl2 /ptp2 out 176 usb1d_txdpls/afe_sclk/ iois16 / pcc_iois16 /ptg4 in 157 irq3/ irl3 /ptp3 out 175 usb1d_txse0/irq4/afe_txout/ pcc_drv /ptg5 in 156 scif0_sck/ptt0 out 174 usb1d_rcv/irq5/afe_fs/ pcc_reg /ptg6 in 155 scif0_rxd/irrx/ptt1 out 173 usb1d_suspend/ refout / irqout /ptp4 in 154 scif0_txd/irtx/ptt2 out 172 usb1_ovr_current /usbf_vbus in 153 scif0_rts /tpu_to0/ptt3 out 171 pcc_vs1 /pint4/ptk0 out 152 scif0_cts /tpu_to1/ptt4 out 170 pcc_vs2 /pint5/ptk1 out 151 mmc_clk/siof1_sck/sd_clk/ tpu_ti2a/ptu0 out 169 pcc_rdy/pint6/ptk2 out 150 mmc_cmd/siof1_rxd/sd_cmd/ tpu_ti2b_ptu1 out section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1227 of 1458 rej09b0033-0300 bit pin name i/o bit pin name i/o 149 mmc_dat/siof1_txd/sd_dat0/ tpu_ti3a/ptu2 out 130 pcc_reset/pint7/ptk3 control 148 siof1_mclk/sd_dat1/tpu_ti3b/ ptu3 out 129 asebrkak /ptj5 control 147 siof1_sync/sd_dat2/ptu4 out 128 audsync /ptj0 control 146 sim_clk/scif1_sck/sd_dat3/ ptv0 out 127 audck/ptj6 control 145 sim_rst/scif1_rxd/sd_wp/ptv1 out 126 audata0/ptj1 control 144 sim_d/scif1_txd/sd_cd/ptv2 out 125 audata1/ptj2 control 143 mmc_odmod / scif1_rts / lcd_vcpwc/tpu_to2/ptv3 out 124 audata2/ptj3 control 142 mmc_vddon/ scif1_cts / lcd_vepwc/tpu_to3/ptv4 out 123 audata3/ptj4 control 141 usb1d_txenl/pint8 pcc_cd1 /ptg0 out 122 irq0/ irl0 /ptp0 control 140 usb1d_speed/pint9/ pcc_cd2 /ptg1 out 121 irq1/ irl1 /ptp1 control 139 usb1d_dpls/pint10/afe_hc1/ pcc_bvd1/ptg2 out 120 irq2/ irl2 /ptp2 control 138 usb1d_dmns/pint11/afe_rlycnt/ pcc_bvd2/ptg3 out 119 irq3/ irl3 /ptp3 control 137 usb1d_txdpls/afe_sclk/ iois16 / pcc_iois16 /ptg4 out 118 scif0_sck/ptt0 control 136 usb1d_txse0/irq4/afe_txout/ pcc_drv /ptg5 out 117 scif0_rxd/irrx/ptt1 control 135 usb1d_rcv/irq5/afe_fs/ pcc_reg /ptg6 out 116 scif0_txd/irtx/ptt2 control 134 usb1d_suspend/ refout / irqout /ptp4 out 115 scif0_rts /tpu_to0/ptt3 control 133 pcc_vs1 /pint4/ptk0 control 114 scif0_cts /tpu_to1/ptt4 control 132 pcc_vs2 /pint5/ptk1 control 113 mmc_clk/siof1_sck/sd_clk/tpu _ti2a/ptu0 control 131 pcc_rdy/pint6/ptk2 control 112 mmc_cmd/siof1_rxd/sd_cmd/ tpu_ti2b_ptu1 control section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1228 of 1458 rej09b0033-0300 bit pin name i/o bit pin name i/o 111 mmc_dat/siof1_txd/sd_dat0/ tpu_ti3a/ptu2 control 91 siof0_sck/pts0 in 110 siof1_mclk/sd_dat1/tpu_ti3b/ ptu3 control 90 siof0_rxd/pts1 in 109 siof1_sync/sd_dat2/ptu4 control 89 siof0_txd/pts2 in 108 sim_clk/scif1_sck/sd_dat3/ ptv0 control 88 siof0_mclk/pts3 in 107 sim_rst/scif1_rxd/sd_wp/ptv1 control 86 siof0_sync/pts4 in 106 sim_d/scif1_txd/sd_cd/ptv2 control 87 lcd_clk in 105 mmc_odmod / scif1_rts / lcd_vcpwc/tpu_to2/ptv3 control 85 lcd_m_disp/pte4 in 104 mmc_vddon/ scif1_cts / lcd_vepwc/tpu_to3/ptv4 control 84 lcd_cl1/pte3 in 103 usb1d_txenl/pint8/ pcc_cd1 /ptg0 control 83 lcd_cl2/pte2 in 102 usb1d_speed/pint9/ pcc_cd2 /ptg1 control 82 lcd_don/pte1 in 101 usb1d_dpls/pint10/afe_hc1/ pcc_bvd1/ptg2 control 81 lcd_flm/pte0 in 100 usb1d_dmns/pint11/afe_rlycnt/ pcc_bvd2/ptg3 control 80 lcd_data0/ptc0 in 99 usb1d_txdpls/afe_sclk/ iois16 / pcc_iois16 /ptg4 control 79 lcd_data1/ptc1 in 98 usb1d_txse0/irq4/afe_txout/ pcc_drv /ptg5 control 78 lcd_data2/ptc2 in 97 usb1d_rcv/irq5/afe_fs/ pcc_reg /ptg6 control 77 lcd_data3/ptc3 in 96 usb1d_suspend/ refout / irqout /ptp4 control 76 lcd_data4/ptc4 in 95 adtrg /ptf0 in 75 lcd_data5/ptc5 in 94 usb1_pwr_en/usbf_uplup/pth0 in 74 lcd_data6/ptc6 in 93 usb2_ovr_current in 73 lcd_data7/ptc7 in 92 usb2_pwr_en/pth1 in 72 lcd_data8/ptd0 in section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1229 of 1458 rej09b0033-0300 bit pin name i/o bit pin name i/o 71 lcd_data9/ptd1 in 39 lcd_data8/ptd0 out 70 lcd_data10/ptd2 in 38 lcd_data9/ptd1 out 69 lcd_data11/ptd3 in 37 lcd_data10/ptd2 out 68 lcd_data12/pint12/ptd4 in 36 lcd_data11/ptd3 out 67 lcd_data13/pint13/ptd5 in 35 lcd_data12/pint12/ptd4 out 66 lcd_data14/pint14/ptd6 in 34 lcd_data13/pint13/ptd5 out 65 lcd_data15/pint15/ptd7 in 33 lcd_data14/pint14/ptd6 out 64 status0/pth2 in 32 lcd_data15/pint15/ptd7 out 63 status1/pth3 in 31 status0/pth2 out 62 md5 in 30 status1/pth3 out 61 md4 in 29 usb1_pwr_en/usbf_uplup/pth0 control 60 md3 in 28 usb2_pwr_en/pth1 control 59 usb1_pwr_en/usbf_uplup/pth0 out 27 siof0_sck/pts0 control 58 usb2_pwr_en/pth1 out 26 siof0_rxd/pts1 control 57 siof0_sck/pts0 out 25 siof0_txd/pts2 control 56 siof0_rxd/pts1 out 24 siof0_mclk/pts3 control 55 siof0_txd/pts2 out 23 siof0_sync/pts4 control 54 siof0_mclk/pts3 out 22 lcd_m_disp/pte4 control 53 siof0_sync/pts4 out 21 lcd_cl1/pte3 control 52 lcd_m_disp/pte4 out 20 lcd_cl2/pte2 control 51 lcd_cl1/pte3 out 19 lcd_don/pte1 control 50 lcd_cl2/pte2 out 18 lcd_flm/pte0 control 49 lcd_don/pte1 out 17 lcd_data0/ptc0 control 48 lcd_flm/pte0 out 16 lcd_data1/ptc1 control 47 lcd_data0/ptc0 out 15 lcd_data2/ptc2 control 46 lcd_data1/ptc1 out 14 lcd_data3/ptc3 control 45 lcd_data2/ptc2 out 13 lcd_data4/ptc4 control 44 lcd_data3/ptc3 out 12 lcd_data5/ptc5 control 43 lcd_data4/ptc4 out 11 lcd_data6/ptc6 control 42 lcd_data5/ptc5 out 10 lcd_data7/ptc7 control 41 lcd_data6/ptc6 out 9 lcd_data8/ptd0 control 40 lcd_data7/ptc7 out 8 lcd_data9/ptd1 control section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1230 of 1458 rej09b0033-0300 bit pin name i/o bit pin name i/o 7 lcd_data10/ptd2 control 3 lcd_data14/pint14/ptd6 control 6 lcd_data11/ptd3 control 2 lcd_data15/pint15/ptd7 control 5 lcd_data12/pint12/ptd4 control 1 status0/pth2 control 4 lcd_data13/pint13/ptd5 control 0 status1/pth3 control to tdo note: * control means a low active signal. the corresponding pin is driven with an out value when the control is driven low. 36.3.5 id register (sdid) sdid is a 32-bit read-only register in which sd idh and sdidl are connected. each register is a 16-bit that can be read by cpu. the idcode command is set from the h-udi pin. this register can be read from the tdo when the tap state is shift-dr. writing is disabled. bit bit name initial value r/w description 31 to 0 did31 to did0 refer to description r device id31 to id0 device id register that is stipulated by jtag. ? h'002f200f (initial value) for this sh7720 group. ? h'002f2447 (initial value) for this SH7721 group. upper four bits may be changed by the chip version. sdidh corresponds to bits 31 to 16. sdidl corresponds to bits 15 to 0. section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1231 of 1458 rej09b0033-0300 36.4 operation 36.4.1 tap controller figure 36.2 shows the internal states of the ta p controller. state trans itions support the jtag standard. test -logic-reset capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-dr-scan run-test/idle 1 0 0 0 0 11 1 1 0 0 0 1 11 0 1 1 1 0 capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select-ir-scan 0 0 1 0 0 0 1 0 1 1 10 figure 36.2 tap controller state transitions note: the transition condition is the tms value at the rising edge of tck. the tdi value is sampled at the rising edge of tck; shifting occurs at the falling edge of tck. for details on change timing of the tdo value, see sect ion 36.4.3, tdo output timing. the tdo is at high impedance, except with shift-dr and shift-ir states. during the change to trst = 0, there is a transition to test-logic-reset asynchronously with tck. section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1232 of 1458 rej09b0033-0300 36.4.2 reset configuration table 36.4 reset configuration asemd0 * 1 resetp trst * 4 chip state l normal reset and h-udi reset l h normal reset l h-udi reset only h h h normal operation l reset hold * 2 l h normal reset * 3 l h-udi reset only l h h normal operation notes: 1. performs normal mode and ase mode settings asemd0 = h, normal mode asemd0 = l, ase mode 2. in ase mode, reset hold is enabled by driving the resetp and trst pins low for a constant cycle. in this state, th e cpu does not start up, even if resetp is driven high. when trst is driven high, h-udi operation is enab led, but the cpu does not start up. the reset hold state is c anceled by the following: ? another resetp assert (power-on reset) ? trst reassert 3. in ase mode, reset may not be enabled. w hen the emulator is not being connected, set asemd0 to high. 4. when using this lsi in normal mode, it is recommended that the trst pin is fixed low. 36.4.3 tdo output timing the timing of data output from the tdo is switched by the command type set in the sdir. the timing changes at the tck falling edge when jtag commands (extest, clamp, highz, sample/preload, idcode, and bypass) are set. this is a timing of the jtag standard. when the h-udi commands (h-udi reset negate, h-udi reset assert, and h-udi interrupt) are set, tdo is output at the tck rising edge earlier than the jt ag standard by a half cycle. section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1233 of 1458 rej09b0033-0300 tdo (when the h-udi command is set) tck tdo (when the boundary scan command is set) t tdo t tdo figure 36.3 h-udi data transfer timing 36.4.4 h-udi reset an h-udi reset is executed by inputting an h-udi reset assert command in sdir. an h-udi reset is of the same kind as a power-on reset. an h-udi reset is released by inputting an h-udi reset negate command. the required time between the h-udi reset assert command and h-udi reset negate command is the same as time for keeping the resetp pin low to apply a power-on reset. h-udi reset assert h-udi reset negate sdir chip internal reset cpu state branch to h'a0000000 figure 36.4 h-udi reset 36.4.5 h-udi interrupt the h-udi interrupt function generates an interrupt by setting a command from the h-udi in the sdir. an h-udi interrupt is a general exception or an interrupt operation, resulting in a branch to an address based on the vbr value plus offset, and with return by the rte instruction. this interrupt request has a fixed priority level of 15. h-udi interrupts are accepted in sleep mode, but not in standby mode. section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1234 of 1458 rej09b0033-0300 36.5 boundary scan a command can be set in sdir by the h-udi to place the h-udi pins in the boundary scan mode stipulated by jtag. 36.5.1 supported instructions this lsi supports the three essential instructi ons defined in the jtag standard (bypass, sample/preload, and extest) and three op tion instructions (idcode, clamp, and highz). (1) bypass the bypass instruction is an essential standard in struction that operates the bypass register. this instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. while this instruction is ex ecuting, the test circu it has no effect on the system circuits. the upper four bits of the instruction code are b'1111. (2) sample/preload the sample/preload instruction i nputs values from this lsi's internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. when this instruction is executing, this lsi's input pin signals are transmitted directly to the internal circuitry, and internal circuit valu es are directly output externally from the output pins. this lsi's system circuits are not affected by execution of this instruction. the upper four bits of the instruction code are b'0100. in a sample operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. snapshot latching is performed in synchronization with the rise of tck in the capture-dr state. snapshot latching does not affect normal operation of this lsi. in a preload operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the extest instruction. without a preload operation, when the extest instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (t ransfer to the output latch) (with the extest instruction, the parallel output latch value is constantly output to the output pin). section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1235 of 1458 rej09b0033-0300 (3) extest this instruction is provided to test external circuitry when this lsi is mounted on a printed circuit board. when this instruction is executed, output pins are used to output test data (previously set by the sample/preload instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. if testing is carried out by using the extest instruction n times, the nth test data is scanned-in when test data (n-1) is scanned out. data loaded into the output pin boundary scan register in the capture-dr state is not used for external circuit testing (it is replaced by a shift operation). the upper four bits of the instruction code are b'0000. (4) idcode a command can be set in sdir by the h-udi pins to place the h-udi pins in the idcode mode stipulated by jtag. when the h-udi is initialized ( trst is asserted or tap is in the test-logic- reset state), the idcode mode is entered. (5) clamp, highz a command can be set in sdir by the h-udi pi ns to place the h-udi pins in the clamp or highz mode stipulated by jtag. 36.5.2 points for attention 1. boundary scan mode does not cover the following signals: ? clock-related signals (extal, xtal, extal_usb, xtal_usb, extal_rtc, xtal_rtc, ckio) ? system- and e10a-related signals ( resetp , resetm , ca, asemd0 ) ? h-udi-related signals (tck, tdi, tdo, tms, trst ) ? iic-related signals (iic_scl/pte6, iic_sda/pte5) ? analog-related signals (an0/ptf1, an1/ptf2, an2/ptf3, an3/ptf4, da0/ptf5, da1/ptf6, usb1_p, usb1_m, usb2_p, usb2_m) 2. when the extest, clamp, and highz commands are set, fix the resetp pin low. 3. fix the ca pin high, during boundary scan. 4. when a boundary scan test for other than bypass and idcode is carried out, fix the asemd0 pin high. section 36 user debugging interface (h-udi) rev. 3.00 jan. 18, 2008 page 1236 of 1458 rej09b0033-0300 36.6 usage notes 1. an h-udi command, once set, will not be modified as long as another command is not re- issued from the h-udi. if the same command is given continuously, the command must be set after a command (bypass, etc.) that does not affect chip operations is once set. 2. because chip operations ar e suspended in standby mode, h-udi commands are not accepted. to keep the tap state constant before and after standby mode, tck must be high during standby mode transition. 3. the h-udi is used for emulator connection. therefore, h-udi functions cannot be used when using an emulator. 36.7 advanced user debugger (aud) the aud is a function only for an emulator. for details on the aud, refer to each emulator's user's manual. section 37 list of registers rev. 3.00 jan. 18, 2008 page 1237 of 1458 rej09b0033-0300 section 37 list of registers the address list gives information on the on-chip i/o registers and is configured as described below. 1. register addresses (by functional module, in order of the corresponding section numbers) ? descriptions by functional module, in order of the corresponding section numbers ? access to reserved addresses which are not described in this list is prohibited. ? when registers consist of 16 or 32 bits, the addresses of the msbs are given, on the presumption of a big-endian system. 2. register bits ? bit configurations of the registers are describe d in the same order as the register addresses (by functional module, in order of the corresponding section numbers). ? reserved bits are indicated by ? in the bit name column. ? no entry in the bit-name column indicates that the whole register is al located as a counter or for holding data. ? when registers consist of 16 or 32 bits, bits are described from the msb side. the order in which bytes are described is on the presumption of a big-endian system. 3. register states in each operating mode ? register states are described in the same or der as the register addresses (by functional module, in order of the corresponding section numbers). ? for the initial state of each bit, refer to the de scription of the register in the corresponding section. ? the register states described here are for the basic operating mode s. if there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip module. section 37 list of registers rev. 3.00 jan. 18, 2008 page 1238 of 1458 rej09b0033-0300 37.1 register addresses entries under access size in dicate number of bits. note: access to undefined or reserved address is prohibited. since operation or continued operation is not guaranteed when these regist ers are accessed, do not attempt such access. register name abbreviation number of bits address module access size mmu control register mmucr 32 h'ffff ffe0 mmu 32 page table entry register high pteh 32 h'ffff fff0 32 page table entry register low ptel 32 h'ffff fff4 32 translation table base register ttb 32 h'ffff fff8 32 cache control register 2 ccr2 32 h'a400 00b0 cache 32 cache control register 3 ccr3 32 h'a400 00b4 32 cache control register 1 ccr1 32 h'ffff ffec 32 interrupt event register 2 intevt2 32 h'a400 0000 32 trapa exception register tra 32 h'ffff ffd0 exception handling 32 exception event register expevt 32 h'ffff ffd4 32 interrupt event register intevt 32 h'ffff ffd8 32 exception address register tea 32 h'ffff fffc 32 interrupt priority register f iprf 16 h'a408 0000 intc 16 interrupt priority register g iprg 16 h'a408 0002 16 interrupt priority register h iprh 16 h'a408 0004 16 interrupt priority register i ipri 16 h'a408 0006 16 interrupt priority register j iprj 16 h'a408 0008 16 interrupt request register 5 irr5 8 h'a408 0020 8 interrupt request register 6 irr6 8 h'a408 0022 8 interrupt request register 7 irr7 8 h'a408 0024 8 interrupt request register 8 irr8 8 h'a408 0026 8 interrupt request register 9 irr9 8 h'a408 0028 8 interrupt request register 0 irr0 8 h'a414 0004 8 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1239 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size interrupt request register 1 irr1 8 h'a414 0006 intc 8 interrupt request register 2 irr2 8 h?a414 0008 8 interrupt request register 3 irr3 8 h?a414 000a 8 interrupt request register 4 irr4 8 h?a414 000c 8 interrupt control register 1 icr1 16 h?a414 0010 16 interrupt control register 2 icr2 16 h?a414 0012 16 pint interrupt enable register pinter 16 h?a414 0014 16 interrupt priority register c iprc 16 h?a414 0016 16 interrupt priority register d iprd 16 h?a414 0018 16 interrupt priority register e ipre 16 h?a414 001a 16 interrupt control register 0 icr0 16 h?a414 fee0 16 interrupt priority register a ipra 16 h?a414 fee2 16 interrupt priority register b iprb 16 h?a414 fee4 16 common control register cmncr 32 h?a4fd 0000 bsc 32 bus control register for cs0 cs0bcr 32 h?a4fd 0004 32 bus control register for cs2 cs2bcr 32 h?a4fd 0008 32 bus control register for cs3 cs3bcr 32 h?a4fd 000c 32 bus control register for cs4 cs4bcr 32 h?a4fd 0010 32 bus control register for cs5a cs5abcr 32 h?a4fd 0014 32 bus control register for cs5b cs5bbcr 32 h?a4fd 0018 32 bus control register for cs6a cs6abcr 32 h?a4fd 001c 32 bus control register for cs6b cs6bbcr 32 h?a4fd 0020 32 wait control register for cs0 cs0wcr 32 h?a4fd 0024 32 wait control register for cs2 cs2wcr 32 h?a4fd 0028 32 wait control register for cs3 cs3wcr 32 h?a4fd 002c 32 wait control register for cs4 cs4wcr 32 h?a4fd 0030 32 wait control register for cs5a cs5awcr 32 h?a4fd 0034 32 wait control register for cs5b cs5bwcr 32 h?a4fd 0038 32 wait control register for cs6a cs6awcr 32 h?a4fd 003c 32 wait control register for cs6b cs6bwcr 32 h?a4fd 0040 32 sdram control register sdcr 32 h?a4fd 0044 32 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1240 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size refresh timer control/status register rtcsr 32 h'a4fd 0048 bsc 32 refresh timer counter rtcnt 32 h?a4fd 004c 32 refresh time constant register rtcor 32 h?a4fd 0050 32 sdram mode register sdmr2 ? h?a4fd 4xxx 16 sdram mode register sdmr3 ? h?a4fd5xxx 16 dma source address register_0 sar_0 32 h?a401 0020 dmac 16, 32 dma destination address register_0 dar_0 32 h?a401 0024 16, 32 dma transfer count register_0 dmatcr_0 32 h?a401 0028 16, 32 dma channel control register_0 chcr_0 32 h?a401 002c 8, 16, 32 dma source address register_1 sar_1 32 h?a401 0030 16, 32 dma destination address register_1 dar_1 32 h?a401 0034 16, 32 dma transfer count register_1 dmatcr_1 32 h?a401 0038 16, 32 dma channel control register _1 chcr_1 32 h?a401 003c 8, 16, 32 dma source address register_2 sar_2 32 h?a401 0040 16, 32 dma destination address register_2 dar_2 32 h?a401 0044 16, 32 dma transfer count register_2 dmatcr_2 32 h?a401 0048 16, 32 dma channel control register_2 chcr_2 32 h?a401 004c 8, 16, 32 dma source address register_3 sar_3 32 h?a401 0050 16, 32 dma destination address register_3 dar_3 32 h?a401 0054 16, 32 dma transfer count register_3 dmatcr_3 32 h?a401 0058 16, 32 dma channel control register_3 chcr_3 32 h?a401 005c 8, 16, 32 dma operation register dmaor 16 h?a401 0060 16 dma source address register_4 sar_4 32 h?a401 0070 16, 32 dma destination address register_4 dar_4 32 h?a401 0074 16, 32 dma transfer count register_4 dmatcr_4 32 h?a401 0078 16, 32 dma channel control register_4 chcr_4 32 h?a401 007c 8, 16, 32 dma source address register_5 sar_5 32 h?a401 0080 16, 32 dma destination address register_5 dar_5 32 h?a401 0084 16, 32 dma transfer count register_5 dmatcr_5 32 h?a401 0088 16, 32 dma channel control register_5 chcr_5 32 h?a401 008c 8, 16, 32 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1241 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size dma extended resource selector 0 dmars0 16 h'a409 0000 dmac 16 dma extended resource selector 1 dmars1 16 h'a409 0004 16 dma extended resource selector 2 dmars2 16 h'a409 0008 16 usbh/usbf clock control register uclkcr 8 h'a40a 0008 cpg 8, 16 * 2 frequency control register frqcr 16 h'a415 ff80 16 watchdog timer counter wtcnt 8 h'a415 ff84 wdt 8, 16 * 2 watchdog timer control/status register wtcsr 8 h'a415 ff86 8, 16 * 2 standby control register 3 stbcr3 8 h'a40a 0000 8 standby control register 4 stbcr4 8 h'a40a 0004 power-down modes 8 standby control register 5 stbcr5 8 h'a40a 0010 8 standby control register stbcr 8 h'a415 ff82 8 standby control register 2 stbcr2 8 h'a415 ff88 8 timer start register ts tr 8 h'a412 fe92 tmu 8 timer constant register_0 tcor_0 32 h'a412 fe94 32 timer counter_0 tcnt_0 32 h'a412 fe98 32 timer control register_0 tcr_0 16 h'a412 fe9c 16 timer constant register_1 tcor_1 32 h'a412 fea0 32 timer counter_1 tcnt_1 32 h'a412 fea4 32 timer control register_1 tcr_1 16 h'a412 fea8 16 timer constant register_2 tcor_2 32 h'a412 feac 32 timer counter_2 tcnt_2 32 h'a412 feb0 32 timer control register_2 tcr_2 16 h'a412 feb4 16 timer start register ts tr 16 h'a448 0000 tpu 16 timer control register_0 tcr_0 16 h'a448 0010 16 timer mode register_0 tmdr_0 16 h'a448 0014 16 timer i/o control register_0 tior_0 16 h'a448 0018 16 timer interrupt enable register_0 tier_0 16 h'a448 001c 16 timer status register_0 tsr_0 16 h'a448 0020 16 timer counter_0 tcnt_0 16 h'a448 0024 16 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1242 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size timer general register a_0 tgra_0 16 h'a448 0028 tpu 16 timer general register b_0 tgrb_0 16 h?a448 002c 16 timer general register c_0 tgrc_0 16 h?a448 0030 16 timer general register d_0 tgrd_0 16 h?a448 0034 16 timer control register_1 tcr_1 16 h?a448 0050 16 timer mode register_1 tmdr_1 16 h?a448 0054 16 timer i/o control register_1 tior_1 16 h?a448 0058 16 timer interrupt enable register_1 tier_1 16 h?a448 005c 16 timer status register_1 tsr_1 16 h?a448 0060 16 timer counter_1 tcnt_1 16 h?a448 0064 16 timer general register a_1 tgra_1 16 h?a448 0068 16 timer general register b_1 tgrb_1 16 h?a448 006c 16 timer general register c_1 tgrc_1 16 h?a448 0070 16 timer general register d_1 tgrd_1 16 h?a448 0074 16 timer control register_2 tcr_2 16 h?a448 0090 16 timer mode register_2 tmdr_2 16 h?a448 0094 16 timer i/o control register_2 tior_2 16 h?a448 0098 16 timer interrupt enable register_2 tier_2 16 h?a448 009c 16 timer status register_2 tsr_2 16 h?a448 00a0 16 timer counter_2 tcnt_2 16 h?a448 00a4 16 timer general register a_2 tgra_2 16 h?a448 00a8 16 timer general register b_2 tgrb_2 16 h?a448 00ac 16 timer general register c_2 tgrc_2 16 h?a448 00b0 16 timer general register d_2 tgrd_2 16 h?a448 00b4 16 timer control register_3 tcr_3 16 h?a448 00d0 16 timer mode register_3 tmdr_3 16 h?a448 00d4 16 timer i/o control register_3 tior_3 16 h?a448 00d8 16 timer interrupt enable register_3 tier_3 16 h?a448 00dc 16 timer status register_3 tsr_3 16 h?a448 00e0 16 timer counter_3 tcnt_3 16 h?a448 00e4 16 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1243 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size timer general register a_3 tgra_3 16 h?a448 00e8 tpu 16 timer general register b_3 tgrb_3 16 h?a448 00ec 16 timer general register c_3 tgrc_3 16 h?a448 00f0 16 timer general register d_3 tgrd_3 16 h?a448 00f4 16 compare match timer start register cmstr 16 h?a44a 0000 cmt 16 compare match timer control/status register_0 cmcsr_0 16 h?a44a 0010 16 compare match timer counter_0 cmcnt_0 32 h?a44a 0014 32 compare match timer constant register_0 cmcor_0 32 h?a44a 0018 32 compare match timer control/status register_1 cmcsr_1 16 h?a44a 0020 16 compare match timer counter_1 cmcnt_1 32 h?a44a 0024 32 compare match timer constant register_1 cmcor_1 32 h?a44a 0028 32 compare match timer control/status register_2 cmcsr_2 16 h?a44a 0030 16 compare match timer counter_2 cmcnt_2 32 h?a44a 0034 32 compare match timer constant register_2 cmcor_2 32 h?a44a 0038 32 compare match timer control/status register_3 cmcsr_3 16 h?a44a 0040 16 compare match timer counter_3 cmcnt_3 32 h?a44a 0044 32 compare match timer constant register_3 cmcor_3 32 h?a44a 0048 32 compare match timer control/status register_4 cmcsr_4 16 h?a44a 0050 16 compare match timer counter_4 cmcnt_4 32 h?a44a 0054 32 compare match timer constant register_4 cmcor_4 32 h?a44a 0058 32 64-hz counter r64cnt 8 h?a413 fec0 rtc 8 second counter rseccnt 8 h?a413 fec2 8 minute counter rmincnt 8 h?a413 fec4 8 hour counter rhrcnt 8 h?a413 fec6 8 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1244 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size day of week counter rwkcnt 8 h'a413 fec8 rtc 8 date counter rdaycnt 8 h?a413 feca 8 month counter rmoncnt 8 h?a413 fecc 8 year counter ryrcnt 16 h?a413 fece scif 16 second alarm register rsecar 8 h?a413 fed0 8 minute alarm register rminar 8 h?a413 fed2 8 hour alarm register rhrar 8 h?a413 fed4 8 day of week alarm register rwkar 8 h?a413 fed6 8 date alarm register rdayar 8 h?a413 fed8 8 month alarm register rmonar 8 h?a413 feda 8 rtc control register 1 rcr1 8 h?a413 fedc 8 rtc control register 2 rcr2 8 h?a413 fede 8 year alarm register ry rar 16 h?a413 fee0 16 rtc control register 3 rcr3 8 h?a413 fee4 8 serial mode register_0 scsmr_0 16 h?a443 0000 16 bit rate register_0 scbrr_0 8 h?a443 0004 8 serial control register_0 scscr_0 16 h?a443 0008 16 transmit data stop register_0 sctdsr_0 8 h?a443 000c 8 fifo error count register_0 scfer_0 16 h?a443 0010 16 serial status register_0 scssr_0 16 h?a443 0014 16 fifo control register_0 scfcr_0 16 h?a443 0018 16 fifo data count register_0 scfdr_0 16 h?a443 001c 16 transmit fifo data register_0 scftdr_0 8 h?a443 0020 8 receive fifo data register_0 scfrdr_0 8 h?a443 0024 8 serial mode register_0 scsmr_1 16 h?a443 8000 16 bit rate register_1 scbrr_1 8 h?a443 8004 8 serial control register_1 scscr_1 16 h?a443 8008 16 transmit data stop register_1 sctdsr_1 8 h?a443 800c 8 fifo error count register_1 scfer_1 16 h?a443 8010 16 serial status register_1 scssr_1 16 h?a443 8014 16 fifo control register_1 scfcr_1 16 h?a443 8018 16 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1245 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size fifo data count register_1 scfdr_1 16 h'a443 801c scif 16 transmit fifo data register_1 scftdr_1 8 h'a443 8020 8 receive fifo data register_1 scfrdr_1 8 h'a443 8024 8 irda mode register scimr 16 h'a444 0000 irda 16 i 2 c bus control register 1 iccr1 8 h'a447 0000 iic 8 i 2 c bus control register 2 iccr2 8 h'a447 0004 8 i 2 c bus mode register icmr 8 h'a447 0008 8 i 2 c bus interrupt enable register icier 8 h'a447 000c 8 i 2 c bus status register icsr 8 h'a447 0010 8 slave address register sar 8 h'a447 0014 8 i 2 c bus transmit data register icdrt 8 h'a447 0018 8 i 2 c bus receive data register icdrr 8 h'a447 001c 8 i 2 c bus master transfer clock select register iccks 8 h'a447 0020 8 mode register_0 simdr_0 16 h'a441 0000 siof 16 clock select register_0 siscr_0 16 h'a441 0002 16 transmit data assign register_0 sitdar_0 16 h'a441 0004 16 receive data assign register_0 sirdar_0 16 h'a441 0006 16 control data assign register_0 sicdar_0 16 h'a441 0008 16 control register_0 sictr_0 16 h'a441 000c 16 fifo control register_0 sifctr_0 16 h'a441 0010 16 status register_0 sistr_0 16 h'a441 0014 16 interrupt enable register_0 siier_0 16 h'a441 0016 16 transmit data register_0 sitdr_0 32 h'a441 0020 32 receive data register_0 sirdr_0 32 h'a441 0024 32 transmit control data register_0 sitcr_0 32 h'a441 0028 32 receive control data register_0 sircr_0 32 h'a441 002c 32 mode register_1 simdr_1 16 h'a441 8000 16 clock select register_1 siscr_1 16 h'a441 8002 16 transmit data assign register_1 sitdar_1 16 h'a441 8004 16 receive data assign register_1 sirdar_1 16 h'a441 8006 16 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1246 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size control data assign register_1 sicdar_1 16 h?a441 8008 siof 16 control register_1 sictr_1 16 h?a441 800c 16 fifo control register_1 sifctr_1 16 h?a441 8010 16 status register_1 sistr_1 16 h?a441 8014 16 interrupt enable register_1 siier_1 16 h?a441 8016 16 transmit data register_1 sitdr_1 32 h?a441 8020 32 receive data register_1 sirdr_1 32 h?a441 8024 32 transmit control data register_1 sitcr_1 32 h?a441 8028 32 receive control data register_1 sircr_1 32 h?a441 802c 32 afeif control register 1 actr1 16 h?a44e 0180 afeif 16 afeif control register 2 actr2 16 h?a44e 0182 16 afeif status register 1 astr1 16 h?a44e 0184 16 afeif status register 2 astr2 16 h?a44e 0186 16 make ratio count register mrcr 16 h?a44e 0188 16 minimum pose count register mpcr 16 h?a44e 018a 16 dial number queue dpnq 16 h?a44e 018c 16 ringing pulse counter rcnt 16 h?a44e 018e 16 afe control data register acdr 16 h?a44e 0190 16 afe status data register asdr 16 h?a44e 0192 16 transmit data fifo port tdfp 16 h?a44e 0194 16, 32 receive data fifo port rdfp 16 h?a44e 0198 16, 32 usb transceiver control register utrctl 16 h?a405 012c usbpmc 16 hc revision register usbhr 32 h?a442 8000 32 hc control register usbhc 32 h?a442 8004 32 hc command status register usbhcs 32 h?a442 8008 32 hc interrupt status register usbhis 32 h?a442 800c 32 hc interrupt enable register usbhie 32 h?a442 8010 32 hcinterruptdisable register usbhid 32 h?a442 8014 32 hchcca register usbhhcca 32 h?a442 8018 32 hc period current ed register usbhpced 32 h?a442 801c 32 hc control head ed usbhched 32 h?a442 8020 32 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1247 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size hc control current ed register usbhcced 32 h'a442 8024 usbpmc 32 hc bulk head ed register usbhbhed 32 h'a442 8028 32 hc bulk current ed register usbhbced 32 h'a442 802c 32 hc done head ed register usbhdhed 32 h'a442 8030 32 hc fm interval register usbhfi 32 h'a442 8034 32 hc fm remaining register usbhfr 32 h'a442 8038 32 hc fm number register usbhfn 32 h'a442 803c 32 hc periodic start register usbhps 32 h'a442 8040 32 hc ls threshold register usbhlst 32 h'a442 8044 32 hc rh descriptor a register usbhrda 32 h'a442 8048 32 hc rh descriptor b register usbhrdb 32 h'a442 804c 32 hc rh status register usbhrs 32 h'a442 8050 32 hc rh port status 1register usbhrps1 32 h'a442 8054 32 hc rh port status 2 register usbhrps2 32 h'a442 8058 32 interrupt flag register 0 ifr0 8 h'a442 0000 usbf 8 interrupt flag register 1 ifr1 8 h'a442 0001 8 interrupt flag register 2 ifr2 8 h'a442 0002 8 interrupt flag register 3 ifr3 8 h'a442 0003 8 interrupt enable register 0 ier0 8 h'a442 0004 8 interrupt enable register 1 ier1 8 h'a442 0005 8 interrupt enable register 2 ier2 8 h'a442 0006 8 interrupt enable register 3 ier3 8 h'a442 0007 8 interrupt select register 0 isr0 8 h'a442 0008 8 interrupt select register 1 isr1 8 h'a442 0009 8 interrupt select register 2 isr2 8 h'a442 000a 8 interrupt select register 3 isr3 8 h'a442 000b 8 ep0i data register epdr0i 8 h'a442 000c 8 ep0o data register epdr0o 8 h'a442 000d 8 ep0s data register epdr0s 8 h'a442 000e 8 ep1 data register epdr1 8 h'a442 0010 8 ep2 data register epdr2 8 h'a442 0014 8 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1248 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size ep3 data register epdr3 8 h'a442 0018 usbf 8 ep4 data register epdr4 8 h'a442 001c 8 ep5 data register epdr5 8 h'a442 0020 8 ep0o receive data size register epsz0o 8 h'a442 0024 8 ep1 receive data size register epsz1 8 h'a442 0025 8 ep4 receive data size register epsz4 8 h'a442 0026 8 data status register dasts 8 h'a442 0027 8 fifo clear register 0 fclr0 8 h'a442 0028 8 fifo clear register 1 fclr1 8 h'a442 0029 8 endpoint stall register 0 epstl0 8 h'a442 002a 8 endpoint stall register 1 epstl1 8 h'a442 002b 8 trigger register trg 8 h'a442 002c 8 dma transfer setting register dma 8 h'a442 002d 8 configuration value register cvr 8 h'a442 002e 8 control register 0 ctlr0 8 h'a442 002f 8 time stamp register h tsrh 8 h'a442 0030 8 time stamp register l tsrl 8 h'a442 0031 8 endpoint information register epir 8 h'a442 0032 8 interrupt flag register 4 ifr4 8 h'a442 0034 8 interrupt enable register 4 ier4 8 h'a442 0035 8 interrupt select register 4 isr4 8 h'a442 0036 8 control register 1 ctlr1 8 h'a442 0037 8 timer register h tmrh 8 h'a442 0038 8 timer register l tmrl 8 h'a442 0039 8 set time out register h stoh 8 h'a442 003a 8 set time out register l stol 8 h'a442 003b 8 palette data register 00 to palette data register ff ldpr00 to ldprff 32 h'a440 0000 to h'a440 03fc lcdc 32 lcdc input clock register ldickr 16 h'a440 0400 16 lcdc module type register ldmtr 16 h'a440 0402 16 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1249 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size lcdc data format register lddfr 16 h'a440 0404 lcdc 16 lcdc scan mode register ldsmr 16 h'a440 0406 16 lcdc data fetch start address register for upper display panel ldsaru 32 h'a440 0408 32 lcdc data fetch start address register for lower display panel ldsarl 32 h'a440 040c 32 lcdc fetch data line address offset register for display panel ldlaor 16 h'a440 0410 16 lcdc palette control register ldpalcr 16 h'a440 0412 16 lcdc horizontal character number register ldhcnr 16 h'a440 0414 16 lcdc horizontal synchronization signal register ldhsynr 16 h'a440 0416 16 lcdc vertical displayed line number register ldvdlnr 16 h'a440 0418 16 lcdc vertical total line number register ldvtlnr 16 h'a440 041a 16 lcdc vertical synchronization signal register ldvsynr 16 h'a440 041c 16 lcdc ac modulation signal toggle line number register ldaclnr 16 h'a440 041e 16 lcdc interrupt control register ldintr 16 h'a440 0420 16 lcdc power management mode register ldpmmr 16 h'a440 0424 16 lcdc power supply sequence period register ldpspr 16 h'a440 0426 16 lcdc control register ldcntr 16 h'a440 0428 16 lcdc user specified interrupt control register lduintr 16 h'a440 0434 16 lcdc user specified interrupt line number register lduintlnr 16 h'a440 0436 16 lcdc memory access interval number register ldlirnr 16 h'a440 0440 16 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1250 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size a/d data register a addra 16 h'a44c 0000 adc 16 a/d data register b addrb 16 h'a44c 0002 16 a/d data register c addrc 16 h'a44c 0004 16 a/d data register d addrd 16 h'a44c 0006 16 a/d control/status register adcsr 16 h'a44c 0008 16 d/a data register 0 dadr0 8 h'a44d 0000 dac 8 d/a data register 1 dadr1 8 h'a44d 0002 8 d/a control register dacr 8 h'a44d 0004 8 area 6 interface status register pcc0isr 8 h'a44b 0000 pcc 8 area 6 general control register pcc0gcr 8 h'a44b 0002 8 area 6 card status change register pcc0cscr 8 h'a44b 0004 8 area 6 card status change interrupt enable register pcc0cscier 8 h'a44b 0006 8 serial mode register scsmr 8 h'a449 0000 sim 8 bit rate register scbrr 8 h'a449 0002 8 serial control register scscr 8 h'a449 0004 8 transmit data register sctdr 8 h'a449 0006 8 serial status register scssr 8 h'a449 0008 8 receive data register scrdr 8 h'a449 000a 8 smart card mode register scscmr 8 h'a449 000c 8 serial control 2 register scsc2r 8 h'a449 000e 8 wait time register scwait 16 h'a449 0010 16 guard extension register scgrd 8 h'a449 0012 8 sampling register scsmpl 16 h'a449 0014 16 command register 0 cmdr0 8 h'a444 8000 mmc 8 command register 1 cmdr1 8 h'a444 8001 8 command register 2 cmdr2 8 h'a444 8002 8 command register 3 cmdr3 8 h'a444 8003 8 command register 4 cmdr4 8 h'a444 8004 8 command register 5 cmdr5 8 h'a444 8005 8 command start register cmdstrt 8 h'a444 8006 8 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1251 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size operation control register opcr 8 h?a444 800a mmc 8 card status register cstr 8 h?a444 800b 8 interrupt control register 0 intcr0 8 h?a444 800c 8 interrupt control register 1 intcr1 8 h?a444 800d 8 interrupt status register 0 intstr0 8 h?a444 800e 8 interrupt status register 1 intstr1 8 h?a444 800f 8 transfer clock control register clkon 8 h?a444 8010 8 command timeout control register ctocr 8 h?a444 8011 8 vdd/open drain control register vdcnt 8 h?a444 8012 8 transfer byte number count register tbcr 8 h?a444 8014 8 mode register moder 8 h?a444 8016 8 command type register cmdtyr 8 h?a444 8018 8 response type register rsptyr 8 h?a444 8019 8 transfer block number counter tbncr 16 h?a444 801a 16 response register 0 rspr0 8 h?a444 8020 8 response register 1 rspr1 8 h?a444 8021 8 response register 2 rspr2 8 h?a444 8022 8 response register 3 rspr3 8 h?a444 8023 8 response register 4 rspr4 8 h?a444 8024 8 response register 5 rspr5 8 h?a444 8025 8 response register 6 rspr6 8 h?a444 8026 8 response register 7 rspr7 8 h?a444 8027 8 response register 8 rspr8 8 h?a444 8028 8 response register 9 rspr9 8 h?a444 8029 8 response register 10 rspr10 8 h?a444 802a 8 response register 11 rspr11 8 h?a444 802b 8 response register 12 rspr12 8 h?a444 802c 8 response register 13 rspr13 8 h?a444 802d 8 response register 14 rspr14 8 h?a444 802e 8 response register 15 rspr15 8 h?a444 802f 8 response register 16 rspr16 8 h?a444 8030 8 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1252 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size response register d rsprd 8 h'a444 8031 mmc 8 data timeout register dtoutr 16 h?a444 8032 16 data register dr 16 h?a444 8040 16 fifo pointer clear register fifoclr 8 h?a444 8042 8 dma control register dmacr 8 h?a444 8044 8 interrupt control register 2 intcr2 8 h?a444 8046 8 interrupt status register 2 intstr2 8 h?a444 8048 8 break data register b bdrb 32 h?a4ff ff90 ubc 32 break data mask register b bdmrb 32 h?a4ff ff94 32 break control register brcr 32 h?a4ff ff98 32 execution times break regist er betr 16 h?a4ff ff9c 16 break address register b barb 32 h?a4ff ffa0 32 break address mask register b bamrb 32 h?a4ff ffa4 32 break bus cycle register b bbrb 16 h?a4ff ffa8 16 branch source register brsr 32 h?a4ff ffac 32 break address register a bara 32 h?a4ff ffb0 32 break address mask register a bamra 32 h?a4ff ffb4 32 break bus cycle register a bbra 16 h?a4ff ffb8 16 branch destination register brdr 32 h?a4ff ffbc 32 break asid register a basra 8 h?ffff ffe4 8 break asid register b basrb 8 h?ffff ffe8 8 port a control register pacr 16 h?a405 0100 pfc 16 port b control register pbcr 16 h?a405 0102 16 port c control register pccr 16 h?a405 0104 16 port d control register pdcr 16 h?a405 0106 16 port e control register pecr 16 h?a405 0108 16 port f control register pfcr 16 h?a405 010a 16 port g control register pgcr 16 h?a405 010c 16 port h control register phcr 16 h?a405 010e 16 port j control register pjcr 16 h?a405 0110 16 port k control register pkcr 16 h?a405 0112 16 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1253 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size port l control register plcr 16 h'a405 0114 pfc 16 port m control register pmcr 16 h'a405 0116 16 port p control register ppcr 16 h'a405 0118 16 port r control register prcr 16 h'a405 011a 16 port s control register pscr 16 h'a405 011c 16 port t control register ptcr 16 h'a405 011e 16 port u control register pucr 16 h'a405 0120 16 port v control register pvcr 16 h'a405 0122 16 pin select register a psela 16 h'a405 0124 16 pin select register b pselb 16 h'a405 0126 16 pin select register c pselc 16 h'a405 0128 16 pin select register d pseld 16 h'a405 012a 16 port a data register padr 8 h'a405 0140 i/o port 8 port b data register pbdr 8 h'a405 0142 8 port c data register pcdr 8 h'a405 0144 8 port d data register pddr 8 h'a405 0146 8 port e data register pedr 8 h'a405 0148 8 port f data register pfdr 8 h'a405 014a 8 port g data register pgdr 8 h'a405 014c 8 port h data register phdr 8 h'a405 014e 8 port j data register pjdr 8 h'a405 0150 8 port k data register pkdr 8 h'a405 0152 8 port l data register pldr 8 h'a405 0154 8 port m data register pmdr 8 h'a405 0156 8 port p data register ppdr 8 h'a405 0158 8 port r data register prdr 8 h'a405 015a 8 port s data register psdr 8 h'a405 015c 8 port t data register ptdr 8 h'a405 015e 8 port u data register pudr 8 h'a405 0160 8 port v data register pvdr 8 h'a405 0162 8 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1254 of 1458 rej09b0033-0300 register name abbreviation number of bits address module access size instruction register sdir 16 h'a410 0200 h-udi 16 id register sdidh 16 h'a410 0214 16, 32 id register sdidl 16 h'a410 0216 16 notes: 1. entries under access size indicate t he size for accessing (reading/writing) the control registers. specifying the size s other than listed ones result s in the wrong operation. 2. 8 bits when reading and 16 bits when writing. section 37 list of registers rev. 3.00 jan. 18, 2008 page 1255 of 1458 rej09b0033-0300 37.2 register bits register addresses and bit names of the on-chip peripheral modules are described below. each line covers eight bits, and 16-bit and 32-bit re gisters are shown as 2 or 4 lines, respectively. register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sv mmucr ? ? rc rc ? tf ix at vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn vpn ? ? pteh asid asid asid asid asid asid asid asid ? ? ? ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ppn ? v ptel ? pr pr sz c d sh ? ttb mmu ccr2 ? ? ? ? ? ? ? ? cache ? ? ? ? ? ? ? le ? ? ? ? ? ? w3load w3lock ? ? ? ? ? ? w2load w2lock ccr3 ? ? ? ? ? ? ? ? csize7 csize6 csize5 csize4 csize3 csize2 csize1 csize0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ccr1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cf cb wt ce section 37 list of registers rev. 3.00 jan. 18, 2008 page 1256 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module intevt2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? exception handling ? ? ? ? intevt2 intevt2 intevt2 intevt2 intevt2 intevt2 intevt2 intevt2 intevt2 intevt2 ? ? tra ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tra tra tra tra tra tra tra tra ? ? expevt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? expevt expevt expevt expevt expevt expevt expevt expevt expevt expevt expevt expevt intevt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? intevt intevt intevt intevt intevt intevt intevt intevt intevt intevt intevt intevt tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea tea iprf adc dmac(2) intc usbf cmt iprg scif0 scif1 ? ? ? ? ? ? ? ? iprh pinta pintb tpu iic ipri siof0 siof1 mmc pcc iprj ? ? ? ? usbh sdhi afeif irr5 adcir ? dei5r dei4r ? ? scif1ir scif0ir section 37 list of registers rev. 3.00 jan. 18, 2008 page 1257 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module irr6 ? ? siof1ir siof0ir ? ? pintbr pintar intc irr7 ? ? ? iicir tpi3r tpi2r tpi1r tpi0r irr8 mmci3r mmci2r mmci1r mmci0r afecir ? ? sdir irr9 pccir usbhir ? cmir ? usbfi1r usbfi0r ? irr0 ? tmu_ sunir irq5r irq4r irq3r irq2r irq1r irq0r irr1 ? ? ? ? dei3r dei2r dei1r dei0r irr2 ? ? ? sslir ? ? ? lcdcir irr3 tendir txir rxir erir ? cuir prir atir irr4 ? tuni2r tuni1r tuni0r itir ? ? rcmir icr1 mai irqlvl blmsk ? irq51s irq50s irq41s irq40s irq31s irq30s irq21s irq20s irq11s irq10s irq01s irq00s icr2 pint15s pint14s pint13s pint12s pint11s pint10s pint9s pint8s pint7s pint6s pint5s pint4s pint3s pint2s pint1s pint0s pinter pint15e pint14e pint13e pint12e pint11e pint10e pint9e pint8e pint7e pint6e pint5e pint4e pint3e pint2e pint1e pint0e iprc irq3 irq2 irq1 irq0 iprd ? tmu (tmu_sun1) irq5 irq4 ipre dmac(1) ? ? ? ? lcdc ? ? ssl icr0 nmil ? ? ? ? ? ? nmie ? ? ? ? ? ? ? ? ipra tmu0 tmu1 tmu2 rtc iprb wdt ref sim ? ? ? ? cmncr ? ? ? ? ? ? ? ? bsc ? ? ? ? ? ? ? ? ? bsd ? map block dprty1 dprty0 dmaiw2 dmaiw1 dmaiw0 dmaiwa ? endian ? hizmem hizcnt section 37 list of registers rev. 3.00 jan. 18, 2008 page 1258 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module cs0bcr ? iww2 iww1 iww0 iwrwd iwrwd iwrwd iwrws2 bsc iwrws1 iwrws0 iwrrd2 iwrrd1 iwrrd0 iwrrs2 iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? cs2bcr ? iww2 iww1 iww0 iwrwd iwrwd iwrwd iwrws2 iwrws1 iwrws0 iwrrd2 iwrrd1 iwrrd0 iwrrs2 iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? cs3bcr ? iww2 iww1 iww0 iwrwd iwrwd iwrwd iwrws2 iwrws1 iwrws0 iwrrd2 iwrrd1 iwrrd0 iwrrs2 iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? cs4bcr ? iww2 iww1 iww0 iwrwd iwrwd iwrwd iwrws2 iwrws1 iwrws0 iwrrd2 iwrrd1 iwrrd0 iwrrs2 iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? cs5abcr ? iww2 iww1 iww0 iwrwd iwrwd iwrwd iwrws2 iwrws1 iwrws0 iwrrd2 iwrrd1 iwrrd0 iwrrs2 iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? cs5bbcr ? iww2 iww1 iww0 iwrwd iwrwd iwrwd iwrws2 iwrws1 iwrws0 iwrrd2 iwrrd1 iwrrd0 iwrrs2 iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? cs6abcr ? iww2 iww1 iww0 iwrwd iwrwd iwrwd iwrws2 iwrws1 iwrws0 iwrrd2 iwrrd1 iwrrd0 iwrrs2 iwrrs1 iwrrs0 type3 type2 type1 type0 ? bsz1 bsz0 ? ? ? ? ? ? ? ? ? cs6bbcr ? iww2 iww1 iww0 iwrwd iwrwd iwrwd iwrws2 iwrws1 iwrws0 iwrrd2 iwrrd1 iwrrd0 iwrrs2 iwrrs1 iwrrs0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1259 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module cs6bbcr type3 type2 type1 type0 ? bsz1 bsz0 ? bsc ? ? ? ? ? ? ? ? cs0wcr * 1 ? ? ? ? ? ? ? ? ? ? ? bas ? ? ? ? ? ? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ? ? ? ? hw1 hw0 cs0wcr * 2 ? ? ? ? ? ? ? ? ? ? ? ben ? ? bw1 bw0 ? ? ? ? ? w3 w2 w1 w0 wm ? ? ? ? ? ? cs0wcr * 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? bw1 bw0 ? ? ? ? ? w3 w2 w1 w0 wm ? ? ? ? ? ? cs2wcr * 1 ? ? ? ? ? ? ? ? ? ? ? bas ? ? ? ? ? ? ? ? ? wr3 wr2 wr1 wr0 wm ? ? ? ? ? ? cs2wcr * 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? a2cl1 a2cl0 ? ? ? ? ? ? ? cs3wcr * 1 ? ? ? ? ? ? ? ? ? ? ? bas ? ? ? ? ? ? ? ? ? wr3 wr2 wr1 wr0 wm ? ? ? ? ? ? cs3wcr * 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? trp1 trp0 ? trcd1 trcd0 ? a3cl1 a3cl0 ? ? trwl1 trwl0 ? trc1 trc0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1260 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module cs4wcr * 1 ? ? ? ? ? ? ? ? bsc ? ? ? bas ? ww2 ww1 ww0 ? ? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ? ? ? ? hw1 hw0 cs4wcr * 2 ? ? ? ? ? ? ? ? ? ? ? ben ? ? bw1 bw0 ? ? ? sw1 sw0 w3 w2 w1 w0 wm ? ? ? ? hw1 hw0 cs5awcr * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ww2 ww1 ww0 ? ? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ? ? ? ? hw1 hw0 cs5bwcr * 1 ? ? ? ? ? ? ? ? ? ? ? bas ? ww2 ww1 ww0 ? ? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ? ? ? ? hw1 hw0 cs5bwcr * 5 ? ? ? ? ? ? ? ? ? ? sa1 sa0 ? ? ? ? ? ted3 ted2 ted1 ted0 pcw3 pcw2 pcw1 pcw0 wm ? ? teh3 teh2 teh1 teh0 cs6awcr * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ? ? ? ? hw1 hw0 cs6bwcr * 1 ? ? ? ? ? ? ? ? ? ? ? bas ? ? ? ? ? ? ? sw1 sw0 wr3 wr2 wr1 wr0 wm ? ? ? ? hw1 hw0 cs6bwcr * 5 ? ? ? ? ? ? ? ? ? ? sa1 sa0 ? ? ? ? section 37 list of registers rev. 3.00 jan. 18, 2008 page 1261 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module cs6bwcr * 5 ? ted3 ted2 ted1 ted0 pcw3 pcw2 pcw1 bsc pcw0 wm ? ? teh3 teh2 teh1 teh0 sdcr ? ? ? ? ? ? ? ? ? ? ? a2row1 a2row0 ? a2col1 a2col0 ? ? deep ? rfsh rmode pdown bactv ? ? ? a3row1 a3row0 ? a3col1 a3col0 rtcsr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cmf cmie cks2 cks1 cks0 rrc2 rrc1 rrc0 rtcnt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rtcor ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sar_0 dmac dar_0 dmatcr_0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1262 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module chcr_0 ? ? ? ? ? ? ? ? dmac do tl ? ? ? ? am al dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 dl ds tb ts1 ts0 ie te de sar_1 dar_1 dmatcr_1 chcr_1 ? ? ? ? ? ? ? ? do tl ? ? ? ? am al dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 dl ds tb ts1 ts0 ie te de sar_2 dar_2 dmatcr_2 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1263 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module dmatcr_2 dmac chcr_2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 ? ? tb ts1 ts0 ie te de sar_3 dar_3 dmatcr_3 chcr_3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 ? ? tb ts1 ts0 ie te de sar_4 dar_4 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1264 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module dmatcr_4 dmac chcr_4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 ? ? tb ts1 ts0 ie te de sar_5 dar_5 dmatcr_5 chcr_5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 ? ? tb ts1 ts0 ie te de dmaor ? ? cms1 cms0 ? ? pr1 pr0 ? ? ? ? ? ae nmif dme dmars0 c1mid5 c1mid4 c1mid3 c1mid2 c1mid1 c1mid0 c1rid1 c1rid0 c0mid5 c0mid4 c0mid3 c0mid2 c0mid1 c0mid0 c0rid1 c0rid0 dmars1 c3mid5 c3mid4 c3mid3 c3mid2 c3mid1 c3mid0 c3rid1 c3rid0 c2mid5 c2mid4 c2mid3 c2mid2 c2mid1 c2mid0 c2rid1 c2rid0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1265 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module dmars2 c5mid5 c5mid4 c5mid3 c5mid2 c5mid1 c5mid0 c5rid1 c5rid0 dmac c4mid5 c4mid4 c4mid3 c4mid2 c4mid1 c4mid0 c4rid1 c4rid0 uclkcr usscs1 usscs0 ? ? ? ? ? ? cpg frqcr pll2en ? ? ckoen ? ? stc1 stc0 ? ? ifc1 ifc0 ? pfc2 pfc1 pfc0 wtcnt wdt wtcsr tme wt/it rsts wovf iovf cks2 cks1 cks0 stbcr3 mstp37 mstp36 mstp35 ? mstp33 mstp32 mstp31 mstp30 stbcr4 ? ? mstp45 mstp44 mstp43 mstp42 mstp41 mstp40 stbcr5 ? mstp56 ? mstp54 ? mstp52 mstp51 mstp50 power- down modes stbcr stby ? ? stbxtl ? mstp2 mstp1 ? stbcr2 mstp10 mstp9 mstp8 mstp7 mstp6 mstp5 ? mstp3 tstr ? ? ? ? ? str2 str1 str0 tmu tcor_0 tcnt_0 tcr_0 ? ? ? ? ? ? ? unf ? ? unie ? ? tpsc2 tpsc1 tpsc0 tcor_1 tcnt_1 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1266 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tcr_1 ? ? ? ? ? ? ? unf tmu ? ? unie ? ? tpsc2 tpsc1 tpsc0 tcor_2 tcnt_2 tcr_2 ? ? ? ? ? ? ? unf ? ? unie ? ? tpsc2 tpsc1 tpsc0 tstr ? ? ? ? ? ? ? ? tpu ? ? ? ? cst3 cst2 cst1 cst0 tcr_0 ? ? ? ? ? ? ? ? cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_0 ? ? ? ? ? ? ? ? ? bfwt bfb bfa ? md2 md1 md0 tior_0 ? ? ? ? ? ? ? ? ? ? ? ? ? ioa2 ioa1 ioa0 tier_0 ? ? ? ? ? ? ? ? ? ? tc1eu tc1ev tg1ed tg1ec tg1eb tg1ea tsr_0 ? ? ? ? ? ? ? ? ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_0 tgra_0 tgrb_0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1267 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tgrc_0 tpu tgrd_0 tcr_1 ? ? ? ? ? ? ? ? cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_1 ? ? ? ? ? ? ? ? ? bfwt bfb bfa ? md2 md1 md0 tior_1 ? ? ? ? ? ? ? ? ? ? ? ? ? ioa2 ioa1 ioa0 tier_1 ? ? ? ? ? ? ? ? ? ? tc1eu tc1ev tg1ed tg1ec tg1eb tg1ea tsr_1 ? ? ? ? ? ? ? ? ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_1 tgra_1 tgrb_1 tgrc_1 tgrd_1 tcr_2 ? ? ? ? ? ? ? ? cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_2 ? ? ? ? ? ? ? ? ? bfwt bfb bfa ? md2 md1 md0 tior_2 ? ? ? ? ? ? ? ? ? ? ? ? ? ioa2 ioa1 ioa0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1268 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tier_2 ? ? ? ? ? ? ? ? tpu ? ? tc1eu tc1ev tg1ed tg1ec tg1eb tg1ea tsr_2 ? ? ? ? ? ? ? ? tcfd ? tcfu tcfv tgfd tgfc tgfb tgfa tcnt_2 tgra_2 tgrb_2 tgrc_2 tgrd_2 tcr_3 ? ? ? ? ? ? ? ? cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_3 ? ? ? ? ? ? ? ? ? bfwt bfb bfa ? md2 md1 md0 tior_3 ? ? ? ? ? ? ? ? ? ? ? ? ? ioa2 ioa1 ioa0 tier_3 ? ? ? ? ? ? ? ? ? ? tc1eu tc1ev tg1ed tg1ec tg1eb tg1ea tsr_3 ? ? ? ? ? ? ? ? tcfd ? tcfu tcfv tgfd tgfc tgfb tgfa tcnt_3 tgra_3 tgrb_3 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1269 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module tgrc_3 tpu tgrd_3 cmstr ? ? ? ? ? ? ? ? cmt ? ? ? str4 str3 str2 str1 str0 cmcsr_0 cmf ovf ? ? ? ? cms cmm ? ? cmr1 cmr0 ? cks2 cks1 cks0 cmcnt_0 cmcor_0 cmcsr_1 cmf ovf ? ? ? ? cms cmm ? cmr1 cmr0 ? cks2 cks1 cks0 cmcnt_1 cmcor_1 cmcsr_2 cmf ovf ? ? ? ? cms cmm ? ? cmr1 cmr0 ? cks2 cks1 cks0 cmcnt_2 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1270 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module cmcnt_2 cmt cmcor_2 cmcsr_3 cmf ovf ? ? ? ? cms cmm ? ? cmr1 cmr0 ? cks2 cks1 cks0 cmcnt_3 cmcor_3 cmcsr_4 cmf ovf ? ? ? ? cms cmm ? ? cmr1 cmr0 ? cks2 cks1 cks0 cmcnt_4 cmcor_4 r64cnt ? 1hz 2hz 4hz 8hz 16hz 32hz 64hz rtc rseccnt ? ten's position of seconds one's position of seconds rmincnt ? ten's position of minutes one's position of minutes section 37 list of registers rev. 3.00 jan. 18, 2008 page 1271 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module rhrcnt ? ? ten's position of hours one's position of hours rtc rwkcnt ? ? ? ? ? day of week rdaycnt ? ? ten's position of dates one's position of dates rmoncnt ? ? ? ten's position of months ten's position of months ryrcnt thousand's position of years hundred's position of years ten's position of years one's position of years rsecar enb ten's position of seconds one's position of seconds rminar enb ten's position of minutes one's position of minutes rhrar enb ? ten's position of hours one's position of hours rwkar enb ? ? ? ? day of week rdayar enb ? ten's position of dates one's position of dates rmonar enb ? ? ten's position of months one's position of months rcr1 cf ? ? cie aie ? ? af rcr2 pef pes2 pes1 pes0 rtcen adj reset start ryrar thousand's position of years hundred's position of years ten's position of years one's position of years rcr3 yaen ? ? ? ? ? ? ? scsmr_0 ? ? ? ? ? src2 src1 src0 scif c/a chr pe o/e stop ? cks1 cks0 scbrr_0 scbrd7 scbrd6 scbrd5 scbrd4 scbrd3 scbrd2 scbrd1 scbrd0 scscr_0 tdrqe rdrqe ? ? tsie erie brie drie tie rie te re ? ? cke1 cke0 sctdsr_0 scfer_0 ? ? per5 per4 per3 per2 per1 per0 ? ? fer5 fer4 fer3 fer2 fer1 fer0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1272 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module scssr_0 ? ? ? ? ? ? orer tsf scif er tend tdfe brk fer per rdf dr scfcr_0 tse tcrst ? ? ? rstrg2 rstrg1 rstrg0 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop scfdr_0 ? t6 t5 t4 t3 t2 t1 t0 ? r6 r5 r4 r3 r2 r1 r0 scftdr_0 scftd7 scftd6 scftd5 scftd4 scftd3 scftd2 scftd1 scftd0 scfrdr_0 scfrd7 scfrd6 scfrd5 scfrd4 scfrd3 scfrd2 scfrd1 scfrd0 scsmr_1 ? ? ? ? ? src2 src1 src0 c/a chr pe o/e stop ? cks1 cks0 scbrr_1 scbrd7 scbrd6 scbrd5 scbrd4 scbrd3 scbrd2 scbrd1 scbrd0 scscr_1 tdrqe rdrqe ? ? tsie erie brie drie tie rie te re ? ? cke1 cke0 sctdsr_1 scfer_1 ? ? per5 per4 per3 per2 per1 per0 ? ? fer5 fer4 fer3 fer2 fer1 fer0 scssr_1 ? ? ? ? ? ? orer tsf er tend tdfe brk fer per rdf dr scfcr_1 tse tcrst ? ? ? rstrg2 rstrg1 rstrg0 rtrg1 rtrg0 ttrg1 ttrg0 mce tfrst rfrst loop scfdr_1 ? t6 t5 t4 t3 t2 t1 t0 ? r6 r5 r4 r3 r2 r1 r0 scftdr_1 scftd7 scftd6 scftd5 scftd4 scftd3 scftd2 scftd1 scftd0 scfrdr_1 scfrd7 scfrd6 scfrd5 scfrd4 scfrd3 scfrd2 scfrd1 scfrd0 scimr ? ? ? ? ? ? ? ? irda irmod ick3 ick2 ick1 ick0 psel ? ? iccr1 ice rcvd mst trs ? ? ? ? iic iccr2 bbsy scp sdao sdaop sclo ? iicrst ? icmr mls ? ? ? bcwp bc2 bc1 bc0 icier tie teie rie nakie stie acke ackbr ackbt icsr tdre tend rdrf nackf stop al/ove aas adz section 37 list of registers rev. 3.00 jan. 18, 2008 page 1273 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module sar sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs iic icdrt icdrt7 icdrt6 icdrt5 icdrt4 icdrt3 icdrt2 icdrt1 icdrt0 icdrr icdrr7 icdrr6 icdrr5 icdrr4 icdrr3 icdrr2 icdrr1 icdrr0 simdr_0 trmd1 trmd0 syncat redg fl3 fl2 fl1 fl0 siof txdiz rcim syncac syncdl ? ? ? ? siscr_0 mssel msimm ? brps4 brps3 brps2 brps1 brps0 ? ? ? ? ? brdv2 brdv1 brdv0 sitdar_0 tdle ? ? ? tdla3 tdla2 tdla1 tdla0 tdre tlrep ? ? tdra3 tdra2 tdra1 tdra0 sirdar_0 rdle ? ? ? rdla3 rdla2 rdla1 rdla0 rdre ? ? ? rdra3 rdra2 rdra1 rdra0 sicdar_0 cd0e ? ? ? cd0a3 cd0a2 cd0a1 cd0a0 cd1e ? ? ? cd1a3 cd1a2 cd1a1 cd1a0 sictr_0 scke fse ? ? ? ? txe rxe ? ? ? ? ? ? txrst rxrst sifctr_0 tfwm2 tfwm1 tfwm0 tfua4 tfua3 tfua2 tfua1 tfua0 rfwm2 rfwm1 rfwm0 rfua4 rfua3 rfua2 rfua1 rfua0 sistr_0 ? tcrdy tfemp tdreq ? rcrdy rfful rdreq ? ? saerr fserr tfovf tfudf rfudf rfovf siier_0 tdmae tcrdye tfempe tdreqe rdmae rcrdye rffule rdreqe ? ? saerre fserre tfovfe tfudfe rfudfe rfovfe sitdr_0 sitdl15 sitdl14 sitdl13 sitdl12 sitdl11 sitdl10 sitdl9 sitdl8 sitdl7 sitdl6 sitdl5 sitdl4 sitdl3 sitdl2 sitdl1 sitdl0 sitdr15 sitdr14 sitdr13 sitdr12 sitdr11 sitdr10 sitdr9 sitdr8 sitdr7 sitdr6 sitdr5 sitdr4 sitdr3 sitdr2 sitdr1 sitdr0 sirdr_0 sirdl15 sirdl14 sirdl13 sirdl12 sirdl11 sirdl10 sirdl9 sirdl8 sirdl7 sirdl6 sirdl5 sirdl4 sirdl3 sirdl2 sirdl1 sirdl0 sirdr15 sirdr14 sirdr13 sirdr12 sirdr11 sirdr10 sirdr9 sirdr8 sirdr7 sirdr6 sirdr5 sirdr4 sirdr3 sirdr2 sirdr1 sirdr0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1274 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module sitcr_0 sitc015 sitc014 sitc013 sitc012 sitc011 sitc010 sitc09 sitc08 siof sitc07 sitc06 sitc05 sitc04 sitc03 sitc02 sitc01 sitc00 sitc115 sitc114 sitc113 sitc112 sitc111 sitc110 sitc19 sitc18 sitcr_0 sitc17 sitc16 sitc15 sitc14 sitc13 sitc12 sitc11 sitc10 sircr_0 sirc015 sirc014 sirc013 sirc012 sirc011 sirc010 sirc09 sirc08 sirc07 sirc06 sirc05 sirc04 sirc03 sirc02 sirc01 sirc00 sirc115 sirc114 sirc113 sirc112 sirc111 sirc110 sirc19 sirc18 sirc17 sirc16 sirc15 sirc14 sirc13 sirc12 sirc11 sirc10 simdr_1 trmd1 trmd0 syncat redg fl3 fl2 fl1 fl0 txdiz rcim syncac syncdl ? ? ? ? siscr_1 mssel msimm ? brps4 brps3 brps2 brps1 brps0 ? ? ? ? ? brdv2 brdv1 brdv0 sitdar_1 tdle ? ? ? tdla3 tdla2 tdla1 tdla0 tdre tlrep ? ? tdra3 tdra2 tdra1 tdra0 sirdar_1 rdle ? ? ? rdla3 rdla2 rdla1 rdla0 rdre ? ? ? rdra3 rdra2 rdra1 rdra0 sicdar_1 cd0e ? ? ? cd0a3 cd0a2 cd0a1 cd0a0 cd1e ? ? ? cd1a3 cd1a2 cd1a1 cd1a0 sictr_1 scke fse ? ? ? ? txe rxe ? ? ? ? ? ? txrst rxrst sifctr_1 tfwm2 tfwm1 tfwm0 tfua4 tfua3 tfua2 tfua1 tfua0 rfwm2 rfwm1 rfwm0 rfua4 rfua3 rfua2 rfua1 rfua0 sistr_1 ? tcrdy tfemp tdreq ? rcrdy rfful rdreq ? ? saerr fserr tfovf tfudf rfudf rfovf siier_1 tdmae tcrdye tfempe tdreqe rdmae rcrdye rffule rdreqe ? ? saerre fserre tfovfe tfudfe rfudfe rfovfe sitdr_1 sitdl15 sitdl14 sitdl13 sitdl12 sitdl11 sitdl10 sitdl9 sitdl8 sitdl7 sitdl6 sitdl5 sitdl4 sitdl3 sitdl2 sitdl1 sitdl0 sitdr15 sitdr14 sitdr13 sitdr12 sitdr11 sitdr10 sitdr9 sitdr8 sitdr7 sitdr6 sitdr5 sitdr4 sitdr3 sitdr2 sitdr1 sitdr0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1275 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module sirdr_1 sirdl15 sirdl14 sirdl13 sirdl12 sirdl11 sirdl10 sirdl9 sirdl8 siof sirdl7 sirdl6 sirdl5 sirdl4 sirdl3 sirdl2 sirdl1 sirdl0 sirdr15 sirdr14 sirdr13 sirdr12 sirdr11 sirdr10 sirdr9 sirdr8 sirdr7 sirdr6 sirdr5 sirdr4 sirdr3 sirdr2 sirdr1 sirdr0 sitcr_1 sitc015 sitc014 sitc013 sitc012 sitc011 sitc010 sitc09 sitc08 sitc07 sitc06 sitc05 sitc04 sitc03 sitc02 sitc01 sitc00 sitc115 sitc114 sitc113 sitc112 sitc111 sitc110 sitc19 sitc18 sitcr_1 sitc17 sitc16 sitc15 sitc14 sitc13 sitc12 sitc11 sitc10 sircr_1 sirc015 sirc014 sirc013 sirc012 sirc011 sirc010 sirc09 sirc08 sirc07 sirc06 sirc05 sirc04 sirc03 sirc02 sirc01 sirc00 sirc115 sirc114 sirc113 sirc112 sirc111 sirc110 sirc19 sirc18 sirc17 sirc16 sirc15 sirc14 sirc13 sirc12 sirc11 sirc10 actr1 hc ? ? ? ? ? ? ? afeif dlb ? ? ffsz2 ffsz1 ffsz0 te re actr2 ? ? ? ? ? ? ? ? ? ? ? dpst pps rcen ? rlyc astr1 ? ? ? ? tfem rffm them rhfm ? ? ? ? tfe rff the rhf astr2 ? ? ? ? ? ? dpem rdetm ? ? ? ? ? ? dpe rdet mrcr ? ? ? ? ? ? mrcr9 mrcr8 mrcr7 mrcr6 mrcr5 mrcr4 mrcr3 mrcr2 mrcr1 mrcr0 mpcr mpcr15 mpcr14 mpcr13 mpcr12 mpcr11 mpcr10 mpcr9 mpcr8 mpcr7 mpcr6 mpcr5 mpcr4 mpcr3 mpcr2 mpcr1 mpcr0 dpnq dn03 dn02 dn01 dn00 dn13 dn12 dn11 dn10 dn23 dn22 dn21 dn20 dn33 dn32 dn31 dn30 rcnt rcnt15 rcnt14 rcnt13 rcnt12 rcnt11 rcnt10 rcnt9 rcnt8 rcnt7 rcnt6 rcnt5 rcnt4 rcnt3 rcnt2 rcnt1 rcnt0 acdr acdr15 acdr14 acdr13 acdr12 acdr11 acdr10 acdr9 acdr8 acdr7 acdr6 acdr5 acdr4 acdr3 acdr2 acdr1 acdr0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1276 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module asdr asdr15 asdr14 asdr13 asdr12 asdr11 asdr10 asdr9 asdr8 afeif asdr7 asdr6 asdr5 asdr4 asdr3 asdr2 asdr1 asdr0 tdfp tdfp15 tdfp14 tdfp13 tdfp12 tdfp11 tdfp10 tdfp9 tdfp8 tdfp7 tdfp6 tdfp5 tdfp4 tdfp3 tdfp2 tdfp1 tdfp0 rdfp rdfp15 rdfp14 rdfp13 rdfp12 rdfp11 rdfp10 rdfp9 rdfp8 rdfp7 rdfp6 rdfp5 rdfp4 rdfp3 rdfp2 rdfp1 rdfp0 utrctl ? ? ? ? ? ? ? drv usb pmc ? ? ? ? ? ? usb_ trans usb_sel usbhr ? ? ? ? ? ? ? ? usbh ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 usbhc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rwe rwc ir hcfs1 hcfs0 ble cle ie ple cbsr1 cbsr0 usbhcs ? ? ? ? ? ? ? ? ? ? ? ? ? ? soc1 soc0 ? ? ? ? ? ? ? ? ? ? ? ? ocr blf clf hcr usbhis ? oc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rhsc fno ue rd sf wdh so usbhie mie oc ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rhsc fno ue rd sf wdh so usbhid mie oc ? ? ? ? ? ? ? ? ? ? ? ? ? ? section 37 list of registers rev. 3.00 jan. 18, 2008 page 1277 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module usbhid ? ? ? ? ? ? ? ? usbh ? rhsc fno ue rd sf wdh so usbhhcca hcca23 hcca22 hcca21 hcca20 hcca19 hcca18 hcca17 hcca16 hcca15 hcca14 hcca13 hcca12 hcca11 hcca10 hcca9 hcca8 hcca7 hcca6 hcca5 hcca4 hcca3 hcca2 hcca1 hcca0 ? ? ? ? ? ? ? ? usbhpced pced27 pced26 pced25 pced24 pced23 pced22 pced21 pced20 pced19 pced18 pced17 pced16 pced15 pced14 pced13 pced12 pced11 pced10 pced9 pced8 pced7 pced6 pced5 pced4 pced3 pced2 pced1 pced0 ? ? ? ? usbhched ched27 ched26 ched25 ched24 ched23 ched22 ched21 ched20 ched19 ched18 ched17 ched16 ched15 ched14 ched13 ched12 ched11 ched10 ched9 ched8 ched7 ched6 ched5 ched4 ched3 ched2 ched1 ched0 ? ? ? ? usbhcced cced27 cced26 cced25 cced24 cced23 cced22 cced21 cced20 cced19 cced18 cced17 cced16 cced15 cced14 cced13 cced12 cced11 cced10 cced9 cced8 cced7 cced6 cced5 cced4 cced3 cced2 cced1 cced0 ? ? ? ? usbhbhed bhed27 bhed26 bhed25 bhed24 bhed23 bhed22 bhed21 bhed20 bhed19 bhed18 bhed17 bhed16 bhed15 bhed14 bhed13 bhed12 bhed11 bhed10 bhed9 bhed8 bhed7 bhed6 bhed5 bhed4 bhed3 bhed2 bhed1 bhed0 ? ? ? ? usbhbced bced27 bced26 bced25 bced24 bced23 bced22 bced21 bced20 bced19 bced18 bced17 bced16 bced15 bced14 bced13 bced12 bced11 bced10 bced9 bced8 bced7 bced6 bced5 bced4 bced3 bced2 bced1 bced0 ? ? ? ? usbhdhed dh27 dh26 dh25 dh24 dh23 dh22 dh21 dh20 dh19 dh18 dh17 dh16 dh15 dh14 dh13 dh12 dh11 dh10 dh9 dh8 dh7 dh6 dh5 dh4 dh3 dh2 dh1 dh0 ? ? ? ? section 37 list of registers rev. 3.00 jan. 18, 2008 page 1278 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module usbhfi fit fsmps14 fsmps13 fsmps12 fsmps11 fsmps10 fsmps9 fsmps8 usbh fsmps7 fsmps6 fsmps5 fsmps4 fsmps3 fsmps2 fsmps1 fsmps0 ? ? fi13 fi12 fi11 fi10 fi9 fi8 fi7 fi6 fi5 fi4 fi3 fi2 fi1 fi0 usbhfr frt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? fr13 fr12 fr11 fr10 fr9 fr8 fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 usbhfn ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? fn15 fn14 fn13 fn12 fn11 fn10 fn9 fn8 fn7 fn6 fn5 fn4 fn3 fn2 fn1 fn0 usbhps ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ps13 ps12 ps11 ps10 ps9 ps8 ps7 ps6 ps5 ps4 ps3 ps2 ps1 ps0 usbhlst ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? lst11 lst10 lst9 lst8 lst7 lst6 lst5 lst4 lst3 lst2 lst1 lst0 usbhrda potpgt7 potpgt6 potpgt5 potpgt4 potpgt3 potpgt2 potpgt1 potpgt0 ? ? ? ? ? ? ? ? ? ? ? nocp ocpm dt nps psm ndp7 ndp6 ndp5 ndp4 ndp3 ndp2 ndp1 ndp0 usbhrdb ppcm15 ppcm14 ppcm13 ppcm12 ppcm11 ppcm10 ppcm9 ppcm8 ppcm7 ppcm6 ppcm5 ppcm4 ppcm3 ppcm2 ppcm1 ppcm0 dr15 dr14 dr13 dr12 dr11 dr10 dr9 dr8 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 usbhrs crwe ? ? ? ? ? ? ? ? ? ? ? ? ? ocic lpsc section 37 list of registers rev. 3.00 jan. 18, 2008 page 1279 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module usbhrs drwe ? ? ? ? ? ? ? usbh ? ? ? ? ? ? oci lps usbhrps1 ? ? ? ? ? ? ? ? ? ? ? prsc ocic pssc pesc csc ? ? ? ? ? ? lsda pps ? ? ? prs poci pss pes ccs usbhrps2 ? ? ? ? ? ? ? ? ? ? ? prsc ocic pssc pesc csc ? ? ? ? ? ? lsda pps ? ? ? prs poci pss pes ccs ifr0 brst ep1full ep2tr ep2empty setupts ep0ots ep0itr ep0its usbf ifr1 ? ? ? ? vbusmn ep3tr ep3ts vbusf ifr2 ? ? surss sursf cfdn sof setc seti ifr3 ? ? ? ? ep5tr ep5ts ep4tf ep4ts ier0 brst ie ep1full is ep2tr ie ep2 empty ie setupts ie ep0ots ie ep0itr ie ep0its ie ier1 ? ? ? ? ? ep3tr ie ep3ts ie vbusf ie ier2 ? ? ? surse ie cfdn ie sofe ie setce ie setie ie ier3 ? ? ? ? ep5tr ie ep5ts ie ep4tf ie ep4ts ie isr0 brst is ep1full is ep2tr is ep2 empty is setupts is ep0ots is ep0itr is ep0its is isr1 ? ? ? ? ? ep3tr is ep3ts is vbusf is isr2 ? ? ? surse is cfdn is sofe is setce is setie is isr3 ? ? ? ? ep5tr is ep5ts is ep4tf is ep4ts is epdr0i d7 d6 d5 d4 d3 d2 d1 d0 epdr0o d7 d6 d5 d4 d3 d2 d1 d0 epdr0s d7 d6 d5 d4 d3 d2 d1 d0 epdr1 d7 d6 d5 d4 d3 d2 d1 d0 epdr2 d7 d6 d5 d4 d3 d2 d1 d0 epdr3 d7 d6 d5 d4 d3 d2 d1 d0 epdr4 d7 d6 d5 d4 d3 d2 d1 d0 epdr5 d7 d6 d5 d4 d3 d2 d1 d0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1280 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module epsz0o usbf epsz1 epsz4 dasts ? ? ep3de ep2de ? ? ? ep0ide fclr0 ? ep3clr ep1clr ep2clr ? ? ep0oclr ep0iclr fclr1 ? ? ? ep5cclr ? ? ep5clr ep4clr epstl0 ? ? ? ? ep3stl ep2stl ep1stl ep0stl epstl1 ? ? ? ? ? ? ep5stl ep4stl trg ? ep3pkte ep1rdfn ep2pkte ? ep0srdfn ep0ordfn ep0ipkte dma ? ? ? ? ? pullupe ep2dmae ep1dmae cvr cnfv1 cnfv0 intv1 intv0 ? altv2 altv1 altv0 ctlr0 ? ? ? rwups rsme ? asce ? tsrh ? ? ? ? ? d10 d9 d8 tsrl d7 d6 d5 d4 d3 d2 d1 d0 epir d7 d6 d5 d4 d3 d2 d1 d0 ifr4 ? ? ? ? ? ? ? tmout ier4 ? ? ? ? ? ? ? tmout ie isr4 ? ? ? ? ? ? ? tmout is ctlr1 ? ? ? ? ? ? tmraclr tmren tmrh d15 d14 d13 d12 d11 d10 d9 d8 tmrl d7 d6 d5 d4 d3 d2 d1 d0 stoh d15 d14 d13 d12 d11 d10 d9 d8 stol d7 d6 d5 d4 d3 d2 d1 d0 ? ? ? ? ? ? ? ? lcdc paldnn23 paldnn22 paldnn21 paldnn20 paldnn19 paldnn18 paldnn17 paldnn16 paldnn15 paldnn14 paldnn13 paldnn12 paldnn11 paldnn10 paldnn9 paldnn8 ldprnn (nn:h'00 to h'ff) paldnn7 paldnn6 paldnn5 paldnn4 paldnn3 paldnn2 paldnn1 paldnn0 ldickr ? ? icksel1 icksel0 ? ? ? ? ? ? dcdr5 dcdr4 dcdr3 dcdr2 dcdr1 dcdr0 ldmtr flmpol cl1pol disppol dpol ? mcnt cl1cnt cl2cnt ? ? miftyp5 miftyp4 miftyp3 miftyp2 miftyp1 miftyp0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1281 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module lddfr ? ? ? ? ? ? ? pabd lcdc ? dsp color6 dsp color5 dsp color4 dsp color3 dsp color2 dsp color1 dsp color0 ldsmr ? ? rot ? ? ? au1 au0 ? ? ? ? ? ? ? ? ldsaru ? ? ? ? ? ? sau25 sau24 sau23 sau22 sau21 sau20 sau19 sau18 sau17 sau16 sau15 sau14 sau13 sau12 sau11 sau10 sau9 sau8 sau7 sau6 sau5 sau4 ? ? ? ? ldsarl ? ? ? ? ? ? sal25 sal24 sal23 sal22 sal21 sal20 sal19 sal18 sal17 sal16 sal15 sal14 sal13 sal12 sal11 sal10 sal9 sal8 sal7 sal6 sal5 sal4 ? ? ? ? ldlaor lao15 lao14 lao13 lao12 lao11 lao10 lao9 lao8 lao7 lao6 lao5 lao4 lao3 lao2 lao1 lao0 ldpalcr ? ? ? ? ? ? ? ? ? ? ? pals ? ? ? palen ldhcnr hdcn7 hdcn6 hdcn5 hdcn4 hdcn3 hdcn2 hdcn1 hdcn0 htcn7 htcn6 htcn5 htcn4 htcn3 htcn2 htcn1 htcn0 ldhsynr hsynw3 hsynw2 hsynw1 hsynw0 ? ? ? ? hsynp7 hsynp6 hsynp5 hsynp4 hsynp3 hsynp2 hsynp1 hsynp0 ldvdlnr ? ? ? ? ? vdln10 vdln9 vdln8 vdln7 vdln6 vdln5 vdln4 vdln3 vdln2 vdln1 vdln0 ldvtlnr ? ? ? ? ? vtln10 vtln9 vtln8 vtln7 vtln6 vtln5 vtln4 vtln3 vtln2 vtln1 vtln0 ldvsynr vsynw3 vsynw2 vsynw1 vsynw0 ? vsynp10 vsynp9 vsynp8 vsynp7 vsynp6 vsynp5 vsynp4 vsynp3 vsynp2 vsynp1 vsynp0 ldaclnr ? ? ? ? ? ? ? ? ? ? ? acln4 acln3 acln2 acln1 acln0 ldintr minten finten vsinten veinten mints fints vsints veints ? ? ? ? ? ? ? ? section 37 list of registers rev. 3.00 jan. 18, 2008 page 1282 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module ldpmmr onc3 onc2 onc1 onc0 offd3 offd2 offd1 offd0 lcdc ? vcpe vepe done ? ? lps1 lps0 ldpspr ona3 ona2 ona1 ona0 onb3 onb2 onb1 onb0 offe3 offe2 offe1 offe0 offf3 offf2 offf1 offf0 ldcntr ? ? ? ? ? ? ? ? ? ? ? don2 ? ? ? don lduintr ? ? ? ? ? ? ? uinten ? ? ? ? ? ? ? uints lduintlnr ? ? ? ? ? uintln10 uintln9 uintln8 uintln7 uintln6 uintln5 uintln4 uintln3 uintln2 uintln1 uintln0 ldlirnr ? ? ? ? ? ? ? ? lirn7 lirn6 lirn5 lirn4 lirn3 lirn2 lirn1 lirn0 addra ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 adc ad1 ad0 ? ? ? ? ? ? addrb ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? addrc ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? addrd ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? adcsr adf adie adst multi1 cks ch2 ch1 ch0 adcr trg1 trg0 scn tesvd1 resvd2 ? dadr0 dac dadr1 dacr daoe1 daoe0 ? ? ? ? ? ? pcc0isr p0rdy/ ireq p0mwp p0vs2 p0vs1 p0cd2 p0cd1 p0bvd2/ p0spkr p0bvd1/ p0stsch g pcc pcc0gcr p0drve p0pccr p0pcct p0use p0mmod p0pa25 p0pa24 p0reg pcc0cscr p0scdi ? p0ireq p0sc p0cdc p0rc p0bw p0bd pcc0cscier p0cre ireqe1 ireqe0 p0sce p0cde p0re p0bwe p0bde section 37 list of registers rev. 3.00 jan. 18, 2008 page 1283 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module scsmr ? ? ? o/e ? ? ? ? sim scbrr ? ? ? ? ? brr2 brr1 brr0 scscr tie rie te re wait_ie teie cke1 cke0 sctdr sctd7 sctd6 sctd5 sctd4 sctd3 sctd2 sctd1 sctd0 scssr tdre rdrf orer ers per tend wait_er ? scrdr scrd7 scrd6 scrd5 scrd4 scrd3 scrd2 scrd1 scrd0 scscmr ? lcb pb ? sdir sinv rst smif scsc2r eio ? ? ? ? ? ? ? scgrd scgrd7 scgrd6 scgrd5 scgrd4 scgrd3 scgrd2 scgrd1 scgrd0 scwait scwait15 scwait14 scwait13 scwait12 scwait11 scwait10 scwait9 scwait8 scwait7 scwait6 scwait5 scwait4 scwait3 scwait2 scwait1 scwait0 scsmpl ? ? ? ? ? scsmpl10 scsmpl9 scsmpl8 scsmpl7 scsmpl6 scsmpl5 scsmpl4 scsmpl3 scsmpl2 scsmpl1 scsmpl0 cmdr0 start host index5 index4 index3 index2 index1 index0 mmc cmdr1 cmdr17 cmdr16 cmdr15 cmdr14 cmdr13 cmdr12 cmdr11 cmdr10 cmdr2 cmdr27 cmdr26 cmdr25 cmdr24 cmdr23 cmdr22 cmdr21 cmdr20 cmdr3 cmdr37 cmdr36 cmdr35 cmdr34 cmdr33 cmdr32 cmdr31 cmdr30 cmdr4 cmdr47 cmdr46 cmdr45 cmdr44 cmdr43 cmdr42 cmdr41 cmdr40 cmdr5 crc6 crc5 crc4 crc3 crc2 crc1 crc0 end cmdstrt ? ? ? ? ? ? ? start opcr cmdoff ? rd_conti dataen ? ? ? ? cstr busy fifo_ full fifo_ empty cwre dtbusy dtbusy_ tu ? req intcr0 feie ffie drpie dtie crpie cmdie dbsyie btie intcr1 intq2e intq1e intq0e ? ? crcerie dterie cterie intstr0 fei ffi drpi dti crpi cmdi dbsyi bti intstr1 ? ? ? ? wreri crceri dteri cteri clkon clkon ? ? ? csel3 csel2 csel1 csel0 ctocr ? ? ? ? ? ? ? ctsel0 vdcnt vddon odmod ? ? ? ? ? ? tbcr ? ? ? ? c3 c2 c1 c0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1284 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module moder ? ? ? ? ? ? ? ? mmc cmdtyr ? ty6 ty5 ty4 ty3 ty2 ty1 ty0 rsptyr ? ? rty5 rty4 rty3 rty2 rty1 rty0 tbncr tbncr15 tbncr14 tbncr13 tbncr12 tbncr11 tbncr10 tbncr9 tbncr8 tbncr7 tbncr6 tbncr5 tbncr4 tbncr3 tbncr2 tbncr1 tbncr0 rspr0 rspr07 rspr06 rspr05 rspr04 rspr03 rspr02 rspr01 rspr00 rspr1 rspr17 rspr16 rspr15 rspr14 rspr13 rspr12 rspr11 rspr10 rspr2 rspr27 rspr26 rspr25 rspr24 rspr23 rspr22 rspr21 rspr20 rspr3 rspr37 rspr36 rspr35 rspr34 rspr33 rspr32 rspr31 rspr30 rspr4 rspr47 rspr46 rspr45 rspr44 rspr43 rspr42 rspr41 rspr40 rspr5 rspr57 rspr56 rspr55 rspr54 rspr53 rspr52 rspr51 rspr50 rspr6 rspr67 rspr66 rspr65 rspr64 rspr63 rspr62 rspr61 rspr60 rspr7 rspr77 rspr76 rspr75 rspr74 rspr73 rspr72 rspr71 rspr70 rspr8 rspr87 rspr86 rspr85 rspr84 rspr83 rspr82 rspr81 rspr80 rspr9 rspr97 rspr96 rspr95 rspr94 rspr93 rspr92 rspr91 rspr90 rspr10 rspr107 rspr106 rspr105 rspr104 rspr103 rspr102 rspr101 rspr100 rspr11 rspr117 rspr116 rspr115 rspr114 rspr113 rspr112 rspr111 rspr110 rspr12 rspr127 rspr126 rspr125 rspr124 rspr123 rspr122 rspr121 rspr120 rspr13 rspr137 rspr136 rspr135 rspr134 rspr133 rspr132 rspr131 rspr130 rspr14 rspr147 rspr146 rspr145 rspr144 rspr143 rspr142 rspr141 rspr140 rspr15 rspr157 rspr156 rspr155 rspr154 rspr153 rspr152 rspr151 rspr150 rspr16 rspr167 rspr166 rspr165 rspr164 rspr163 rspr162 rspr161 rspr160 rsprd ? ? ? rsprd4 rsprd3 rsprd2 rsprd1 rsprd0 dtoutr dtoutr15 dtoutr14 dtoutr13 dtoutr12 dtoutr11 dtoutr10 dtoutr9 dtoutr8 dtoutr7 dtoutr6 dtoutr5 dtoutr4 dtoutr3 dtoutr2 dtoutr1 dtoutr0 dr dr15 dr14 dr13 dr12 dr11 dr10 dr9 dr8 dr7 dr6 dr5 dr4 dr3 dr2 dr1 dr0 fifoclr fifoclr7 fifoclr6 fifoclr5 fifoclr4 fifoclr3 fifoclr2 fifoclr1 fifoclr0 dmacr dmaen auto ? ? ? set2 set1 set0 intcr2 intrq3e ? ? ? ? ? ? frdyie intstr2 ? ? ? ? ? ? frdy_tu frdyi section 37 list of registers rev. 3.00 jan. 18, 2008 page 1285 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module bdrb bdb31 bdb30 bdb29 bdb28 bdb27 bdb26 bdb25 bdb24 ubc bdb23 bdb22 bdb21 bdb20 bdb19 bdb18 bdb17 bdb16 bdb15 bdb14 bdb13 bdb12 bdb11 bdb10 bdb9 bdb8 bdb7 bdb6 bdb5 bdb4 bdb3 bdb2 bdb1 bdb0 bdmrb bdmb31 bdmb30 bdmb29 bdmb28 bdmb27 bdmb26 bdmb25 bdmb24 bdmb23 bdmb22 bdmb21 bdmb20 bdmb19 bdmb18 bdmb17 bdmb16 bdmb15 bdmb14 bdmb13 bdmb12 bdmb11 bdmb10 bdmb9 bdmb8 bdmb7 bdmb6 bdmb5 bdmb4 bdmb3 bdmb2 bdmb1 bdmb0 brcr ? ? ? ? ? ? ? ? ? ? baswa baswb ? ? ? ? scmfca scmfcb scmfda scmfdb pcte pcba ? ? dbeb pcbb ? ? seq ? ? etbe betr ? ? ? ? bet11 bet10 bet9 bet8 bet7 bet6 bet5 bet4 bet3 bet2 bet1 bet0 barb bab31 bab30 bab29 bab28 bab27 bab26 bab25 bab24 bab23 bab22 bab21 bab20 bab19 bab18 bab17 bab16 bab15 bab14 bab13 bab12 bab11 bab10 bab9 bab8 bab7 bab6 bab5 bab4 bab3 bab2 bab1 bab0 bamrb bamb31 bamb30 bamb29 bamb28 bamb27 bamb26 bamb25 bamb24 bamb23 bamb22 bamb21 bamb20 bamb19 bamb18 bamb17 bamb16 bamb15 bamb14 bamb13 bamb12 bamb11 bamb10 bamb9 bamb8 bamb7 bamb6 bamb5 bamb4 bamb3 bamb2 bamb1 bamb0 bbrb ? ? ? ? ? ? xye xys cdb1 cdb0 idb1 idb0 rwb1 rwb0 szb1 szb0 brsr svf ? ? ? bsa27 bsa26 bsa25 bsa24 bsa23 bsa22 bsa21 bsa20 bsa19 bsa18 bsa17 bsa16 bsa15 bsa14 bsa13 bsa12 bsa11 bsa10 bsa9 bsa8 bsa7 bsa6 bsa5 bsa4 bsa3 bsa2 bsa1 bsa0 bara baa31 baa30 baa29 baa28 baa27 baa26 baa25 baa24 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1286 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module bara baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 ubc baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 bamra bama31 bama30 bama29 bama28 bama27 bama26 bama25 bama24 bama23 bama22 bama21 bama20 bama19 bama18 bama17 bama16 bama15 bama14 bama13 bama12 bama11 bama10 bama9 bama8 bama7 bama6 bama5 bama4 bama3 bama2 bama1 bama0 bbra ? ? ? ? ? ? ? ? cda1 cda0 ida1 ida0 rwa1 rwa0 sza1 sza0 brdr dvf ? ? ? bda27 bda26 bda25 bda24 bda23 bda22 bda21 bda20 bda19 bda18 bda17 bda16 bda15 bda14 bda13 bda12 bda11 bda10 bda9 bda8 bda7 bda6 bda5 bda4 bda3 bda2 bda1 bda0 basra basa7 basa6 basa5 basa4 basa3 basa2 basa1 basa0 basrb basb7 basb6 basb5 basb4 basb3 basb2 basb1 basb0 pacr pa7md1 pa7md0 pa6md1 pa6md0 pa5md1 pa5md0 pa4md1 pa4md0 pfc pa3md1 pa3md0 pa2md1 pa2md0 pa1md1 pa1md0 pa0md1 pa0md0 pbcr pb7md1 pb7md0 pb6md1 pb6md0 pb5md1 pb5md0 pb4md1 pb4md0 pb3md1 pb3md0 pb2md1 pb2md0 pb1md1 pb1md0 pb0md1 pb0md0 pccr pc7md1 pc7md0 pc6md1 pc6md0 pc5md1 pc5md0 pc4md1 pc4md0 pc3md1 pc3md0 pc2md1 pc2md0 pc1md1 pc1md0 pc0md1 pc0md0 pdcr pd7md1 pd7md0 pd6md1 pd6md0 pd5md1 pd5md0 pd4md1 pd4md0 pd3md1 pd3md0 pd2md1 pd2md0 pd1md1 pd1md0 pd0md1 pd0md0 pecr ? ? pe6md1 ? pe5md1 ? pe4md1 pe4md0 pe3md1 pe3md0 pe2md1 pe2md0 pe1md1 pe1md0 pe0md1 pe0md0 pfcr ? ? pf6md1 pf6md0 pf5md1 pf5md0 pf4md1 pf4md0 pf3md1 pf3md0 pf2md1 pf2md0 pf1md1 pf1md0 pf0md1 pf0md0 pgcr ? ? pg6md1 pg6md0 pg5md1 pg5md0 pg4md1 pg4md0 pg3md1 pg3md0 pg2md1 pg2md0 pg1md1 pg1md0 pg0md1 pg0md0 phcr ? ? ph6md1 ph6md0 ph5md1 ph5md0 ph4md1 ph4md0 ph3md1 ph3md0 ph2md1 ph2md0 ph1md1 ph1md0 ph0md1 ph0md0 section 37 list of registers rev. 3.00 jan. 18, 2008 page 1287 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module pjcr ? ? pj6md1 pj6md0 pj5md1 pj5md0 pj4md1 pj4md0 pfc pj3md1 pj3md0 pj2md1 pj2md0 pj1md1 pj1md0 pj0md1 pj0md0 pkcr ? ? ? ? ? ? ? ? pk3md1 pk3md0 pk2md1 pk2md0 pk1md1 pk1md0 pk0md1 pk0md0 plcr pl7md1 pl7md0 pl6md1 pl6md0 pl5md1 pl5md0 pl4md1 pl4md0 pl3md1 pl3md0 ? ? ? ? ? ? pmcr pm7md1 pm7md0 pm6md1 pm6md0 pm5md1 pm5md0 pm4md1 pm4md0 pm3md1 pm3md0 pm2md1 pm2md0 pm1md1 pm1md0 pm0md1 pm0md0 ppcr ? ? ? ? ? ? pp4md1 pp4md0 pp3md1 pp3md0 pp2md1 pp2md0 pp1md1 pp1md0 pp0md1 pp0md0 prcr pr7md1 pr7md0 pr6md1 pr6md0 pr5md1 pr5md0 pr4md1 pr4md0 pr3md1 pr3md0 pr2md1 pr2md0 pr1md1 pr1md0 pr0md1 pr0md0 pscr ? ? ? ? ? ? ps4md1 ps4md0 ps3md1 ps3md0 ps2md1 ps2md0 ps1md1 ps1md0 ps0md1 ps0md0 ptcr ? ? ? ? ? ? pt4md1 pt4md0 pt3md1 pt3md0 pt2md1 pt2md0 pt1md1 pt1md0 pt0md1 pt0md0 pucr ? ? ? ? ? ? pu4md1 pu4md0 pu3md1 pu3md0 pu2md1 pu2md0 pu1md1 pu1md0 pu0md1 pu0md0 pvcr ? ? ? ? ? ? pv4md1 pv4md0 pv3md1 pv3md0 pv2md1 pv2md0 pv1md1 pv1md0 pv0md1 pv0md0 psela psela15 psela14 psela13 psela12 psela11 psela10 psela9 psela8 psela7 psela6 psela5 psela4 psela3 psela2 psela1 psela0 pselb pselb15 pselb14 pselb13 pselb12 pselb11 pselb10 pselb9 pselb8 ? ? ? ? ? ? ? pselb0 pselc pselc15 pselc14 pselc13 pselc12 pselc11 pselc10 pselc9 pselc8 ? ? ? ? ? ? ? ? pseld ? pseld14 pseld13 pseld12 ? pseld10 pseld9 pseld8 ? pseld6 pseld5 pseld4 ? pseld2 pseld1 pseld0 padr pa7dt pa6dt pa5dt pa4dt pa3dt pa2dt pa1dt pa0dt i/o port pbdr pb7dt pb6dt pb5dt pb4dt pb3dt pb2dt pb1dt pb0dt pcdr pc7dt pc6dt pc5dt pc4dt pc3dt pc2dt pc1dt pc0dt section 37 list of registers rev. 3.00 jan. 18, 2008 page 1288 of 1458 rej09b0033-0300 register abbreviation bit 31/23/15/7 bit 30/22/14/6 bit 29/21/13/5 bit 28/20/12/4 bit 27/19/11/3 bit 26/18/10/2 bit 25/17/9/1 bit 24/16/8/0 module pddr pd7dt pd6dt pd5dt pd4dt pd3dt pd2dt pd1dt pd0dt i/o port pedr ? pe6dt pe5dt pe4dt pe3dt pe2dt pe1dt pe0dt pfdr ? pf6dt pf5dt pf4dt pf3dt pf2dt pf1dt pf0dt pgdr ? pg6dt pg5dt pg4dt pg3dt pg2dt pg1dt pg0dt phdr ? ph6dt ph5dt ph4dt ph3dt ph2dt ph1dt ph0dt pjdr ? pj6dt pj5dt pj4dt pj3dt pj2dt pj1dt pj0dt pkdr ? ? ? ? pk3dt pk2dt pk1dt pk0dt pldr pl7dt pl6dt pl5dt pl4dt pl3dt ? ? ? pmdr pm7dt pm6dt pm5dt pm4dt pm3dt pm2dt pm1dt pm0dt ppdr ? ? ? pp4dt pp3dt pp2dt pp1dt pp0dt prdr pr7dt pr6dt pr5dt pr4dt pr3dt pr2dt pr1dt pr0dt psdr ? ? ? ps4dt ps3dt ps2dt ps1dt ps0dt ptdr ? ? ? pt4dt pt3dt pt2dt pt1dt pt0dt pudr ? ? ? pu4dt pu3dt pu2dt pu1dt pu0dt pvdr ? ? ? pv4dt pv3dt pv2dt pv1dt pv0dt sdir t17 t16 t15 t14 t13 t12 t11 t10 h ? udi ? ? ? ? ? ? ? ? sdidh did31 did30 did29 did28 did27 did26 did25 did24 did23 did22 did21 did20 did19 did18 did17 did16 sdidl did15 did14 did13 did12 did11 did10 did9 did8 did7 did6 did5 did4 did3 did2 did1 did0 notes: 1. specified memory type is normal area or byte selection sram. 2. specified memory type is burst rom (asynchronous). 3. specified memory type is burst rom (synchronous). 4. specified memory type is sdram. 5. specified memory type is pcmcia. section 37 list of registers rev. 3.00 jan. 18, 2008 page 1289 of 1458 rej09b0033-0300 37.3 register states in each operating mode register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module mmucr initialized initialized retained retained retained mmu pteh initialized initialized retained retained retained ptel initialized initialized retained retained retained ttb initialized initialized retained retained retained ccr2 initialized initialized retained retained retained cache ccr3 initialized initialized retained retained retained ccr1 initialized initialized retained retained retained intevt2 initialized initialized retained ? retained tra initialized initialized retained ? retained exception handling expevt initialized initialized retained ? retained intevt initialized initialized retained ? retained tea initialized initialized retained ? retained iprf initialized initialized retained ? retained intc iprg initialized initialized retained ? retained iprh initialized initialized retained ? retained ipri initialized initialized retained ? retained iprj initialized initialized retained ? retained irr5 initialized initialized retained ? retained irr6 initialized initialized retained ? retained irr7 initialized initialized retained ? retained irr8 initialized initialized retained ? retained irr9 initialized initialized retained ? retained irr0 initialized initialized retained ? retained irr1 initialized initialized retained ? retained irr2 initialized initialized retained ? retained irr3 initialized initialized retained ? retained irr4 initialized initialized retained ? retained icr1 initialized initialized retained ? retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1290 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module icr2 initialized initialized retained ? retained intc pinter initialized initialized retained ? retained iprc initialized initialized retained ? retained iprd initialized initialized retained ? retained ipre initialized initialized retained ? retained icr0 initialized initialized retained ? retained ipra initialized initialized retained ? retained iprb initialized initialized retained ? retained cmncr initialized initialized retained ? retained bsc cs0bcr initialized initialized retained ? retained cs2bcr initialized initialized retained ? retained cs3bcr initialized initialized retained ? retained cs4bcr initialized initialized retained ? retained cs5abcr initialized initialized retained ? retained cs5bbcr initialized initialized retained ? retained cs6abcr initialized initialized retained ? retained cs6bbcr initialized initialized retained ? retained cs0wcr initialized initialized retained ? retained cs2wcr initialized initialized retained ? retained cs3wcr initialized initialized retained ? retained cs4wcr initialized initialized retained ? retained cs5awcr initialized initialized retained ? retained cs5bwcr initialized initialized retained ? retained cs6awcr initialized initialized retained ? retained cs6bwcr initialized initialized retained ? retained sdcr initialized initialized retained ? retained rtcsr initialized initialized retained ? retained rtcnt initialized initialized retained ? retained rtcor initialized initialized retained ? retained sar_0 initialized initialized retained retained retained dmac dar_0 initialized initialized retained retained retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1291 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module dmatcr_0 initialized initialized retained retained retained dmac chcr_0 initialized initialized retained retained retained sar_1 initialized initialized retained retained retained dar_1 initialized initialized retained retained retained dmatcr_1 initialized initialized retained retained retained chcr_1 initialized initialized retained retained retained sar_2 initialized initialized retained retained retained dar_2 initialized initialized retained retained retained dmatcr_2 initialized initialized retained retained retained chcr_2 initialized initialized retained retained retained sar_3 initialized initialized retained retained retained dar_3 initialized initialized retained retained retained dmatcr_3 initialized initialized retained retained retained chcr_3 initialized initialized retained retained retained sar_4 initialized initialized retained retained retained dar_4 initialized initialized retained retained retained dmatcr_4 initialized initialized retained retained retained chcr_4 initialized initialized retained retained retained sar_5 initialized initialized retained retained retained dar_5 initialized initialized retained retained retained dmatcr_5 initialized initialized retained retained retained chcr_5 initialized initialized retained retained retained dmaor initialized initialized retained retained retained dmars0 initialized initialized retained retained retained dmars1 initialized initialized retained retained retained dmars2 initialized initialized retained retained retained uclkcr initialized retained retained ? retained cpg frqcr initialized * 6 retained retained ? retained wtcnt initialized * 6 retained retained ? retained wdt wtcsr initialized * 6 retained retained ? retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1292 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module stbcr3 initialized retained retained ? retained stbcr4 initialized retained retained ? retained stbcr5 initialized retained retained ? retained power-down modes stbcr initialized retained retained ? retained stbcr2 initialized retained retained ? retained tstr initialized initialized initialized * 2 initialized retained tmu tcor_0 initialized initialized retained retained retained tcnt_0 initialized initialized retained retained retained tcr_0 initialized initialized retained retained retained tcor_1 initialized initialized retained retained retained tcnt_1 initialized initialized retained retained retained tcr_1 initialized initialized retained retained retained tcor_2 initialized initialized retained retained retained tcnt_2 initialized initialized retained retained retained tcr_2 initialized initialized retained retained retained tstr initialized initialized retained retained retained tpu tcr_0 initialized initialized retained retained retained tmdr_0 initialized initialized retained retained retained tior_0 initialized initialized retained retained retained tier_0 initialized initialized retained retained retained tsr_0 initialized initialized retained retained retained tcnt_0 initialized initialized retained retained retained tgra_0 initialized initialized retained retained retained tgrb_0 initialized initialized retained retained retained tgrc_0 initialized initialized retained retained retained tgrd_0 initialized initialized retained retained retained tcr_1 initialized initialized retained retained retained tmdr_1 initialized initialized retained retained retained tior_1 initialized initialized retained retained retained tier_1 initialized initialized retained retained retained tsr_1 initialized initialized retained retained retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1293 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module tcnt_1 initialized initialized retained retained retained tpu tgra_1 initialized initialized retained retained retained tgrb_1 initialized initialized retained retained retained tgrc_1 initialized initialized retained retained retained tgrd_1 initialized initialized retained retained retained tcr_2 initialized initialized retained retained retained tmdr_2 initialized initialized retained retained retained tior_2 initialized initialized retained retained retained tier_2 initialized initialized retained retained retained tsr_2 initialized initialized retained retained retained tcnt_2 initialized initialized retained retained retained tgra_2 initialized initialized retained retained retained tgrb_2 initialized initialized retained retained retained tgrc_2 initialized initialized retained retained retained tgrd_2 initialized initialized retained retained retained tcr_3 initialized initialized retained retained retained tmdr_3 initialized initialized retained retained retained tior_3 initialized initialized retained retained retained tier_3 initialized initialized retained retained retained tsr_3 initialized initialized retained retained retained tcnt_3 initialized initialized retained retained retained tgra_3 initialized initialized retained retained retained tgrb_3 initialized initialized retained retained retained tgrc_3 initialized initialized retained retained retained tgrd_3 initialized initialized retained retained retained cmstr initialized initialized retained retained retained cmt cmcsr_0 initialized initialized retained retained retained cmcnt_0 initialized initialized retained retained retained cmcor_0 initialized initialized retained retained retained cmcsr_1 initialized initialized retained retained retained cmcnt_1 initialized initialized retained retained retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1294 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module cmcor_1 initialized initialized retained retained retained cmt cmcsr_2 initialized initialized retained retained retained cmcnt_2 initialized initialized retained retained retained cmcor_2 initialized initialized retained retained retained cmcsr_3 initialized initialized retained retained retained cmcnt_3 initialized initialized retained retained retained cmcor_3 initialized initialized retained retained retained cmcsr_4 initialized initialized retained retained retained cmcnt_4 initialized initialized retained retained retained cmcor_4 initialized initialized retained retained retained r64cnt retained retained retained retained retained rtc rseccnt retained retained retained retained retained rmincnt retained retained retained retained retained rhrcnt retained retained retained retained retained rwkcnt retained retained retained retained retained rdaycnt retained retained retained retained retained rmoncnt retained retained retained retained retained ryrcnt retained retained retained retained retained rsecar retained * 3 retained retained retained retained rminar retained * 3 retained retained retained retained rhrar retained * 3 retained retained retained retained rwkar retained * 3 retained retained retained retained rdayar retained * 3 retained retained retained retained rmonar retained * 3 retained retained retained retained rcr1 initialized initialized retained retained retained rcr2 initialized initialized * 4 retained retained retained ryrar retained retained retained retained retained rcr3 initialized retained retained retained retained scsmr_0 initialized initialized re tained retained retained scif scbrr_0 initialized initialized retained retained retained scscr_0 initialized initialized retained retained retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1295 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module sctdsr_0 initialized initialized retained retained retained scif scfer_0 initialized initialized retained retained retained scssr_0 initialized initialized retained retained retained scfcr_0 initialized initialized retained retained retained scfdr_0 initialized initialized retained retained retained scftdr_0 initialized initialized retained retained retained scfrdr_0 initialized initialized retained retained retained scsmr_1 initialized initialized retained retained retained scbrr_1 initialized initialized retained retained retained scscr_1 initialized initialized retained retained retained sctdsr_1 initialized initialized retained retained retained scfer_1 initialized initialized retained retained retained scssr_1 initialized initialized retained retained retained scfcr_1 initialized initialized retained retained retained scfdr_1 initialized initialized retained retained retained scftdr_1 initialized initialized retained retained retained scfrdr_1 initialized initialized retained retained retained scimr initialized initialized retained retained retained irda iccr1 initialized initialized retained retained retained iic iccr2 initialized initialized retained retained retained icmr initialized initialized retained retained retained icier initialized initialized retained retained retained icsr initialized initialized retained retained retained sar initialized initialized retained retained retained icdrt initialized initialized retained retained retained icdrr initialized initialized retained retained retained iccks initialized initialized retained retained retained simdr_0 initialized initialized retained retained retained siof0 siscr_0 initialized initialized retained retained retained sitdar_0 initialized initialized retained retained retained sirdar_0 initialized initialized retained retained retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1296 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module sicdar_0 initialized initialized retained retained retained siof0 sictr_0 initialized initialized retained retained retained sifctr_0 initialized initialized retained retained retained sistr_0 initialized initialized retained retained retained siier_0 initialized initialized retained retained retained sitdr_0 initialized initialized retained retained retained sirdr_0 initialized initialized retained retained retained sitcr_0 initialized initialized retained retained retained sircr_0 initialized initialized retained retained retained simdr_1 initialized initialized retained retained retained siof1 siscr_1 initialized initialized retained retained retained sitdar_1 initialized initialized retained retained retained sirdar_1 initialized initialized retained retained retained sicdar_1 initialized initialized retained retained retained siof1 sictr_1 initialized initialized retained retained retained sifctr_1 initialized initialized retained retained retained sistr_1 initialized initialized retained retained retained siier_1 initialized initialized retained retained retained sitdr_1 initialized initialized retained retained retained sirdr_1 initialized initialized retained retained retained sitcr_1 initialized initialized retained retained retained sircr_1 initialized initialized retained retained retained actr1 initialized initialized retained retained retained afeif actr2 initialized initialized retained retained retained astr1 initialized initialized retained retained retained astr2 initialized initialized retained retained retained mrcr initialized initialized retained retained retained mpcr initialized initialized retained retained retained dpnq initialized initialized retained retained retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1297 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module rcnt initialized initialized retained retained retained afeif acdr initialized initialized retained retained retained asdr initialized initialized retained retained retained tdfp initialized initialized retained retained retained rdfp initialized initialized retained retained retained utrctl initialized retained retained ? retained usb pmc usbhr initialized initialized retained retained retained usbh usbhc initialized initialized retained retained retained usbhcs initialized initialized retained retained retained usbhis initialized initialized retained retained retained usbhie initialized initialized retained retained retained usbhid initialized initialized retained retained retained usbhhcca initialized initialized retained retained retained usbhpced initialized initializ ed retained retained retained usbhched initialized initialized retained retained retained usbhcced initialized initialized retained retained retained usbhbhed initialized initializ ed retained retained retained usbhbced initialized initializ ed retained retained retained usbhdhed initialized initialized retained retained retained usbhfi initialized initialized retained retained retained usbhfr initialized initialized retained retained retained usbhfn initialized initialized retained retained retained usbhps initialized initialized retained retained retained usbhlst initialized initialized retained retained retained usbhrda initialized initialized retained retained retained usbhrdb initialized initialized retained retained retained usbhrs initialized initialized retained retained retained usbhrps1 initialized initialized retained retained retained usbhrps2 initialized initialized retained retained retained ifr0 initialized initialized re tained retained retained usbf ifr1 initialized initialized retained retained retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1298 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module ifr2 initialized initialized re tained retained retained usbf ifr3 initialized initialized retained retained retained ier0 initialized initialized retained retained retained ier1 initialized initialized retained retained retained ier2 initialized initialized retained retained retained ier3 initialized initialized retained retained retained isr0 initialized initialized retained retained retained isr1 initialized initialized retained retained retained isr2 initialized initialized retained retained retained isr3 initialized initialized retained retained retained epdr0i initialized initialized retained retained retained epdr0o initialized initialized retained retained retained epdr0s initialized initialized retained retained retained epdr1 initialized initialized retained retained retained epdr2 initialized initialized retained retained retained epdr3 initialized initialized retained retained retained epdr4 initialized initialized retained retained retained epdr5 initialized initialized retained retained retained epsz0o initialized initialized retained retained retained epsz1 initialized initialized retained retained retained epsz4 initialized initialized retained retained retained dasts initialized initialized retained retained retained fclr0 initialized initialized retained retained retained fclr1 initialized initialized retained retained retained epstl0 initialized initialized retained retained retained epstl1 initialized initialized retained retained retained trg initialized initialized retained retained retained dma initialized initialized retained retained retained cvr initialized initialized retained retained retained ctlr0 initialized initialized retained retained retained tsrh initialized initialized retained retained retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1299 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module tsrl initialized initialized retained retained retained usbf epir initialized initialized retained retained retained ifr4 initialized initialized retained retained retained ier4 initialized initialized retained retained retained isr4 initialized initialized retained retained retained ctlr1 initialized initialized retained retained retained tmrh initialized initialized retained retained retained tmrl initialized initialized retained retained retained stoh initialized initialized retained retained retained stol initialized initialized retained retained retained ldprnn (nn:00 to ff) initialized initialized retained retained retained lcdc ldickr initialized initialized retained retained retained ldmtr initialized initialized retained retained retained lddfr initialized initialized retained retained retained ldsmr initialized initialized retained retained retained ldsaru initialized initialized retained retained retained ldsarl initialized initialized retained retained retained ldlaor initialized initialized retained retained retained ldpalcr initialized initialized retained retained retained ldhcnr initialized initialized retained retained retained ldhsynr initialized initialized retained retained retained ldvdlnr initialized initialized retained retained retained ldvtlnr initialized initialized retained retained retained ldvsynr initialized initialized retained retained retained ldaclnr initialized initialized retained retained retained ldintr initialized initialized retained retained retained ldpmmr initialized initialized retained retained retained ldpspr initialized initialized retained retained retained ldcntr initialized initialized retained retained retained lduintr initialized initialized retained retained retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1300 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module lduintlnr initialized initialized retained retained retained lcdc ldlirnr initialized initialized retained retained retained addra initialized initialized init ialized initialized retained adc addrb initialized initialized in itialized initialized retained addrc initialized initialized init ialized initialized retained addrd initialized initialized init ialized initialized retained adcsr initialized initialized in itialized initialized retained dadr0 initialized initialized retained retained retained dac dadr1 initialized initialized retained retained retained dacr initialized initialized retained retained retained pcc0isr * 5 * 5 * 5 * 5 * 5 pcc pcc0gcr initialized retained retained retained retained pcc0cscr initialized retained retained retained retained pcc0cscier initialized retained retained retained retained scsmr initialized initialized retained retained retained sim scbrr initialized initialized retained retained retained scscr initialized initialized retained retained retained sctdr initialized initialized retained retained retained scssr initialized initialized retained retained retained scrdr initialized initialized retained retained retained scscmr initialized initialized retained retained retained scsc2r initialized initialized retained retained retained scgrd initialized initialized retained retained retained scwait initialized initialized retained retained retained scsmpl initialized initialized retained retained retained cmdr0 initialized initialized retained retained retained mmc cmdr1 initialized initialized retained retained retained cmdr2 initialized initialized retained retained retained cmdr3 initialized initialized retained retained retained cmdr4 initialized initialized retained retained retained cmdr5 initialized initialized retained retained retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1301 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module cmdstrt initialized initialized retained retained retained mmc opcr initialized initialized retained retained retained cstr initialized initialized retained retained retained intcr0 initialized initialized retained retained retained intcr1 initialized initialized retained retained retained intstr0 initialized initialized retained retained retained intstr1 initialized initialized retained retained retained clkon initialized initialized retained retained retained ctocr initialized initialized retained retained retained vdcnt initialized initialized retained retained retained tbcr initialized initialized retained retained retained moder initialized initialized retained retained retained cmdtyr initialized initialized retained retained retained rsptyr initialized initialized retained retained retained tbncr initialized initialized retained retained retained rspr0 initialized initialized retained retained retained rspr1 initialized initialized retained retained retained rspr2 initialized initialized retained retained retained rspr3 initialized initialized retained retained retained rspr4 initialized initialized retained retained retained rspr5 initialized initialized retained retained retained rspr6 initialized initialized retained retained retained rspr7 initialized initialized retained retained retained rspr8 initialized initialized retained retained retained rspr9 initialized initialized retained retained retained rspr10 initialized initialized retained retained retained rspr11 initialized initialized retained retained retained rspr12 initialized initialized retained retained retained rspr13 initialized initialized retained retained retained rspr14 initialized initialized retained retained retained rspr15 initialized initialized retained retained retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1302 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module rspr16 initialized initialized retained retained retained mmc rsprd initialized initialized retained retained retained dtoutr initialized initialized retained retained retained dr initialized initialized retained retained retained fifoclr initialized initialized retained retained retained dmacr initialized initialized retained retained retained intcr2 initialized initialized retained retained retained intstr2 initialized initialized retained retained retained rdtimsel initialized initialized retained retained retained bdrb initialized initialized retained retained retained ubc bdmrb initialized initialized retained retained retained brcr initialized initialized retained retained retained betr initialized initialized retained retained retained barb initialized initialized retained retained retained bamrb initialized initialized retained retained retained bbrb initialized initialized retained retained retained brsr initialized initialized retained retained retained bara initialized initialized retained retained retained bamra initialized initialized retained retained retained bbra initialized initialized retained retained retained brdr initialized initialized retained retained retained basra initialized initialized retained retained retained basrb initialized initialized retained retained retained pacr initialized retained retained ? retained pfc pbcr initialized retained retained ? retained pccr initialized retained retained ? retained pdcr initialized retained retained ? retained pecr initialized retained retained ? retained pfcr initialized retained retained ? retained pgcr initialized retained retained ? retained phcr initialized retained retained ? retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1303 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module pjcr initialized retained retained ? retained pfc pkcr initialized retained retained ? retained plcr initialized retained retained ? retained pmcr initialized retained retained ? retained ppcr initialized retained retained ? retained prcr initialized retained retained ? retained pscr initialized retained retained ? retained ptcr initialized retained retained ? retained pucr initialized retained retained ? retained pvcr initialized retained retained ? retained psela initialized retained retained ? retained pselb initialized retained retained ? retained pselc initialized retained retained ? retained pseld initialized retained retained ? retained padr initialized retained retained ? retained i/o port pbdr initialized retained retained ? retained pcdr initialized retained retained ? retained pddr initialized retained retained ? retained pedr initialized retained retained ? retained pfdr initialized retained retained ? retained pgdr initialized retained retained ? retained phdr initialized retained retained ? retained pjdr initialized retained retained ? retained pkdr initialized retained retained ? retained pldr initialized retained retained ? retained pmdr initialized retained retained ? retained ppdr initialized retained retained ? retained prdr initialized retained retained ? retained psdr initialized retained retained ? retained ptdr initialized retained retained ? retained section 37 list of registers rev. 3.00 jan. 18, 2008 page 1304 of 1458 rej09b0033-0300 register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module pudr initialized retained retained ? retained i/o port pvdr initialized retained retained ? retained sdir retained retained retained retained retained h-udi sdidh retained retained retained retained retained sdidl retained retained retained retained retained notes: 1. for the initial value, see the correspon ding section on each module. since the values of registers of which initial values are undefined are not retained, described as initialized. 2. initialized when the multiplication ratio of pll1 is changed. 3. some bits are initialized by a power- on reset. for details, see section 17, realtime clock (rtc). 4. some bits are initialized by a manual re set. for details, see section 17, realtime clock (rtc). 5. changes according to the status of the pc card. 6. not initialized by a power-on reset due to the wdt. section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1305 of 1458 rej09b0033-0300 section 38 electrical characteristics 38.1 absolute maximum ratings table 38.1 shows the absolute maximum ratings. table 38.1 absolute maximum ratings item symbol value unit power supply voltage (i/o) v cc q, v cc q1, v cc q_rtc ? 0.3 to 4.6 v power supply voltage (internal) v cc , v cc _pll1, v cc _pll2, v cc _rtc ? 0.3 to 2.1 v input voltage v in ? 0.3 to v cc q + 0.3 ? 0.3 to v cc q1 + 0.3 ? 0.3 to v cc q_rtc + 0.3 v analog power supply voltage av cc ? 0.3 to 4.6 v usb power supply voltage av cc _usb ? 0.3 to 4.6 v analog input voltage v an ? 0.3 to av cc + 0.3 v operating temperature t opr ? 20 to 75 c storage temperature t stg ? 55 to 125 c caution: permanent damage to the lsi may resu lt if absolute maximum ratings are exceeded. section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1306 of 1458 rej09b0033-0300 38.2 power-on and power-off order ? order of turning on 1.5 v power (v cc , v cc _pll1, v cc _pll2, and v cc _rtc), 1.8 v/3.3 v power (v cc q1), and 3.3v power (v cc q, v cc _rtc, av cc , av cc _usb ? first turn on the 3.3 v power and 3.3 v/1.8 v power, then turn on the 1.5 v power within 1 ms. this interval should be as short as possibl e. the system design must ensure that the states of pins or undefined period of an internal state do not cause erroneous system operation. ? until voltage is applied to all power supplies and a low level is input to the resetp pin, internal circuits remain unsettled, and so pin states are also undefined. the system design must ensure that these undefined states do not cause erroneous system operation. waveforms at power-on are shown in the following figure. vccq, vccq1, vccq_rtc, avcc, avcc_usb (min.) power vcc, vcc_pll1, vcc_pll2, vcc_rtc (min.) voltage vcc/2 level voltage vccq1: 1.8 v/3.3v power t pwu t unc gnd pins states undefined normal operation period turn on power while resetp is low in advance power-on reset state pins states undefined resetp other pins * note: * except power/gnd, clock related, and analog pins vccq, vccq_rtc, avcc, avcc_usb: 3.3 v power vcc, vcc_pll1, vcc_pll2, vcc_rtc: 1.5 v power note: handling of ca pin the ca pin must be ensured to go high before power is turned on. when it is not ensured, through current flows to the i/o buffer, etc. and it may cause the lsi damage even if a clock is not input. section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1307 of 1458 rej09b0033-0300 table 38.2 recommended timing in power-on item symbol maximum value unit time difference between the power-on of (v cc q, v cc q1, v cc q_rtc, av cc , av cc _usb) and (v cc , v cc _pll1, v cc _pll2, v cc _rtc) levels t pwu 1 ms time over which the internal state is undefined t unc 100 ms note: * the table shown above is recommended values , so they represent guidelines rather than strict requirements. the time over which the internal state is undefined means th e time taken to reach vcc (min.). the pin states become defined when v cc q, v cc q1, v cc q_rtc, av cc , and av cc _usb (min.) are reached. the period of power-on reset ( resetp ) is, however, normally accepted as meaning the time taken for oscillation to become stable (when using the on-chip oscillator) after vcc (min.) is reached. ensure that the period over which the internal state is undefined is less than or equal to 100 ms. ? power-off order ? in the reverse order of powering-on, first turn off the 1.5 v power, then turn off the 3.3 v/1.8 v power within 10 ms. this interval should be as short as possible. the system design must ensure that the states of pins or undefined period of an internal state do not cause erroneous system operation. ? pin states are undefined while only the 1.5 v power is off. the system design must ensure that these undefined states do not cause erroneous system operation. vccq1: 1.8 v/3.3 v power t pwd gnd operation stopped normal operation period v cc /2 level voltage vccq, vccq_rtc, avcc, avcc_usb: 3.3 v power vcc, vcc_pll1, vcc_pll2, vcc_rtc: 1.5 v power section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1308 of 1458 rej09b0033-0300 table 38.3 recommended timing in power-off item symbol maximum value unit time difference between the power-off of (v cc q, v cc q1, v cc q_rtc, av cc , av cc _usb) and (v cc , v cc _pll1, v cc _pll2, v cc _rtc) levels t pwd 10 ms note: * the table shown above is recommended values, so they represent guidelines rather than strict requirements. ? power on and off in hardware standby mode ? hardware standby mode can be used while an rtc clock is in operation. ? apply a low level on the ca pin. confirm that the level on the status0 pin and status1 pin have become high and low, respectively. v cc , v cc _pll1, v cc _pll2, v cc q, v cc q1, av cc , av cc _usb can then be turned off. power supplies v cc q_rtc and v cc _rtc must remain on. the ca pin must be ensured to go low. ? v cc q, v cc q1, av cc , av cc _usb, v cc , v cc _pll1, and v cc _pll2 must be turned on while resetp is low. after the power supply is stable, apply a high level to the ca pin. resetp must then be canceled to high. section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1309 of 1458 rej09b0033-0300 38.3 dc characteristics tables 38.4 and 38.5 show the dc characteristics. table 38.4 dc characteristics (1) [common] conditions: t a = ?20 c to +75 c item symbol min. typ. max. unit test conditions power supply voltage v cc q v cc q_rtc 2.7 3.3 3.6 v v cc q1 2.7/1.65 3.3/1.8 3.6/1.95 v v cc v cc _pll1 * 1 v cc _pll2 * 1 v cc _rtc * 1 1.4 1.5 1.6 v analog (a/d, d/a) power supply voltage av cc * 2 3.0 3.3 3.6 v when not in use, connect to v cc q. analog usb power supply voltage av cc _usb 3.0 3.3 3.6 v when not in use, connect to v cc q. during a/d conversion ? 0.8 2 ma during a/d and d/a conversion ? 2.4 6 ma analog (a/d, d/a) power supply current idle al cc ? 0.1 5.0 ma t a = 25 c analog usb power supply current al cc _usb * 2 ? 4 8 ma av cc _usb = 3.3 v section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1310 of 1458 rej09b0033-0300 item symbol min. typ. max. unit test conditions i cc ? 230 300 ma v cc = 1.5v i = 133 mhz normal operation i cc q ? 60 80 ma v cc q, v cc q1 = 3.3 v b = 66 mhz i cc ? 35 50 sleep mode i cc q ? 15 20 ma when sleep mode is entered after a power- on reset: v cc q, v cc q1 = 3.3 v b = 33 mhz i cc ? 80 250 standby mode i cc q ? 10 20 a t a = 25 c, rtc off v cc q, v cc q1 = 3.3 v v cc = 1.5 v current consumption * 3 hardware standby mode (state when only v cc _rtc and v cc q_rtc are on) i ustby ? ? 50 a t a = 25 c v cc q_rtc = 3.3 v v cc _rtc = 1.5 v rtc clock = 32 khz input leakage current all input pins | i in | ? ? 1.0 a v in = 0.5 to v cc q ? 0.5 v v in = 0.5 to v cc q1 ? 0.5 v three-state leakage current input/output pins, all output pins (off state) | i tsi | ? ? 1.0 a v in = 0.5 to v cc q ? 0.5 v v in = 0.5 to v cc q1 ? 0.5 v pull-up resistance i/o port pins p pull 20 50 120 k ? pin capacitance all pins c ? ? 10 pf notes: 1. when the pll and rtc are not used, the v cc _pll1, v cc _pll2, v cc _rtc, v cc q_rtc, v ss _pll1, v ss _pll2, and v ss _rtc should be power supplied. 2. av cc and av cc _usb should satisfy the condition v cc q ? 0.3 v av cc and av cc _usb v cc q + 0.3 v. even when the a/d converter, d/a c onverter, and usb are not used, av cc , av ss , av cc _usb, and av ss _usb should not be open. connect av cc and av cc _usb to av cc q, and av ss and av ss _usb to v ss q. 3. current consumption values are for v ih min = v cc ? 0.5 v, v ih min = v cc q1 ? 0.5 v, and v il max = 0.5 v with all output pins unloaded. section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1311 of 1458 rej09b0033-0300 table 38.4 dc characteristics (2 -a) [except usb transceiver, i 2 c, adc, dac analog related pins] condition: ta = ? 20 to 75 c item symbol min. typ. max. unit test conditions group 1 input pins * v cc q 0.9 ? v cc q + 0.3 v ca, extal_rtc, resetp v cc q_rtc 0.9 ? v cc q_rtc + 0.3 v v cc q1 0.85 ? v cc q1 + 0.3 v v cc q1 = 1.65 to 1.95 v group 2 input pins * 2.2 ? v cc q1 + 0.3 v v cc q1 = 2.7 to 3.6 v ptf5 to ptf6 2.2 ? av cc + 0.3 v ptf1 to ptf4 2.0 ? av cc + 0.3 v input high voltage other input pins v ih 2.2 ? v cc q + 0.3 v group 1 input pins * ? 0.3 ? v cc q 0.1 v ca, extal_rtc, resetp ? 0.3 ? v cc q_rtc 0.1 v ? 0.3 ? v cc q1 0.15 v v cc q1 = 1.65 to 1.95 v group 2 input pins * ? 0.3 ? v cc q1 0.2 v v cc q1 = 2.7 to 3.6 v ptf5 to ptf6 ? 0.3 ? av cc 0.2 v ptf1 to ptf4 ? 0.3 ? av cc 0.2 v input low voltage other input pins v il ? 0.3 ? v cc q 0.2 v output high voltage group 2 output pins * v oh v cc q1 0.85 ? ? v v cc q1 = 1.65 to 1.95 v i oh = ? 0.2 ma 2.4 ? ? v v cc q1 = 3.0 to 3.6 v i oh = ? 0.2 ma 2.2 ? ? v v cc q1 = 2.7 to 3.6 v i oh = ? 2 ma other output pins 2.2 ? ? v i oh = ? 2ma output low voltage group 2 output pins * v ol ? ? v cc q1 0.15 v v cc q1 = 1.65 to 1.95 v i ol = 0.2 ma ? ? 0.5 v v cc q1 = 2.7 to 3.6 v i ol = 1.6 ma other output pins ? ? 0.5 v i ol = 1.6 ma section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1312 of 1458 rej09b0033-0300 note: * group 1: nmi, asemd0 , md0 to md5, trst /ptl7, irq0/ irl0 /ptp0 to irq3/ irl3 /ptp3, usb1d_txse0/irq4/afe_txout/ pcc_drv /ptg5, usb1d_rcv/irq5/afe_fs/ pcc_reg /ptg6, extal, resetm , afe_rdet /iic_sda/pte5, and afe_rxin/iic_scl/pte6 group 2: a0/ptr0, a1 to a18, a19/ptr1 to a25/ptr7, ckio, rd/ wr , cas /pth5, we3 /dqmuu/ iciowr , we2 /dqmul/ iciord , cke/pth4, ras /pth6, we1 /dqmlu/ we , we0 /dqmll, cs2 , cs3 , cs6b / ce1b /ptm0, cs6a / ce2b , cs5b / ce1a /ptm1, cs5a / ce2a , back , cs0 , breq , cs4 , bs , rd , wait / pcc_wait , dreq0 /pint0/ptm6, dack0 /pint1/ptm4, tend0/pint2/ptm2, dreq1 /ptm7, dack1 /ptm5, tend1/pint3/ptm3, d0 to d15, d16/pta0 to d23/pta7 , and d24/ptb0 to d31/ptb7 table 38.4 dc characteristics (2-b) [i 2 c related pins*] conditions: v cc q = ? 2.7 to 3.6 v, v cc = 1.4 to 1.6 v, ta = ? 20 to 75 c item symbol min. typ. max. unit test conditions power supply voltage vccq 2.7 3.3 3.6 v input high voltage vih v cc q 0.7 ? v cc q + 0.3 v input low voltage vil ? 0.3 ? v cc q 0.3 v output low voltage vol ? ? 0.4 v iol = 1.6 ma permissible output low current iol ? ? 10 ma note: * the iic_scl and iic_sda pins (open-drain pins). section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1313 of 1458 rej09b0033-0300 table 38.4 dc characteristics (2-c) [usb transceiver related pins* 1 ] condition: ta = ? 20 to 75 c item symbol min. typ. max. unit test conditions power supply voltage * 2 av cc _usb 3.0 3.3 3.6 v differential input sensitivity v di 0.2 ? ? v ? (dp) ? (dm) ? differential common mode range v cm 0.8 ? 2.5 v single ended receiver threshold voltage v se 0.8 ? 2.0 v output high voltage v oh 2.5 ? av cc _usb v output low voltage v ol ? ? 0.3 v tray state leakage voltage i lo ? 10 ? 10 a 0v < v in < 3.3v notes: 1. d + and d ? pins. 2. av cc _usb should satisfy the condition v cc q av cc _usb and be supplied av cc _usb and av ss _usb. table 38.5 permissible output current values conditions: v cc q = v cc q_rtc = v cc _q1 = 2.7 to 3.6 v, v cc = v cc _pll1 = v cc _pll2 = v cc _rtc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, av cc _usb = 3.0 to 3.6 v, ta = ? 20 to 75 c item symbol min. typ. max. unit permissible output low current (per pin) i ol ? ? 2.0 ma permissible output low current (total) i ol ? ? 120 ma permissible output high current (per pin) ?i oh ? ? 2.0 ma permissible output high current (total) (?i oh ) ? ? 40 ma note: * to ensure chip reliability, do not exceed the output current values given in table 38.5. section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1314 of 1458 rej09b0033-0300 38.4 ac characteristics the input of this lsi is a synchronous input. the setup hold time of each input signal should be kept unless any notice. v cc q1 can be set to 2.7 to 3.6 v or 1.65 to 1.95 v. when v cc q1 is set to 1.65 to 1.95 v, the drivability of the i/o buffer will be its highest specifications. for the change of the drivability of the i/o buffer, see section 34.1.23, usb transceiver control register (utrctl). table 38.6 maximum operating frequencies conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, ta = ? 20 to 75 c item symbol min. typ. max. unit remarks cpu, cache (i ) 24 ? 133.34 external bus (b ) * 24 ? 66.67 operating frequency peripheral module (p ) f 8.34 ? 33.34 mhz 133 mhz version note: * when using the usb host controller, the external bus frequency (b ) should be set to 32 mhz or higher. section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1315 of 1458 rej09b0033-0300 38.4.1 clock timing table 38.7 clock timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, ta = ?20 to 75c, maximum external bus operating frequency: 66.67 mhz item symbol min. max. unit figure extal clock input frequency f ex 10 66.67 mhz extal clock input cycle time t excyc 15 100 ns extal clock input low pulse width t exl 7 ? ns extal clock input high pulse width t exh 7 ? ns extal clock input rise time t exr ? 4 ns extal clock input fall time t exf ? 4 ns 38.1 ckio clock output frequency f op 20 66.67 mhz ckio clock output cycle time t cyc 15 50 ns ckio clock output low pulse width t ckol 3 ? ns ckio clock output high pulse width t ckoh 3 ? ns ckio clock output rise time t ckor ? 3 ns ckio clock output fall time t ckof ? 3 ns 38.2 ckio clock input frequency f cki 20 66.67 mhz ckio clock input cycle time t ckicyc 15 50 ns ckio clock input low pulse width t ckil 3 ? ns ckio clock input high pulse width t ckih 3 ? ns ckio clock input rise time t ckir ? 3 ns ckio clock input fall time t ckif ? 3 ns 38.3 resetp setup time t resps 20 ? ns 38.4 resetp assert time t respw 20 ? t cyc 38.4, 38.5 resetm assert time t resmw 20 ? t cyc 38.5 power-on oscillation settling time t soc1 10 ? ms 38.4 oscillation settling time on return from standby 1 t soc2 10 ? ms 38.5 oscillation settling time on return from standby 2 t soc3 10 ? ms 38.6 pll synchronization settling time t pll 100 ? s 38.7 section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1316 of 1458 rej09b0033-0300 t exh t exf t exr t exl t excyc v ih v ih v ih 1/2 v ccq 1/2 v ccq v il v il extal * (input) note: * when clock is input from extal pin figure 38.1 extal clock input timing t cyc t ckol t ckoh v oh 1/2v ccq1 ckio (output) 1/2v ccq1 t ckor t ckof v oh v ol v ol v oh figure 38.2 ckio clock output timing t ckicyc t ckil t ckih v ih 1/2v cc q1 ckio (input) 1/2v cc q1 t ckir t ckif v ih v il v il v ih figure 38.3 ckio clock input timing section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1317 of 1458 rej09b0033-0300 v cc min t respw t resps t soc1 v cc resetp ckio, internal clock stable oscillation note: oscillation settling time when on-chip oscillator is used figure 38.4 power-on os cillation settling time ckio, internal clock stable oscillation standby t soc2 t respw resetp note: oscillation settling time when on-chip oscillator is used resetm t respw t resmw figure 38.5 oscillation settling time on return from standby (return by reset) ckio, internal clock stable oscillation standby t soc3 nmi, irq5 to irq0 note: oscillation settling time when on-chip oscillator is used figure 38.6 oscillation settling time on return from standby (return by nmi or irq) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1318 of 1458 rej09b0033-0300 input clock setting time reset or nmi interrupt request input clock setting time normal mode normal mode standby mode pll output, ckio output internal clock status 0 pll synchronization time note: pll oscillation setting time when clock is input from extal pin t pll pll synchronization time extal input figure 38.7 pll synchronization settling time by reset, nmi or irq interrupts section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1319 of 1458 rej09b0033-0300 38.4.2 control signal timing table 38.8 control signal timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, ta = ?20 to 75c item symbol min. max. unit figure resetp pulse width t respw 20 * 3 ? tcyc* 2 * 4 resetp setup time * 1 t resps 23 ? ns resetp hold time t resph 2 ? ns resetm pulse width t respw 20 * 3 ? tcyc* 2 * 4 resetm setup time * 1 t resps 23 ? ns resetm hold time t resph 2 ? ns 38.8, 38.9 breq setup time t breqs 1/2t cyc + 7 ? ns breq hold time t breqh 1/2t cyc + 2 ? ns 38.10 nmi setup time * 1 t nmis 8 ? ns nmi hold time t nmih 3 ? ns irq5 to irq0 setup time * 1 t irqs 8 ? ns irq5 to irq0 hold time t irqh 3 ? ns 38.9 back delay time t backd 1/2t cyc 1/2t cyc + 13 ns status0 delay time t std ? 18 ns bus tri-state delay time 1 t boff1 0 30 ns bus tri-state delay time 2 t boff2 0 30 ns 38.10, 38.11 bus buffer-on time 1 t bon1 0 30 ns bus buffer-on time 2 t bon2 0 30 ns 38.10, 38.11 notes: 1. resetp , nmi, and irq5 to irq0 are asynch ronous. changes are detected at the clock rise when the setup time shown is used. if the setup time cannot be used, detection may be delayed until the next clock rises. 2. the upper limits of the external bus clock are 66.67 mhz (133 mhz version). 3. in standby mode, t respw = t soc2 (10 ms). when the clock multiplication ratio is changed, t respw = t pll (100 s). 4. t cyc means the external bus clock cycle (b clock cycle). section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1320 of 1458 rej09b0033-0300 ckio t resps t resps resetp resetm t respw figure 38.8 reset input timing ckio resetp resetm t resph t resps v ih v il nmi t nmih t nmis v ih v il irq5 to irq0 t irqh t irqs v ih v il figure 38.9 interrupt signal input timing section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1321 of 1458 rej09b0033-0300 ckio (hizcnt=1) breq back a25 to a0, d31 to d0 rd , rd/ wr , csn , wen , bs ckio (hizcnt=0) breqh t boff2 t breqs t backd t backd t breqh t breqs t bon1 t boff1 t boff2 t bon2 t bon2 t figure 38.10 bus release timing ckio t boff2 t boff1 t std t bon2 t bon1 normal mode standby mode normal mode status0 a25 to a0, d15 to d0 rd , rd/ wr , csn , wen , bs figure 38.11 pin drive timing at standby section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1322 of 1458 rej09b0033-0300 38.4.3 ac bus timing table 38.9 bus timing conditions: clock mode 0, v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, ta = ?20 to 75c 66.67 mhz item symbol min. max. unit figure address delay time 1 t ad1 1 13 ns 38.12 to 38.42 address delay time 2 t ad2 1/2t cyc 1/2t cyc + 13 ns 38.19 address delay time 3 t ad3 1/2t cyc 1/2t cyc + 13 ns address setup time t as 0 ? ns 38.12 to 38.19 address hold time t ah 0 ? ns 38.12, 38.13 bs delay time t bsd ? 13 ns 38.12 to 38.36, 38.37, 38.38 cs delay time 1 t csd1 1 13 ns 38.12 to 38.36, 38.37 to 38.42 cs delay time 2 t csd2 1/2t cyc 1/2t cyc + 13 ns read/write delay time 1 t rwd1 1 13 ns 38.12 to 38.36, 38.37 to 38.42 read/write delay time 2 t rwd2 1/2t cyc 1/2t cyc + 13 ns read strobe delay time t rsd 1/2t cyc 1/2t cyc + 13 ns 38.12 to 38.19, 38.39, 38.40 read data setup time 1 t rds1 1/2t cyc + 10 ? ns 38.12 to 38.18, 38.37 to 38.42 read data setup time 2 t rds2 7 ? ns 38.20 to 38.23, 38.28 to 38.30, 38.37, 38.38 read data setup time 3 t rds3 1/2t cyc + 10 ? ns 38.19 read data setup time 4 t rds4 1/2t cyc + 10 ? ns read data hold time 1 t rdh1 0 ? ns 38.12 to 38.18, 38.37 to 38.42 read data hold time 2 t rdh2 2 ? ns 38.20 to 38.23, 38.28 to 38.30, 38.37, 38.38 read data hold time 3 t rdh3 0 ? ns 38.19 read data hold time 4 t rdh4 1/2t cyc + 10 ? ns write enable delay time 1 t wed1 1/2t cyc 1/2t cyc + 13 ns 38.12 to 38.17, 38.39, 38.40 write enable delay time 2 t wed2 ? 13 ns 38.18 section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1323 of 1458 rej09b0033-0300 66.67 mhz item symbol min. max. unit figure write data delay time 1 t wdd1 ? 13 ns 38.12 to 38.18, 38.39 to 38.42 write data delay time 2 t wdd2 ? 13 ns 38.24 to 38.27, 38.31 to 38.33, 38.37, 38.38 write data delay time 3 t wdd3 ? 1/2t cyc + 13 ns write data hold time 1 t wdh1 1 ? ns 38.12 to 38.18, 38.37 to 38.42 write data hold time 2 t wdh2 1 ? ns 38.24 to 38.27, 38.31 to 38.33, 38.37, 38.38 write data hold time 3 t wdh3 1/2t cyc ? ns write data hold time 4 t wdh4 0 ? ns 38.12 write data hold time 5 t wdh5 1 ? ns 38.39 to 38.42 wait setup time 1 t wts1 1/2t cyc + 7 ? ns 38.12 to 38.19, 38.40, 38.42 wait hold time 1 t wth1 1/2t cyc + 2 ? ns 38.12 to 38.19, 38.40, 38.42 ras delay time 1 t rasd1 1 13 ns 38.20 to 38.36, 38.37, 38.38 ras delay time 2 t rasd2 1/2t cyc 1/2t cyc + 13 ns cas delay time 1 t casd1 1 13 ns 38.20 to 38.36, 38.37, 38.38 cas delay time 2 t casd2 1/2t cyc 1/2t cyc + 13 ns dqm delay time 1 t dqmd1 1 13 ns 38.20 to 38.36, 38.37, 38.38 dqm delay time 2 t dqmd2 1/2t cyc 1/2t cyc + 13 ns cke delay time 1 t cked1 1 13 ns 38.35, 38.36, 38.37, 38.38 cke delay time 2 t cked2 1/2t cyc 1/2t cyc + 13 ns dack delay time t dacd ? 13 ns 38.12 to 38.36, 38.37 iciord delay time t icrsd ? 1/2t cyc + 13 ns 38.39, 38.40 iciowr delay time t icwsd ? 1/2t cyc + 13 ns 38.41, 38.42 iois16 setup time t io16s 1/2t cyc + 6 ? ns 38.42 iois16 hold time t io16h 1/2t cyc + 4 ? ns 38.42 refout , irqout delay time t refod ? 1/2t cyc + 13 ns 38.43 section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1324 of 1458 rej09b0033-0300 38.4.4 basic timing t1 t2 ckio a25 to a0 cs n rd/ wr rd d31 to d0 we n d31 to d0 bs dackn * wait read write t ad1 t rsd t rsd t ad1 t csd1 t as t ah t rwd1 t rdh1 t rwd1 t rds1 t dacd t dacd t wdd1 t wdh1 t csd1 t bsd t bsd t wed1 t wed1 t wts1 t wth1 t ah t wdh4 note: * waveform when active low is specified for dackn. figure 38.12 basic bus cycle in normal space (no wait) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1325 of 1458 rej09b0033-0300 t1 t ad1 t as t csd1 tw t2 t ad1 t rwd1 t rwd1 t csd1 t rsd t rsd t ah t rdh1 t rds1 t wed1 t wed1 t ah t bsd t bsd t wth1 t wts1 t dacd t dacd t wdh1 t wdd1 ckio a25 to a0 csn rd/ wr rd d15 to d0 read wen bs wait dackn * d15 to d0 write note: * waveform when active low is specified for dackn. figure 38.13 basic bus cycle in normal space (software wait 1) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1326 of 1458 rej09b0033-0300 t1 twx t2 ckio a25 to a0 cs n rd/ wr rd d15 to d0 we n d15 to d0 bs dackn * wait read write t ad1 t rsd t rsd t ad1 t csd1 t as t rwd1 t rdh1 t rwd1 t rds1 t dacd t dacd t wdd1 t wdh1 t csd1 note: * waveform when active low is specified for dackn. t bsd t bsd t wed1 t wed1 t wth1 t wts1 t wts1 t wth1 figure 38.14 basic bus cycle in no rmal space (external wait 1 input) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1327 of 1458 rej09b0033-0300 t1 tw t2 taw t1 tw t2 ckio a25 to a0 cs n rd/ wr rd d15 to d0 we n d15 to d0 bs dackn * wait read write t ad1 t rsd t wed1 t wed1 t wed1 t wed1 t rsd t rsd t rsd t ad1 t ad1 t ad1 t csd1 t rwd1 t rwd1 t rdh1 t rdh1 t rwd1 t rwd1 t csd1 t rds1 t dacd t wth1 t wts1 t wts1 t wth1 t dacd t dacd t dacd t wdd1 t wdh1 t wdd1 t wdh1 t rds1 t csd1 t csd1 t as t as note: * waveform when active low is specified for dackn. t bsd t bsd t bsd t bsd figure 38.15 basic bus cycle in normal space (software wait 1, extern al wait valid (wm bit = 0), no idle cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1328 of 1458 rej09b0033-0300 th t1 twx t2 tf ckio a25 to a0 cs n rd/ wr rd d15 to d0 we n d15 to d0 bs dackn * wait read write t ad1 t rsd t rsd t ad1 t csd1 t rwd1 t rdh1 t rwd1 t rds1 t dacd t wth1 t wts1 t wts1 t wth1 t dacd t wdd1 t wdh1 t csd1 note: * waveform when active low is specified for dackn. t bsd t bsd t wed1 t wed1 figure 38.16 cs extended bus cycle in normal space (sw = 1 cycle, hw = 1 cycl e, external wait 1 input) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1329 of 1458 rej09b0033-0300 th t1 twx t2 tf ckio a25 to a0 cs n we n rd/ wr rd d15 to d0 rd/ wr d15 to d0 bs wait dackn * read write note: * waveform when active low is specified for dackn. t ad1 t ad1 t csd1 t wed1 t wed1 t csd1 t bsd t bsd t wts1 t wth1 t wth1 t wts1 t rsd t rsd t rdh1 t rds1 t dacd t dacd t rwd1 t rwd1 t wdh1 t wdd1 t rwd1 t rwd1 figure 38.17 bus cycle of sram with byte selection (sw = 1 cycle, hw = 1 cycle, external wait 1 input, bas = 0 (ub and lb in wr ite cycle controlled)) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1330 of 1458 rej09b0033-0300 th t1 twx t2 tf ckio a25 to a0 cs n we n rd/ wr rd d15 to d0 rd/ wr d15 to d0 bs wait dackn * read write t ad1 t ad1 t csd1 t csd1 t bsd t bsd t wts1 t wth1 t wth1 t wts1 t rsd t rsd t rdh1 t rds1 t wed2 t wed2 t dacd t dacd t wdh1 t wdd1 t rwd1 t rwd1 t rwd1 t rwd1 note: * waveform when active low is specified for dackn. figure 38.18 bus cycle of sram with byte selection (sw = 1 cycle, hw = 1 cycle, external wait 1 input, bas = 1 (we in writ e cycle controlled)) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1331 of 1458 rej09b0033-0300 38.4.5 burst rom timing t1 tw twx t2b twb ckio a25 to a0 cs n rd/ wr rd d15 to d0 wen bs dackn * wait t ad1 t ad2 t ad2 t ad2 t csd1 t rwd1 t as t2b t csd1 t rsd t rsd t rdh3 t rds3 t rdh3 t rds3 t bsd t bsd t dacd t dacd t wts1 t wth1 t wth1 t wts1 t rwd1 note: * waveform when active low is specified for dackn. figure 38.19 read bus cycle of burst rom (software wait 1, ex ternal wait 1 input, burst wait 1, number of burst 2) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1332 of 1458 rej09b0033-0300 38.4.6 sdram timing tr tc tcw td1 tde ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 row address column address t ad1 t ad1 t ad1 reada command t ad1 t ad1 t ad1 t bsd t bsd t bsd t csd1 t csd1 t rwd1 t rasd1 t rasd1 t rdh2 t rds2 t rwd1 t rasd1 t casd1 t casd1 t casd1 t casd1 t dqmd1 t dqmd1 t dacd t dacd t dacd notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.20 single read bus cycle of sdram (auto precharge mode, cas latency 2, trcd = 1 cycle, trp = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1333 of 1458 rej09b0033-0300 tr trw tc tcw td1 ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 row address column address tde tap t ad1 t ad1 t ad1 reada command t ad1 t ad1 t ad1 t bsd t bsd t bsd t csd1 t csd1 t rwd1 t rasd1 t rasd1 t rdh2 t rds2 t rwd1 t rasd1 t casd1 t casd1 t casd1 t casd1 t dqmd1 t dqmd1 t dacd t dacd t dacd notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.21 single read bus cycle of sdram (auto precharge mode, cas latency 2, trcd = 2 cycles, trp = 2 cycles) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1334 of 1458 rej09b0033-0300 tr tc1 tc2 td1 tc3 td2 tc4 ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 column address4 row address td3 tc5 td4 tc6 td5 tc7 td6 tc8 td7 td8 tde tap t ad1 column address1 t ad1 column address2 t ad1 column address3 t ad1 t ad1 t ad1 reada command t ad1 t ad1 t ad1 t ad1 t bsd t bsd t csd1 t csd1 t rwd1 t rasd1 t rasd1 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rwd1 t rasd1 t casd1 t casd1 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t casd1 t casd1 t dqmd1 t dqmd1 t dacd t dacd t ad1 t ad1 t ad1 t ad1 column address5 column address6 column address7 column address8 reada command notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.22 burst read bus cycle of sdram (single read 8) (auto precharge mode, cas latency 2, trcd = 1 cycle, trp = 2 cycles) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1335 of 1458 rej09b0033-0300 tr tc1 tc2 td1 tc3 td2 tc4 ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 column address4 row address td3 tc5 td4 tc6 td5 tc7 td6 tc8 td7 td8 tde tap t ad1 column address1 t ad1 column address2 t ad1 column address3 t ad1 t ad1 t ad1 reada command t ad1 t ad1 t ad1 t ad1 t bsd t bsd t csd1 t csd1 t rwd1 t rasd1 t rasd1 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rwd1 t rasd1 t casd1 t casd1 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t casd1 t casd1 t dqmd1 t dqmd1 t dacd t dacd t ad1 t ad1 t ad1 t ad1 column address5 column address6 column address7 column address8 reada command notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.23 burst read bus cycle of sdram (single read 8) (auto precharge mode, cas latency 2, trcd = 2 cycles, trp = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1336 of 1458 rej09b0033-0300 tr trwl ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 column address row address tc t ad1 t ad1 t ad1 writa command t ad1 t ad1 t bsd t bsd t csd1 t csd1 t rwd1 t rasd1 t rasd1 t rwd1 t rwd1 t rasd1 t casd1 t casd1 t casd1 t dqmd1 t dqmd1 t wdh2 t wdd2 t dacd t dacd notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.24 single write bus cycle of sdram (auto precharge mode, trwl = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1337 of 1458 rej09b0033-0300 tr trw ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 row address trw trwl tc t ad1 t ad1 t ad1 writa command t ad1 t ad1 t bsd t bsd t csd1 t csd1 t rwd1 t rasd1 t rasd1 t rwd1 t rwd1 t rasd1 t casd1 t casd1 t casd1 t dqmd1 t dqmd1 t wdh2 t wdd2 t dacd t dacd column address notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.25 single write bus cycle of sdram (auto precharge mode, trcd = 3 cycles, trwl = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1338 of 1458 rej09b0033-0300 tr tc1 tc2 tc3 tc4 ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 column address4 row address tc5 tc6 tc7 tc8 trwl t ad1 column address1 t ad1 column address2 t ad1 column address3 t ad1 t ad1 t ad1 writa command writ command t ad1 t ad1 t ad1 t bsd t bsd t csd1 t csd1 t rwd1 t rasd1 t rasd1 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t rwd1 t rasd1 t casd1 t casd1 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t casd1 t dqmd1 t dqmd1 t dacd t dacd t rwd1 column address8 t ad1 column address7 t ad1 column address6 t ad1 column address5 t ad1 notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.26 burst write bus cycle of sdram (single write 8) (auto precharge mode, trcd = 1 cycle, trwl = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1339 of 1458 rej09b0033-0300 tr tc1 tc2 tc3 tc4 ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 column address4 row address tc5 tc6 tc7 tc8 trwl t ad1 column address1 t ad1 column address2 t ad1 column address3 t ad1 t ad1 t ad1 writa command writ command t ad1 t ad1 t ad1 t bsd t bsd t csd1 t csd1 t rwd1 t rasd1 t rasd1 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t rwd1 t rasd1 t casd1 t casd1 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t casd1 t dqmd1 t dqmd1 t dacd t dacd t rwd1 column address8 t ad1 column address7 t ad1 column address6 t ad1 column address5 t ad1 notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.27 burst write bus cycle of sdram (single write 8) (auto precharge mode, trcd = 2 cycles, trwl = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1340 of 1458 rej09b0033-0300 tr tc1 tc2 td1 tc3 td2 tc4 ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 column address4 row address td3 tc5 td4 tc6 td5 tc7 td6 tc8 td7 td8 tde t ad1 column address1 t ad1 column address2 t ad1 column address3 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 read command t ad1 t ad1 t ad1 t bsd t bsd t csd1 t csd1 t rwd1 t rasd1 t rasd1 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rwd1 t rasd1 t casd1 t casd1 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t casd1 t casd1 t dqmd1 t dqmd1 t dacd t dacd column address5 column address6 column address7 column address8 notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.28 burst read bus cycle of sdram (single read 8) (bank active mode: actv + read command, cas latency 2, trcd = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1341 of 1458 rej09b0033-0300 tc1 tc2 td1 tc3 td2 tc4 ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 column address8 td3 tc5 td4 tc6 td5 tc7 td6 tc8 td7 td8 tde t ad1 column address1 t ad1 column address2 t ad1 t ad1 t ad1 t ad1 t ad1 column address3 column address4 column address5 column address6 column address7 t ad1 t ad1 read command t ad1 t ad1 t bsd t bsd t csd1 t csd1 t rwd1 t rasd1 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rwd1 t rasd1 t casd1 t casd1 t casd1 t dqmd1 t dqmd1 t dacd t dacd notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.29 burst read bus cycle of sdram (single read 8) (bank active mode: read command, same row address, cas latency 2, trcd = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1342 of 1458 rej09b0033-0300 ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 tr tc1 tp tpw tc2 td1 tc3 td2 tc4 td3 tc5 td4 tc6 td5 tc7 td6 tc8 td7 td8 tde t ad1 column address1 t ad1 column address2 t ad1 column address3 t ad1 column address4 t ad1 column address5 t ad1 column address6 t ad1 column address7 t ad1 t ad1 t ad1 read command t ad1 t ad1 t ad1 t ad1 t bsd t bsd t csd1 t rwd1 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rwd1 t casd1 t casd1 t casd1 t casd1 t dqmd1 t dqmd1 t dacd t dacd t csd1 t rwd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 t rds2 t rdh2 column address8 row address notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.30 burst read bus cycle of sdram (single read 8) (bank active mode: pre + actv + read command, different row address, cas latency 2, trcd = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1343 of 1458 rej09b0033-0300 tr tc1 tc2 tc3 tc4 ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 column address8 row address tc5 tc6 tc7 tc8 t ad1 column address1 t ad1 column address2 t ad1 column address3 t ad1 column address4 t ad1 column address5 t ad1 column address6 t ad1 column address7 t ad1 t ad1 t ad1 write command t ad1 t ad1 t bsd t bsd t csd1 t csd1 t rwd1 t rasd1 t rasd1 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t rwd1 t rasd1 t casd1 t casd1 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t casd1 t dqmd1 t dqmd1 t dacd t dacd t rwd1 notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.31 burst write bus cycle of sdram (single write 8) (bank active mode: actv + writ command, trcd = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1344 of 1458 rej09b0033-0300 tnop tc1 tc2 tc3 tc4 ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 column address8 tc5 tc6 tc7 tc8 t ad1 column address1 t ad1 column address2 t ad1 column address3 t ad1 column address4 t ad1 column address5 t ad1 column address6 t ad1 column address7 t ad1 t ad1 t ad1 write command t ad1 t ad1 t bsd t bsd t csd1 t csd1 t rwd1 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t wdh2 t wdd2 t rwd1 t rasd1 t casd1 t casd1 t casd1 t dqmd1 t dqmd1 t dacd t dacd t rwd1 notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.32 burst write bus cycle of sdram (single write 8) (bank active mode: actv + writ command, trcd = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1345 of 1458 rej09b0033-0300 tr tc1 tp tpw tc2 ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 row address tc3 tc4 tc5 tc6 tc7 tc8 t ad1 column address1 t ad1 column address2 t ad1 column address3 t ad1 column address4 t ad1 column address5 t ad1 column address6 t ad1 column address7 t ad1 t ad1 t ad1 write command t ad1 t ad1 t ad1 t bsd t bsd t csd1 t rwd1 t wdh2 t wdh2 t wdh2 t wdd2 t wdd2 t wdd2 t wdd2 t wdd2 t wdd2 t wdd2 t wdd2 t rwd1 t casd1 t casd1 t casd1 t dqmd1 t dqmd1 t dacd t dacd t csd1 t rwd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t wdh2 t wdh2 t wdh2 t wdh2 t wdh2 column address8 t rwd1 notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.33 burst write bus cycle of sdram (single write 8) (bank active mode: pre + actv + writ command, trcd = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1346 of 1458 rej09b0033-0300 tp tpw trr trc trc ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke (high) t ad1 trc trc t ad1 t ad1 t ad1 t ad1 t ad1 t csd1 t csd1 t rwd1 t csd1 t csd1 t csd1 t rwd1 t dacd t bsd t casd1 t casd1 t casd1 t casd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t dqmd1 t dqmd1 (high-z) t rwd1 notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.34 auto refresh timing of sdram (trp = 2 cycles) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1347 of 1458 rej09b0033-0300 tp tpw trr trc ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke t ad1 trc trc trc trc t ad1 t ad1 t ad1 t ad1 t ad1 t csd1 t csd1 t rwd1 t csd1 t csd1 t csd1 t rwd1 t dacd t bsd t cked1 t cked1 t cked1 t casd1 t casd1 t casd1 t casd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t dqmd1 t dqmd1 (high-z) t rwd1 notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.35 self refresh timi ng of sdram (trp = 2 cycles) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1348 of 1458 rej09b0033-0300 tp tpw trr trc ckio a23 to a0 a12/a11 * 1 csn rd/ wr ras cas dqmx d15 to d0 bs dackn * 2 cke t ad1 trr trc trc tmw tde t ad1 t ad1 t ad1 t csd1 t csd1 t rwd1 t csd1 t csd1 t csd1 t csd1 t csd1 t csd1 t csd1 t rwd1 t dacd t bsd t cked1 t casd1 t casd1 t casd1 t casd1 t casd1 t casd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t rasd1 t dqmd1 t dqmd1 (high-z) (high) t rwd1 t rwd1 t rwd1 t ad1 t ad1 t ad1 t ad1 notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.36 power- on sequence of sdram (mode write timing, trp = 2 cycles) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1349 of 1458 rej09b0033-0300 tr tc trwl tr tc tcw td1 tde ckio a23 to a0 a12/a11 * 1 cs n rd/ wr ras cas dqmx d15 to d0 bs cke dackn * 2 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t csd1 t ad1 t ad1 t csd1 t ad1 t rasd1 t casd1 t casd1 t casd1 t rasd1 t rasd1 t rasd1 t ad1 t ad1 t ad1 t dqmd1 t cked1 t csd1 t dqmd1 t rwd1 t rwd1 t casd1 t dqmd1 t cked1 t dacd t dacd t dacd t dacd t dacd t rdh2 t bsd t bsd t bsd t bsd t bsd t rwd1 t casd1 t rasd1 t csd1 t dqmd1 t wdd2 t rds2 t wdh2 row address column address column address row address writa command reada command notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.37 write to read bus cy cle in power-down mode of sdram (auto precharge mode, trcd = 1 cycle, trp = 1 cycle, trwl = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1350 of 1458 rej09b0033-0300 tr tc tcw td1 tde tr tc trwl ckio a23 to a0 a12/a11 * 1 cs n rd/ wr ras cas dqmx d15 to d0 bs cke dackn * 2 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t ad1 t csd1 t ad1 t ad1 t ad1 t ad1 t ad1 t csd1 t ad1 t rasd1 t casd1 t casd1 t casd1 t rasd1 t rasd1 t rasd1 t dqmd1 t cked1 t csd1 t dqmd1 t rwd1 t rwd1 t casd1 t dqmd1 t cked1 t dacd t dacd t dacd t dacd t dacd t wdh2 t bsd t bsd t bsd t bsd t bsd t rwd1 t casd1 t rasd1 t csd1 t dqmd1 t rds2 t wdd2 t rdh2 row address row address reada command writa command column address column address notes: 1. address pin that is connected to a10 of sdram 2. waveform when active low is specified for dackn figure 38.38 read to write bus cy cle in power-down mode of sdram (auto precharge mode, trcd = 1 cycle, trp = 1 cycle, trwl = 1 cycle) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1351 of 1458 rej09b0033-0300 38.4.7 pcmcia timing tpcm1 tpcm1w tpcm1w tpcm1w ckio a25 to a0 cexx rd/ wr rd d15 to d0 d15 to d0 we bs t ad1 tpcm2 t ad1 t csd1 t csd1 t rwd1 t rwd1 t rsd t rsd t rds1 t rdh1 t wed1 t wed1 t wdh5 t wdh1 t wdd1 t bsd t bsd read write figure 38.39 pcmcia memory card interface bus timing section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1352 of 1458 rej09b0033-0300 tpcm0w tpcm0 tpcm1 tpcm1w tpcm1w tpcm1w tpcm1w ckio a25 to a0 cexx rd/ wr rd d15 to d0 d15 to d0 we bs wait t ad1 tpcm2 tpcm2w t ad1 t csd1 t csd1 t rwd1 t rwd1 t rsd t rsd t rds1 t rdh1 t wed1 t wed1 t wdh5 t wdh1 t wdd1 t bsd t bsd t wts1 t wts1 t wth1 t wth1 read write figure 38.40 pcmcia memory card interface bus timing (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait 1, hardware wait 1) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1353 of 1458 rej09b0033-0300 tpci1 tpci1w tpci1w tpci1w ckio a25 to a0 cexx rd/ wr iciord d15 to d0 d15 to d0 iciowr bs t ad1 tpci2 t ad1 t csd1 t csd1 t rwd1 t rwd1 t icrsd t icrsd t rds1 t rdh1 t icwsd t icwsd t wdh5 t wdh1 t wdd1 t bsd t bsd read write figure 38.41 pcmcia i/o card interface bus timing section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1354 of 1458 rej09b0033-0300 tpci0w tpci0 tpci1 tpci1w tpci1w tpci1w tpci1w ckio a25 to a0 cexx rd/ wr iciord d15 to d0 d15 to d0 iciowr bs wait iois16 t ad1 tpci2 tpci2w t ad1 t csd1 t csd1 t rwd1 t rwd1 t icrsd t icrsd t rds1 t rdh1 t icwsd t icwsd t wdh5 t wdh1 t wdd1 t bsd t io16h t io16h t bsd t wts1 t wts1 t wth1 t wth1 read write figure 38.42 pcmcia i/o card interface bus timing (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait 1, hardware wait 1) ckio t refod r efout , irqout figure 38.43 refout , irqout delay time section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1355 of 1458 rej09b0033-0300 38.4.8 peripheral mo dule signal timing table 38.10 peripheral module signal timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ?20 to 75c module item symbol min. max. unit figure output data delay time t portd ? 17 input data setup time t ports 15 ? i/o port input data hold time t porth 8 ? ns 38.44 dreqn setup time t dreqs 6 ? dreqn hold time t dreqh 4 ? 38.45 dmac dackn , tendn delay time t dacd ? 13 ns 38.46 t ports ckio i/o port pins 7 to 0 (read) i/o port pins 7 to 0 (write) t porth t portd figure 38.44 i/o port timing t dreqs t dreqh ckio d reqn figure 38.45 dreq input timing (dreq low level is detected) ckio dackn , dackn t dacd t dacd figure 38.46 dack output timing section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1356 of 1458 rej09b0033-0300 38.4.9 16-bit timer pulse unit (tpu) table 38.11 16-bit timer pulse unit conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ?20 to 75c item symbol min. max. unit figure timer output delay time t tod ? 15 ns 38.47 timer clock input setup time t tcks 15 ? ns 38.48 single-edge setting t tckwh , t tckwl 2 ? timer clock pulse width both-edge setting t tckwh , t tckwl 3 ? pcyc * 38.48 note: * peripheral clock (p ) cycle. ckio tpu_to0, tpu_to1, t tod tpu_to2, tpu_to3 figure 38.47 tpu output timing ckio tpu_ti2a, tpu_ti2b, tpu_ti3a, tpu_ti3b t tcks t tckwl t tckwh t tcks figure 38.48 tpu clock input timing section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1357 of 1458 rej09b0033-0300 38.4.10 rtc signal timing table 38.12 rtc signal timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ?20 to 75c module item symbol min. max. unit figure rtc oscillation settling time t rosc 3 ? s 38.49 rtc crystal osillator stable oscillation v cc v ccmin t rosc figure 38.49 oscillation settling time when rtc crystal oscillator is turned on section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1358 of 1458 rej09b0033-0300 38.4.11 scif module signal timing table 38.13 scif module signal timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ?20 to 75c module item symbol min. max. unit figure scif asynchronous 12 ? input clock cycle synchronous t scyc 4 ? 38.50 38.51 input clock rise time t sckr ? 1.5 38.50 input clock fall time t sckf ? 1.5 t pcyc input clock pulse width t sckw 0.4 0.6 t scyc transmit data delay time t txd ? 3 t pcyc * + 50 ns 38.51 receive data setup time (synchronous) t rxs 2 t pcyc * ? receive data hold time (synchronous) t rxh 2 t pcyc * ? rts delay time t rtsd ? 100 cts setup time t ctss 100 ? cts hold time t ctsh 100 ? note: * t pcyc is a cycle time of a peripheral clock (p ). t sckw t sckr t sckf t scyc scifn_sck figure 38.50 sck input clock timing section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1359 of 1458 rej09b0033-0300 t scyc t txd scifn_sck scifn_txd (data transmission) scifn_rxd (data reception) scifn_rts t rxh t rxs t rtsd scifn_cts t ctsh t ctss figure 38.51 scif input/output timing in synchronous mode section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1360 of 1458 rej09b0033-0300 38.4.12 i 2 c bus interface timing table 38.14 i 2 c bus interface timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v, v cc = 1.4 to 1.6 v, ta = ?20 to 75c value item symbol test conditions min. typ. max. unit figure scl input cycle time t scl 12 t pcyc + 600 ? ? ns 38.52 scl input high pulse width t sclh 3 t pcyc + 300 ? ? ns scl input low pulse width t scll 5 t pcyc + 300 ? ? ns scl, sda input fall time t sf ? ? 300 ns scl, sda input spike pulse removal time t sp ? ? 1 t cyc ns sda input bus free time t buf 5 t pcyc ? ? ns start condition input hold time t stah 3 t pcyc ? ? ns retransmission start condition input setup time t stas 3 t pcyc ? ? ns stop condition input setup time t stos 3 t pcyc ? ? ns data input setup time t sdas 1 t pcyc + 20 ? ? ns data input hold time t sdah 0 ? ? ns capacitive load of scl, sda cb 0 ? 400 pf scl, sda output fall time t sf vccq = 3.0 v ? ? 250 ns ? ? 300 ns note: * t pcyc is a cycle time of a peripheral clock (p ). section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1361 of 1458 rej09b0033-0300 iic_scl v ih v il t stah t buf p * s * t sf t sr t scl t sdah t sclh t scll iic_sda sr * t stas t sp t stos t sdas p * * s, p, and sr indicate as below. s: start condition p: stop condition sr: retransmission start condition 0 figure 38.52 i 2 c bus interface input/output timing section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1362 of 1458 rej09b0033-0300 38.4.13 siof module signal timing table 38.15 siof module signal timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ? 20 to 75 c item symbol min. max. unit figure siof_mclk clock input cycle time t mcyc t pcyc * 1 ? ns 38.53 siof_mclk input high level width t mwh 0.4 t mcyc ? ns 38.53 siof_mclk input low level width t mwl 0.4 t mcyc ? ns 38.53 siof_sck clock cycle time t sicyc t pcyc * 1 ? ns 38.54 to 38.58 siof_sck output high level width t swho 0.4 t sicyc ? ns 38.54 to 38.57 siof_sck output low level width t swlo 0.4 t sicyc ? ns 38.54 to 38.57 siof_sync output delay time t fsd ? 20 ns 38.54 to 38.57 siof_sck input high level width t swhi 0.4 t sicyc ? ns 38.58 siof_sck input low level width t swli 0.4 t sicyc ? ns 38.58 siof_sync input setup time t fss 20 ? ns 38.58 siof_sync input hold time t fsh 20 ? ns 38.58 siof_txd output delay time t stdd ? 20 ns 38.54 to 38.58 siof_rxd input setup time t srds 20 ? ns 38.54 to 38.58 siof_rxd input hold time t srdh 20 ? ns 38.54 to 38.58 note: t pcyc is a cycle time of a peripheral clock (p ). t mwh t mwl t mcyc siofn_mclk figure 38.53 siof_mclk input timing section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1363 of 1458 rej09b0033-0300 t sicyc t swlo t swho t fsd t stdd t stdd t srds t srdh t fsd siofn_sck (output) siofn_sync (output) siofn_txd siofn_rxd figure 38.54 siof transmission/reception timing (master mode 1, fall sampling) t sicyc t swho t swlo t fsd t stdd t stdd t srds t srdh t fsd siofn_sck (output) siofn_sync (output) siofn_txd siofn_rxd figure 38.55 siof transmission/reception timing (master mode 1, rise sampling) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1364 of 1458 rej09b0033-0300 t sicyc t swlo t swho t stdd t stdd t stdd t stdd t srds t srdh t fsd t fsd siofn_sck (output) siofn_sync (output) siofn_txd siofn_rxd figure 38.56 siof transmission/reception timing (master mode 2, fall sampling) t sicyc t swho t swlo t stdd t stdd t stdd t stdd t srds t srdh t fsd t fsd siofn_sck (output) siofn_sync (output) siofn_txd siofn_rxd figure 38.57 siof transmission/reception timing (master mode 2, rise sampling) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1365 of 1458 rej09b0033-0300 t sicyc t swli t swhi t fsh t stdd t stdd t srds t srdh t fss siofn_sck (input) siofn_sync (input) siofn_txd siofn_rxd figure 38.58 siof transmission/reception timing (slave mode 1, slave mode 2) 38.4.14 afeif module signal timing table 38.16 afeif module signal timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ? 20 to 75 c item symbol min max unit afe_sclk clock input cycle time t ascyc 8 t pcyc ? ns afe_sclk input high level width t aswh 0.4 t ascyc ? ns afe_sclk input low level width t aswl 0.4 t ascyc ? ns afe_fs input time t afsd 0 50 ns afe_txout output delay time t atdd ? t pcyc + 20 ns afe_rxin input setup time t ards 20 ? ns afe_rxin input hold time t ardh 2 t pcyc + 20 ? ns afe_hc1 output delay time t ahcd ? 3 t pcyc + 20 ns afe_rlyc output delay time t arlyd ? t pcyc + 20 ns note: t pcyc is a cycle time (ns) of a peripheral clock (p ). section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1366 of 1458 rej09b0033-0300 t ards t ardh t ahcd t arlyd t ahcd afe_sclk afe_fs afe_txout afe_rxin afe_hc1 afe_rlyc t ascyc t aswl t aswh t afsd t afsd t atdd figure 38.59 afeif module ac timing 38.4.15 usb module signal timing table 38.17 usb module clock timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc _usb= 3.0 to 3.6 v, ta = ? 20 to 75 c item symbol min. max. unit figure extal_usb clock frequency (48 mhz) t freq 47.9 48.1 mhz clock rise time t r48 ? 6 ns clock fall time t f48 ? 6 ns 38.60 section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1367 of 1458 rej09b0033-0300 t high t low t freq 10% extal_usb (input) t r48 t f48 90% figure 38.60 usb clock timing table 38.18 usb electrical ch aracteristics (full-speed) item symbol min. max. unit figure transition time (rise) * 2 t r 4 20 ns cl = 50 pf transition time (fall) * 2 t f 4 20 ns cl = 50 pf rise/fall time matching t rfm 85 111 % (tr/tf) output signal crossover power supply voltage v crs 1.3 2.0 v ? notes: measured with edge control c edge = 47 pf and connection of direct resister rs = 27 ? . 1. value when cl = 50 pf unless specified. 2. value within 10 % to 90 % of the signal power supply voltage. table 38.19 usb electrical ch aracteristics (low-speed) item symbol min. max. unit figure 75 ? ns cl = 200 pf transition time (rise) * t r ? 300 ns cl = 600 pf 75 ? ns cl = 200 pf transition time (fall) * t f ? 300 ns cl = 600 pf rise/fall time matching t rfm 80 125 % (tr/tf) output signal crossover power supply voltage v crs 1.3 2.0 v ? notes: measured with edge control c edge = 47 pf and connection of direct resister rs = 27 ? . * value within 10 % to 90 % of the signal power supply voltage. section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1368 of 1458 rej09b0033-0300 38.4.16 lcdc module signal timing table 38.20 lcdc module signal timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ? 20 to 75 c item symbol min. max. unit figure lcd_clk input clock frequency t freq ? 66 mhz lcd_clk input clock rise time t r ? 3 ns lcd_clk input clock fall time t f ? 3 ns lcd_clk input clock duty t duty 90 110 % clock (lcd_cl2) cycle time t cc 25 ? ns clock (lcd_cl2) high level pulse width t chw 7 ? ns clock (lcd_cl2) low level pulse width t clw 7 ? ns clock (lcd_cl2) transition time (rise/fall) t ct ? 3 ns data (lcd_data) delay time t dddo ? 3.5 3 ns display enable (lcd_m_disp) delay time t iddo ? 3.5 3 ns horizontal synchronous signal (lcd_cl1) delay time t hddo ? 3.5 3 ns vertical synchronous signal (lcd_flm) delay time t vddo ? 3.5 3 ns 38.61 section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1369 of 1458 rej09b0033-0300 t dd t dt t chw t clw t ct t ct t cc 0.8vcc 0.2vcc t dt lcd_data0 to lcd_data15 lcd_cl2 lcd_m_disp lcd_cl1 lcd_flm t id t it 0.8vcc 0.2vcc t it t hd t ht 0.8vcc 0.2vcc t ht t vt t vd 0.8vcc 0.2vcc 0.8vcc t vt 0.2vcc figure 38.61 lcdc module signal timing 38.4.17 sim module signal timing table 38.21 sim module signal timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ? 20 to 75 c item symbol min. max. unit figure sim_clk clock cycle t smcyc 2 x tpcyc 16 x tpcyc ns sim_clk clock high level width t smcwh 0.4 t smcyc ? ns sim_clk clock low level width t smcwl 0.4 t smcyc ? ns sim_rst reset output delay t smrd 0 20 ns 38.62 note: t pcyc is a cycle time of a peripheral clock (p ). section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1370 of 1458 rej09b0033-0300 t smcwh t smcwl t smrd t smrd t smcyc sim_clk sim_rst figure 38.62 sim module signal timing 38.4.18 mmcif module signal timing table 38.22 mmcif module signal timing conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ? 20 to 75 c item symbol min. max. unit figure mmc_clk clock cycle t mmcyc 60 ? ns mmc_clk clock high level width t mmwh 0.4 t mmcyc ? ns mmc_clk clock low level width t mmwl 0.4 t mmcyc ? ns mmc_cmd output data delay t mmcd ? 10 ns mmc_cmd input data hold t mmrcs 10 ? ns mmc_cmd input data setup t mmrch 10 ? ns mmc_dat output data delay t mmtdd ? 10 ns mmc_dat input data setup t mmrds 10 ? ns mmc_dat input data hold t mmrdh 10 ? ns 38.63, 38.64 section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1371 of 1458 rej09b0033-0300 t mmcyc t mmwh t mmwl t mmtdd t mmtdd t mmcd t mmcd mmc_clk mmc_dat (output) mmc_cmd (output) figure 38.63 mmcif transmit timing t mmrds t mmrdh t mmrch t mmrcs mmc_clk mmc_cmd (input) mmc_dat (input) figure 38.64 mmcif receive timing (rise sampling) section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1372 of 1458 rej09b0033-0300 38.4.19 h-udi related pin timing table 38.23 h-udi related pin timing conditions: v cc q = vccq_rtc = 2.7 to 3.6 v, vccq1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = v cc _pll1 = v cc _pll2 = vcc_rtc = 1.4 to 1.6 v, avcc = avcc_usb = 3.0 to 3.6 v, t a = ? 20 to 75 c item symbol min. max. unit figure tck cycle time t tckcyc 50 ? ns tck high level pulse width t tckh 12 ? ns tck low level pulse width t tckl 12 ? ns tck rise/fall time t tckf ? 4 ns 38.65 trst setup time t trsts 12 ? ns trst hold time t trsth 50 ? t cyc 38.66 tdi setup time t tdis 10 ? ns tdi hold time t tdih 10 ? ns tms setup time t tmss 10 ? ns tms hold time t tmsh 10 ? ns tdo delay time t tdod ? 16 ns 38.67 asemd0 setup time t asemd0s 12 ? ns asemd0 hold time t asemd0h 12 ? ns 38.68 t tckh t tckf t tckf t tckl t tckcyc v ih v ih v ih 1/2 v cc q 1/2 v cc q v il v il figure 38.65 tck input timing section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1373 of 1458 rej09b0033-0300 t trsts t trsth trst resetp figure 38.66 trst input timing (reset hold) t tmss t tmsh t tdod t tckcyc t tdih t tdis tck tdi tms tdo figure 38.67 h-udi data transfer timing t asemd0h t asemd0s resetp asemd0 figure 38.68 asemd0 input timing section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1374 of 1458 rej09b0033-0300 38.5 a/d converter characteristics table 38.24 lists the a/d converter characteristics. table 38.24 a/d converter characteristics conditions: v cc q = 2.7 to 3.6 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ? 20 to 75 c item min. typ. max. unit resolution 10 10 10 bits conversion time 15 ? ? s analog input capacitance ? ? 20 pf permissible signal source (single source) impedance ? ? 5 k ? nonlinearity error ? ? 3.0 lsb offset error ? ? 2.0 lsb full scale error ? ? 2.0 lsb quantization error ? ? 0.5 lsb absolute accuracy ? ? 4.0 lsb 38.6 d/a converter characteristics table 38.25 lists d/a converter characteristics. table 38.25 d/a converter characteristics conditions: v cc q = 2.7 to 3.6 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ? 20 to 75 c item min. typ. max. unit test conditions resolution 8 8 8 bits conversion time ? ? 10.0 s 20 pf capacitive load absolute accuracy ? 2.5 4.0 lsb 2 m ? resistance load section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1375 of 1458 rej09b0033-0300 38.7 ac characteristic test conditions ? i/o signal reference level: v cc q 2 , v cc q1 2 (v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v) ? input pulse level: vccq to vssq, vccq1 to vssq1 ? input rise and fall times: 1 ns i ol i oh c l v ref this lsi output pin reference voltage of output load switch notes: 1. cl is the total value that includes the capacitance of measurement instruments, and is set as follows for each pin: 30 pf: ckio, cs0 , cs2 to cs6b 50 pf: all other pins 2. i ol = 0.2 ma, i oh = -0.2 ma figure 38.69 output load circuit section 38 electrical characteristics rev. 3.00 jan. 18, 2008 page 1376 of 1458 rej09b0033-0300 appendix rev. 3.00 jan. 18, 2008 page 1377 of 1458 rej09b0033-0300 appendix a. pin states table a.1 pin states category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins a1 a2 vssq ? ? ? ? ? ? a2 d5 vccq ? ? ? ? ? ? a3 d6 status1/pth3 h h/p l/k l/z l/p o/io open a4 d7 lcd_data13/ pint13/ptd5 v o/i/p o/i/p z/z/z o/i/p o/i/io open a5 e6 vssq ? ? ? ? ? ? a6 d8 vccq ? ? ? ? ? ? a7 e8 lcd_data5/ ptc5 v o/p o/k z/z o/p o/io open a8 e9 lcd_data1/ ptc1 v o/p o/k z/z o/p o/io open a9 d10 lcd_cl2/pte2 v o/p o/k z/z o/p o/io open a10 a11 vssq ? ? ? ? ? ? a11 e12 vccq ? ? ? ? ? ? a12 e13 lcd_clk i i i z i i pull-up a13 d12 vssq ? ? ? ? ? ? a14 e15 vccq ? ? ? ? ? ? a15 d13 usb1_pwr_en/ usbf_uplup/ pth0 z o/o/p o/o/k z/z/z o/o/p o/o/io pull-up a16 a15 avss ? ? ? ? ? ? a17 a16 an0/ptf1 z z/i z/z z/z i/i i/i pull-up a18 b18 avcc_usb ? ? ? ? ? ? a19 d17 avss_usb ? ? ? ? ? ? a20 b21 vssq ? ? ? ? ? ? appendix rev. 3.00 jan. 18, 2008 page 1378 of 1458 rej09b0033-0300 category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins b1 e4 vcc_pll2 ? ? ? ? ? ? b2 b1 md2 i i i z i i must be used b3 b2 xtal o o o o o o open b4 a5 resetm i i i i i i pull-up b5 a4 md4 i i z z i i must be used b6 c1 lcd_data15/ pint15/ptd7 v o/i/p o/i/p z/z/z o/i/p o/i/io open b7 b3 lcd_data11/ ptd3 v o/p o/k z/z o/p o/io open b8 e7 lcd_data7/ ptc7 v o/p o/k z/z o/p o/io open b9 d9 lcd_data3/ ptc3 v o/p o/k z/z o/p o/io open b10 e10 lcd_flm/pte0 v o/p o/k z/z o/p o/io open b11 d11 lcd_m_disp/ pte4 v o/p o/k z/z o/p o/io open b12 e14 siof0_mclk/ pts3 v i/p z/k z/z i/p i/io open b13 e16 usb2_pwr_en/ pth1 z o/p o/k z/z o/p o/io pull-up b14 b16 da1/ptf6 z z/i z/z z/z o/i o/i open b15 b17 an2/ptf3 z z/i z/z z/z i/i i/i pull-up b16 a17 usb2_m z * 2 l z z i io pull-down b17 a18 usb1_p z * 1 z * 1 z z i io open b18 a21 usb1_m z * 1 z * 1 z z i io open b19 a20 avcc_usb ? ? ? ? ? ? b20 e20 vccq ? ? ? ? ? ? c1 d2 vcc_pll1 ? ? ? ? ? ? c2 a1 md1 i i i z i i must be used appendix rev. 3.00 jan. 18, 2008 page 1379 of 1458 rej09b0033-0300 category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins c3 b5 md5 i i i z i i must be used c4 a3 extal i i i i i i pull-up c5 b4 md3 i i z z i i must be used c6 b7 lcd_data12/ pint12/ptd4 v o/i/p o/i/p z/z/z o/i/p o/i/io open c7 b8 lcd_data9/ ptd1 v o/p o/k z/z o/p o/io open c8 b9 lcd_data6/ ptc6 v o/p o/k z/z o/p o/io open c9 b10 lcd_data2/ ptc2 v o/p o/k z/z o/p o/io open c10 b11 lcd_don/pte1 v o/p o/k z/z o/p o/io open c11 a12 siof0_sync/ pts4 v o/p z/k z/z io/p io/io open c12 a13 siof0_txd/pts2 v o/p z/k z/z o/p o/io open c13 a14 siof0_sck/ pts0 v o/p z/k z/z io/p io/io open c14 e17 adtrg /ptf0 v i/p z/k z/z i/p i/i open c15 d18 an3/ptf4 z z/i z/z z/z i/i i/i pull-up c16 d16 usb2_p z * 2 l z z i io pull-down c17 b19 avcc ? ? ? ? ? ? c18 e18 usb1d_txdpls/ afe_sclk/ iois16 / pcc_iois16 /ptg4 z o/i/i/i/p o/z/z/z/ k z/z/z/z/z o/i/i/i/p o/i/i/i/io pull-up c19 b20 usb1_ovr_current / usbf_vbus i i/i i/i i/i i/i i/i pull-down c20 e21 extal_usb i i i i i i pull-up d1 f1 vssq1 ? ? ? ? ? ? d2 d1 md0 i i i z i i must be used appendix rev. 3.00 jan. 18, 2008 page 1380 of 1458 rej09b0033-0300 category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins d3 c2 d31/ptb7 z z/p z/k z/z z/p io/io pull-up d4 b6 status0/pth2 h h/p h/k h/z l/p o/io open d5 a6 lcd_data14/ pint14/ptd6 v o/i/p o/i/p z/z/z o/i/p o/i/io open d6 a7 lcd_data10/ ptd2 v o/p o/k z/z o/p o/io open d7 a8 lcd_data8/ ptd0 v o/p o/k z/z o/p o/io open d8 a9 lcd_data4/ ptc4 v o/p o/k z/z o/p o/io open d9 a10 lcd_data0/ ptc0 v o/p o/k z/z o/p o/io open d10 e11 lcd_cl1/pte3 v o/p o/k z/z o/p o/io open d11 b12 vss ? ? ? ? ? ? d12 b13 vcc ? ? ? ? ? ? d13 b14 siof0_rxd/pts1 v i/p z/k z/z i/p i/io open d14 b15 usb2_ovr_current i i i i i i pull-up d15 d14 da0/ptf5 z z/i z/z z/z o/i o/i open d16 d15 an1/ptf2 z z/i z/z z/z i/i i/i pull-up d17 a19 usb1d_dmns/ pint11/ afe_rlycnt/ pcc_bvd2/ptg3 z i/i/o/i/p i/i/o/z/p z/z/z/z/z i/i/o/i/p i/i/o/i/io pull-up d18 c21 usb1d_suspend/ refout / irqout / ptp4 z o/o/o/ p o/z/z/k z/z/z/z o/o/o/p o/o/o/ io pull-up d19 f18 xtal_usb o o o o o o open d20 f21 usb1d_txenl/ pcc_cd1 / pint8/ptg0 z o/i/i/p o/z/i/p z/z/z/z o/i/i/p o/i/i/io pull-up e1 g1 vccq1 ? ? ? ? ? ? e2 e1 vss_pll2 ? ? ? ? ? ? e3 f4 vss_pll1 ? ? ? ? ? ? appendix rev. 3.00 jan. 18, 2008 page 1381 of 1458 rej09b0033-0300 category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins e4 g4 d30/ptb6 z z/p z/k z/z z/p io/io pull-up e17 g18 usb1d_speed/ pcc_cd2 / pint9/ptg1 z o/i/i/p o/z/i/p z/z/z/z o/i/i/p o/i/i/io pull-up e18 d20 usb1d_rcv/ afe_fs/ pcc_reg / irq5/ptg6 z i/i/o/i/p i/z/o/i/k z/z/z/z/z i/i/o/i/p i/i/o/i/io pull-up e19 d21 usb1d_txse0/ afe_txout/ pcc_drv /irq4/ ptg5 z o/o/o/ i/p o/z/o/i/k z/z/z/z/z o/o/o/i/ p o/o/o/i/ io pull-up e20 g21 vssq ? ? ? ? ? ? f1 g2 d24/ptb0 z z/p z/k z/z z/p io/io pull-up f2 e2 d29/ptb5 z z/p z/k z/z z/p io/io pull-up f3 d4 d28/ptb4 z z/p z/k z/z z/p io/io pull-up f4 h4 d27/ptb3 z z/p z/k z/z z/p io/io pull-up f17 f17 mmc_vddon/ scif1_cts / lcd_vepwc/ tpu_to3/ptv4 o o/i/o/ o/p z/z/o/o/ k z/z/z/z/z o/i/o/o/ p o/i/o/o/i o open f18 c20 afe_rdet / iic_sda/pte5 i i/i/i i/i/i i/i/i i/io/i i/io/i pull-up f19 f20 usb1d_dpls/ pint10/afe_hc1/ pcc_bvd1/ptg2 z i/i/o/i/p i/i/z/z/p z/z/z/z/z i/i/o/i/p i/i/o/i/io pull-up f20 h20 vccq ? ? ? ? ? ? g1 h2 vssq1 ? ? ? ? ? ? g2 f2 d26/ptb2 z z/p z/k z/z z/p io/io pull-up g3 e5 d25/ptb1 z z/p z/k z/z z/p io/io pull-up g4 j4 vcc ? ? ? ? ? ? g17 g17 vss ? ? ? ? ? ? appendix rev. 3.00 jan. 18, 2008 page 1382 of 1458 rej09b0033-0300 category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins g18 h18 mmc_odmod / scif1_rts / lcd_vcpwc/ tpu_to2/ptv3 o o/o/o/ o/p z/z/o/o/ k z/z/z/z/z o/o/o/ o/p o/o/o/ o/io open g19 g20 afe_rxin/ iic_scl/pte6 i i/i/i i/i/i i/i/i i/io/i i/io/i pull-up g20 j20 sim_clk/ scif1_sck/ sd_dat3/ptv0 z o/z/i/p z/z/z/k z/z/z/z o/i/io/p o/io/io/ io pull-up h1 j1 vccq1 ? ? ? ? ? ? h2 h1 d23/pta7 z z/p z/k z/z z/p io/io pull-up h3 f5 d22/pta6 z z/p z/k z/z z/p io/io pull-up h4 g5 vss ? ? ? ? ? ? h17 j18 vcc ? ? ? ? ? ? h18 h17 sim_rst/ scif1_rxd/ sd_wp/ptv1 z o/z/i/p z/z/z/k z/z/z/z o/i/i/p o/i/i/io pull-up h19 h21 sim_d/ scif1_txd/ sd_cd/ptv2 z i/z/i/p z/z/i/k z/z/z/z io/o/i/p io/o/i/ io pull-up h20 k20 mmc_dat/ siof1_txd/ sd_dat0/ tpu_ti3a/ptu2 z i/o/i/i/p z/z/z/z/k z/z/z/z/z io/o/io/ i/p io/o/io/ i/io pull-up j1 k1 vssq1 ? ? ? ? ? ? j2 j2 d20/pta4 z z/p z/k z/z z/p io/io pull-up j3 k4 d21/pta5 z z/p z/k z/z z/p io/io pull-up j4 h5 d19/pta3 z z/p z/k z/z z/p io/io pull-up j17 k17 mmc_cmd/ siof1_rxd/ sd_cmd/ tpu_ti2b/ptu1 z i/i/i/i/ p z/z/z/z/k z/z/z/z/ z io/i/io/ i/p io/i/io/ i/io pull-up appendix rev. 3.00 jan. 18, 2008 page 1383 of 1458 rej09b0033-0300 category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins j18 j17 siof1_mclk/ sd_dat1/ tpu_ti3b/ptu3 z i/i/i/p z/z/z/k z/z/z/z i/io/i/p i/io/i/io pull-up j19 j21 siof1_sync/ sd_dat2/ptu4 z o/i/p z/z/k z/z/z io/io/p io/io/io pull-up j20 l17 scif0_rts / tpu_to0/ptt3 v o/o/p z/z/k z/z/z o/o/p o/o/io open k1 l1 vccq1 ? ? ? ? ? ? k2 k2 d17/pta1 z z/p z/k z/z z/p io/io pull-up k3 j5 d18/pta2 z z/p z/k z/z z/p io/io pull-up k4 l4 d16/pta0 z z/p z/k z/z z/p io/io pull-up k17 l20 scif0_txd/irtx/ ptt2 v z/z/p z/z/k z/z/z o/o/p o/o/io open k18 k18 scif0_cts / tpu_to1/ptt4 v i/o/p z/z/k z/z/z i/o/p i/o/io open k19 k21 mmc_clk/ siof1_sck/ sd_clk/ tpu_ti2a/ptu0 z o/o/o/ i/p o/z/z/z/ k z/z/z/z/ z o/io/o/ i/p o/io/o/ i/io pull-up k20 m17 vssq ? ? ? ? ? ? l1 k5 ckio io zio zio z zio io open l2 m1 we2 /dqmul/ iciord h h/h/h hz/hz/ hz z/z/z z/z/z o/o/o open l3 m4 we3 /dqmuu/ iciowr h h/h/h hz/hz/ hz z/z/z z/z/z o/o/o open l4 l5 rd/ wr h h hz z z o open l17 l21 scif0_rxd/irrx/ ptt1 v z/z/p z/z/k z/z/z i/i/p i/i/io open l18 m20 irq3/ irl3 /ptp3 v i/i/p i/i/k z/z/z i/i/p i/i/io open l19 n17 scif0_sck/ptt0 v z/p z/k z/z i/p io/io open l20 l18 vccq ? ? ? ? ? ? appendix rev. 3.00 jan. 18, 2008 page 1384 of 1458 rej09b0033-0300 category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins m1 l2 cas /pth5 h h/p hz/k z/z hz/p o/io open m2 n1 we0 /dqmll h h/h hz/hz z/z z/z o/o open m3 n5 we1 /dqmlu/ we h h/h/h hz/hz/ hz z/z/z z/z/z o/o/o open m4 m5 cke/pth4 z o/p hz/k z/z oz/p o/io open m17 m21 irq1/ irl1 /ptp1 v i/i/p i/i/k z/z/z i/i/p i/i/io open m18 n20 nmi i i i i i i pull-up m19 m18 irq0/ irl0 /ptp0 v i/i/p i/i/k z/z/z i/i/p i/i/io open m20 p17 irq2/ irl2 /ptp2 v i/i/p i/i/k z/z/z i/i/p i/i/io open n1 m2 ras /pth6 h h/p hz/k z/z hz/p o/io open n2 p1 cs3 h h hz z z o open n3 p5 cs2 h h hz z z o open n4 n4 vcc ? ? ? ? ? ? n17 n21 vss ? ? ? ? ? ? n18 p20 audata2/ptj3 x o/p o/k z/z o/p o/io open n19 n18 audata1/ptj2 x o/p o/k z/z o/p o/io open n20 r17 audata3/ptj4 x o/p o/k z/z o/p o/io open p1 n2 vssq1 ? ? ? ? ? ? p2 w2 a14 o o oz z z o open p3 p2 a17 o o oz z z o open p4 r5 vss ? ? ? ? ? ? p17 p21 vcc ? ? ? ? ? ? p18 r20 audata0/ptj1 x o/p o/k z/z o/p o/io open p19 p18 audck/ptj6 v o/p o/k z/z o/p o/io open p20 t17 vssq ? ? ? ? ? ? r1 p4 vccq1 ? ? ? ? ? ? r2 t2 a11 o o oz z z o open r3 r2 a13 o o oz z z o open r4 r1 a15 o o oz z z o open r17 t20 audsync /ptj0 x o/p o/k z/z o/p o/io open appendix rev. 3.00 jan. 18, 2008 page 1385 of 1458 rej09b0033-0300 category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins r18 r21 asemd0 i i i i i i pull-up r19 r18 trst /ptl7 i i/p z/k z/z i/p i/io pull-down r20 u17 vccq ? ? ? ? ? ? t1 t5 a16 o o oz z z o open t2 v1 a6 o o oz z z o open t3 v2 a5 o o oz z z o open t4 t1 a12 o o oz z z o open t17 u20 tms/ptl6 i i/p z/k z/z i/p i/io pull-up t18 t18 tck/ptl3 i i/p z/k z/z i/p i/io pull-up t19 u21 pcc_reset/ pint7/ptk3 v o/i/p o/i/p z/z/z o/i/p o/i/io open t20 v18 asebrkak /ptj5 v o/p o/k z/z o/p o/io open u1 r4 vssq1 ? ? ? ? ? ? u2 t4 a9 o o oz z z o open u3 w1 a4 o o oz z z o open u4 aa3 a10 o o oz z z o open u5 y5 d11 z z z z z io pull-up u6 y6 d8 z z z z z io pull-up u7 aa8 d4 z z z z z io pull-up u8 aa9 d1 z z z z z io pull-up u9 aa10 vcc ? ? ? ? ? ? u10 v11 vss ? ? ? ? ? ? u11 u11 back o o o z l o open u12 u12 bs h h hz z z o open u13 v13 a19/ptr1 o o/p oz/k z/z z/p o/io open u14 u15 a22/ptr4 o o/p oz/k z/z z/p o/io open u15 u16 a24/ptr6 o o/p oz/k z/z z/p o/io open u16 v15 dack0 /pint1/ ptm4 v o/i/p o/i/p z/z/z o/i/p o/i/io open u17 w21 dreq1 /ptm7 v i/p z/k z/z i/p i/io open appendix rev. 3.00 jan. 18, 2008 page 1386 of 1458 rej09b0033-0300 category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins u18 t21 tdi/ptl4 i i/p z/k z/z i/p i/io pull-up u19 v21 pcc_rdy/pint6/ ptk2 v i/i/p z/i/p z/z/z i/i/p i/i/io open u20 w20 tdo/ptl5 z o/p oz/k z/z o/p o/io open v1 u1 vccq1 ? ? ? ? ? ? v2 y2 a3 o o oz z z o open v3 u4 a7 o o oz z z o open v4 aa6 d12 z z z z z io pull-up v5 y4 d14 z z z z z io pull-up v6 aa7 d9 z z z z z io pull-up v7 y7 d6 z z z z z io pull-up v8 y8 d2 z z z z z io pull-up v9 y9 d0 z z z z z io pull-up v10 y10 cs5b / ce1a /ptm1 h h/h/p hz/hz/k z/z/z z/z/p o/o/io open v11 v12 breq z i i z i i pull-up v12 u13 wait / pcc_wait i i/i i/i z/z z/z i/i pull-up v13 u14 a20/ptr2 o o/p oz/k z/z z/p o/io open v14 v14 a23/ptr5 o o/p oz/k z/z z/p o/io open v15 y19 dreq0 /pint0/ ptm6 v i/i/p z/i/p z/z/z i/i/p i/i/io open v16 y18 extal_rtc i i i i i i pull-up v17 aa19 xtal_rtc o o o o o o open v18 v17 resetp i i i i i i must be used v19 aa21 pcc_vs2 /pint5/ ptk1 v i/i/p z/i/p z/z/z i/i/p i/i/io open v20 v20 vssq ? ? ? ? ? ? w1 u2 a8 o o oz z z o open w2 aa2 a2 o o oz z z o open w3 aa1 a1 o o oz z z o open appendix rev. 3.00 jan. 18, 2008 page 1387 of 1458 rej09b0033-0300 category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins w4 aa4 a0/ptr0 o o/p oz/k z/z z/p o/io open w5 aa5 d15 z z z z z io pull-up w6 v7 d10 z z z z z io pull-up w7 v8 d7 z z z z z io pull-up w8 v9 d3 z z z z z io pull-up w9 v10 cs6b / ce1b /ptm0 h h/h/p hz/hz/k z/z/z z/z/p o/o/io open w10 u9 cs5a / ce2a h h/h hz/hz z/z z/z o/o open w11 aa12 cs4 h h hz z z o open w12 aa13 a18 o o oz z z o open w13 aa14 a21/ptr3 o o/p oz/k z/z z/p o/io open w14 y15 a25/ptr7 o o/p oz/k z/z z/p o/io open w15 y16 tend0/pint2/ ptm2 v o/i/p o/i/p z/z/z o/i/p o/i/io open w16 aa18 vccq_rtc ? ? ? ? ? ? w17 v16 tend1/pint3/ ptm3 v o/i/p o/i/p z/z/z o/i/p o/i/io open w18 y20 vss_rtc ? ? ? ? ? ? w19 y21 pcc_vs1 /pint4/ ptk0 v i/i/p z/i/p z/z/z i/i/p i/i/io open w20 u18 vccq ? ? ? ? ? ? y1 y1 vssq1 ? ? ? ? ? ? y2 v5 vccq1 ? ? ? ? ? ? y3 v6 d13 z z z z z io pull-up y4 y3 vssq1 ? ? ? ? ? ? y5 v4 vccq1 ? ? ? ? ? ? y6 u5 d5 z z z z z io pull-up y7 u6 vssq1 ? ? ? ? ? ? y8 u7 vccq1 ? ? ? ? ? ? y9 u8 cs6a / ce2b h h/h h/z z/z z/z o/o open y10 aa11 vssq1 ? ? ? ? ? ? appendix rev. 3.00 jan. 18, 2008 page 1388 of 1458 rej09b0033-0300 category plbg 0256 ga-a plbg 0256 ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins y11 u10 vccq1 ? ? ? ? ? ? y12 y11 cs0 h h hz z z o open y13 y12 rd h h hz z z o open y14 y13 vssq1 ? ? ? ? ? ? y15 y14 vccq1 ? ? ? ? ? ? y16 aa15 vssq1 ? ? ? ? ? ? y17 aa16 vccq1 ? ? ? ? ? ? y18 aa17 dack1 /ptm5 v o/p o/k z/z o/p o/io open y19 y17 ca i i i i i i pull-up y20 aa20 vcc_rtc ? ? ? ? ? ? notes: * 1 the conditions for setting usb1_p and usb1_m to z (open) are as follows: (1) pull the usb1_ovr_current /usbf_vbus pin down. (2) clear the usb_trans bit in utrctr to 0 (initial value). set the usb_sel bit in utrctr to 1 (initial value). * 2 after negation of resetp , usb2_p and usb2_m go low after tens of extal_usb clock cycles have been input. 1. handlings of unused pins in this table are handling examples with the pin functions set to the initial values of the pin function controller (pfc) and cannot be guaranteed in some cases. 2. controlled by software when an input buffer (pad) is not enabled. 3. normal input pin specification. 4. a schmitt characteristic is provided. 5. a board with which the emulator can be used must be designed according to the emulator specifications. [legend] i: input (input buffer on, output buffer off) i: input (input buffer on, output buffer off, fixed i nput in internal logic) o: output (input buffer off, output buffer on, unid entified level) l: low output (input bu ffer off, output buffer on) h: high output (input bu ffer off, output buffer on) z: high-impeda nce (input buffer off, output buffer off) v: input buffer off, output buffer off, pull-up on m: input buffer on, output buffer off, pull-up on appendix rev. 3.00 jan. 18, 2008 page 1389 of 1458 rej09b0033-0300 k: input buffer off/output buffer off (pull-up on), i nput buffer off/output buffer off (pull-up off), or input buffer off/output buffer on acco rding to the register settings p: input buffer on/output buffer off (pull-up on), i nput buffer on/output buffer off (pull-up off), or input buffer off/output buffer on acco rding to the register settings x: undefined appendix rev. 3.00 jan. 18, 2008 page 1390 of 1458 rej09b0033-0300 b. product lineup (1) sh7720 group power supply voltage model i/o internal operating frequency product code package ssl sdhi hd6417720bp133c 256-pin 17mm x 17mm csp (plbg0256ga-a) o ? hd6417720bp133cv 256-pin 17mm x 17mm csp (plbg0256ga-a) o ? hd6417720bl133c 256-pin 11mm x 11mm csp (plbg0256ka-a) o ? sh7720 hd6417720bl133cv 256-pin 11mm x 11mm csp (plbg0256ka-a) o ? hd6417320bp133c 256-pin 17mm x 17mm csp (plbg0256ga-a) o o hd6417320bp133cv 256-pin 17mm x 17mm csp (plbg0256ga-a) o o hd6417320bl133c 256-pin 11mm x 11mm csp (plbg0256ka-a) o o sh7320 3.3 v 0.3v 1.5 v 0.1v 133.34 mhz hd6417320bl133cv 256-pin 11mm x 11mm csp (plbg0256ka-a) o o [legend] o: provided; ? : not provided appendix rev. 3.00 jan. 18, 2008 page 1391 of 1458 rej09b0033-0300 (2) SH7721 group power supply voltage model i/o internal operating frequency product code package ssl sdhi r8a77210c133bg 256-pin 17mm x 17mm csp (plbg0256ga-a) ? ? r8a77210c133bgv 256-pin 17mm x 17mm csp (plbg0256ga-a) ? ? r8a77210c133ba 256-pin 11mm x 11mm csp (plbg0256ka-a) ? ? r8a77210c133bav 256-pin 11mm x 11mm csp (plbg0256ka-a) ? ? r8a77211c133bg 256-pin 17mm x 17mm csp (plbg0256ga-a) ? o r8a77211c133bgv 256-pin 17mm x 17mm csp (plbg0256ga-a) ? o r8a77211c133ba 256-pin 11mm x 11mm csp (plbg0256ka-a) ? o SH7721 3.3 v 0.3v 1.5 v 0.1v 133.34 mhz r8a77211c133bav 256-pin 11mm x 11mm csp (plbg0256ka-a) ? o [legend] o: provided; ? : not provided appendix rev. 3.00 jan. 18, 2008 page 1392 of 1458 rej09b0033-0300 c. package dimensions e a max nom min dimension in millimeters symbol reference a b x y 1 17.0 0.10 0.80 0.45 0.50 0.55 0.35 0.40 0.45 1.40 17.0 0.08 v w 0.9 0.9 y0.2 1 0.20 0.15 previous code jeita package code renesas code bp-256h/bp-256hv 0.6g mass[typ.] e d z z e d z z e d s s e d p-lfbga256-17x17-0.80 plbg0256ga-a 1 1 a a b s s y s wa s wb v s y 1 234567891011121314151617181920 b c d e f g h j k l m n p r t u v w y a a e e b a s b m 4 d e figure c.1 package dimensions (plbg0256ga-a (bp-256h/hv)) appendix rev. 3.00 jan. 18, 2008 page 1393 of 1458 rej09b0033-0300 aa y w v u t r p n m l k j h g f e d c b 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 y s v b ws a ws ys s b a a 1 1 a a mass[typ.] 0.3g bp-256c/bp-256cv renesas code jeita package code previous code 0.15 0.20 1 0.2 y 0.5 0.5 w v 0.05 11.00 1.40 0.30 0.25 0.20 0.35 0.30 0.25 0.50 0.08 11.00 1 y x b a reference symbol dimension in millimeters min nom max a e e d z z e d s s e d p-lfbga256-11x11-0.50 plbg0256ka-a e e b a s b m 4 e d z z d e figure c.2 package dimensions (plbg0256ka-a (bp-256c/cv)) appendix rev. 3.00 jan. 18, 2008 page 1394 of 1458 rej09b0033-0300 rev. 3.00 jan. 18, 2008 page 1395 of 1458 rej09b0033-0300 main revisions and add itions in this edition item page revision (see manual for details) all sh7720 and sh7320 group hardware manuals are merged into this manual, to which the SH7721 group is newly added. all the pins in the sd host interface (sdhi) are added. introduction abbreviations viii added des data encryption standard rsa rivest shamir adleman ssl secure socket layer sdhi sd host interface 5 deleted item features section 1 overview table 1.1 sh7720/SH7721 features serial i/o with fifo (siof0, siof1) ? internal 64-byte transmit/receive fifo ? supports 8-/16-/16-bit stereo sound input/output ? sampling rate clo ck input selectable from p and external pin ? internal prescaler for p ? spi mode ? provides continuous full - duplex communication with spi slave device in fixed master mode. ? transmit/receive data length of fixed 8 bits ? with interrupt request and dmac request rev. 3.00 jan. 18, 2008 page 1396 of 1458 rej09b0033-0300 item page revision (see manual for details) amended item features pc card controller (pcc) ? complies with the pcmcia rev.2.1/jeida version 4.2 ? supports the ic memory card interface and i/o card interface a/d converter (adc) ? 10 bits 4 lsb, four channels ? conversion time: 15 s ? input range: 0 to av cc (max. 3.6 v) sd host interface (sdhi) note: only for models with the sdhi added ssl accelerator (ssl) note: sh7720 group only ? rsa encryption ? supported operations: addition, subtraction, multiplication, power operation ? des and triple-des encryption/decryption table 1.1 sh7720/SH7721 features 6, 7 table 1.2 product lineup (sh7720 group) table 1.3 product lineup (SH7721 group) 8, 9 replaced and table numbers assigned 1.2 block diagram figure 1.1 block diagram 10 sdhi and its related pins added; bridges and clocks deleted. rev. 3.00 jan. 18, 2008 page 1397 of 1458 rej09b0033-0300 item page revision (see manual for details) 1.3 pin assignments 1.3.1 pin assignments figure 1.2 pin assignments (plbg0256ga-a (bp-256h/hv)) 11 amended k17 scif0_txd/irtx/ptt2 l17 scif0_rxd/irrx/ptt1 figure 1.3 pin assignments (plbg0256ka-a (bp-256c/cv)) 12 amended l20 scif0_txd/irtx/ptt2 l21 scif0_rxd/irrx/ptt1 k1 vssq1 l1 vccq1 u5 d5 amended pin no. (plbg0256 ga-a) pin no. (plbg0256 ka-a) pin name function u16 v15 dack0 / pint1/ ptm4 dma transfer request reception/ port interrupt/ general- purpose port y12 y11 cs0 chip select y13 y12 rd read strobe y14 y13 vssq1 i/o pow er supply (0 v) y18 aa17 dack1 / ptm5 dma transfer request reception/ general- purpose port table 1.4 list of pin assignments 24 rev. 3.00 jan. 18, 2008 page 1398 of 1458 rej09b0033-0300 item page revision (see manual for details) amended classifica- tion symbol name function clock xtal crystal for connection to a crystal resonator. ckio system clock used as a pin to input external clock or output clock. direct memory access controller (dmac) dreq0 , dreq1 dma-transfer request input pins for external requests for dma transfer dack0 , dack1 dma transfer request reception indicates the acceptance of dma transfer requests to external devices. serial i/o with fifo (siof) siof0_syn c, siof1_syn c siof frame sync siof frame synchronization signals siof0_txd, siof1_txd siof transmit data siof transmit data pin siof0_rxd, siof1_rxd siof receive data siof receive data pin a/d converter (adc) an3 to an0 analog input pin avcc power supply pin for the a/d or d/a converter. when the a/d or d/a converter is not in use, connect this pin to input/output power supply (vccq). 1.3.2 pin functions table 1.5 sh7720/SH7721 pin functions 26, 29, 32 avss ground pin for the a/d or d/a converter. connect this pin to input/output power supply (vssq). 1.3.2 pin functions 35 notes added ?. 6. sdhi associated pins support only for the models including the sdhi. section 2 cpu 2.1 processing states and processing modes 2.1.1 processing states (1) reset state 37 deleted in manual reset, the register contents of a part of the lsi on-chip modules, such as the bus state controller (bsc), are retained. rev. 3.00 jan. 18, 2008 page 1399 of 1458 rej09b0033-0300 item page revision (see manual for details) section 8 interrupt controller (intc) figure 8.1 block diagram of intc 244 changed input/output control priority identifier com- parator interrupt request sr cpu bus interface internal bus intc i3 i2 i1 i0 (interrupt request) icr irr0 pinter 6 4 16 irq5 to irq0 nmi pint5 to pint0 irl3 to irl0 irlqout ipr [legend] interrupt control register interrupt priority register interrupt request register pint interrupt enable register refresh request in bus state controller icr: ipr: irr: pinter: ref: dmac scif siof tmu tpu wdt adc usbf usbh rtc sim lcdc pcc mmc i 2 c cmt afeif ssl sdhi ref amended name abbreviation i/o description 8.2 input/output pins table 8.1 pin configuration 245 bus request signal pin irqout out- put bus request signal for an interrupt section 8 interrupt controller (intc) 8.3 register descriptions 246 deleted ? interrupt request register 10 (irr10) rev. 3.00 jan. 18, 2008 page 1400 of 1458 rej09b0033-0300 item page revision (see manual for details) 248 amended register bits 15 to 12 bits 7 to 4 bits 3 to 0 iprd reserved * irq5 irq4 iprg scif0 reserved * reserved * iprj reserved * sdhi afeif 8.3.1 interrupt priority registers a to j (ipra to iprj) table 8.2 interrupt sources and ipra to iprj note: * reserved. always read as 0. the write value should always be 0. the ssl and sdhi -related bits are effective only for the models that include them. reserved bits apply if they are not included. changed irr0 is an 8-bit register that indicates interrupt requests from the tmu and irq0 to irq5. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 8.3.4 interrupt request register 0 (irr0) 252 8.3.5 interrupt request register 1 (irr1) 253 deleted irr1 is an 8-bit register that indicates whether interrupt requests from the dmac and lcdc are generated. 8.3.6 interrupt request register 2 (irr2) 254 changed irr2 is an 8-bit register that indicates whether interrupt requests from the ssl and lcdc are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. note: on the models not having the ssl, the ssl- related bits are reserved. the write value should always be 0. added bit bit name description 4 sslir ssli interrupt request ? note: on the models not having the ssl, this bit is reserved and always read as 0. the write value should always be 0. rev. 3.00 jan. 18, 2008 page 1401 of 1458 rej09b0033-0300 item page revision (see manual for details) changed irr8 is an 8-bit register that indicates whether interrupt requests from the sdhi, mmc, and afeif are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. note: on the models not having the sdhi, the sdhi- related bits are reserved. the write value should always be 0. changed and a note added. bit bit name description 0 sdir sdi interrupt request indicates whether the sdi (sdhi) interrupt request is generated. 0: sdi interrupt request is not generated 1: sdi interrupt request is generated note: on the models not having the sdhi, this bit is reserved and always read as 0. the write value should always be 0. 8.3.12 interrupt request register 8 (irr8) 261 8.3.13 interrupt request register 9 (irr9) 262 amended irr9 is an 8-bit register that indicates whether interrupt requests from the pcc, usbh, usbf, and cmt are generated. this register is initialized to h'00 by a power-on reset or manual reset, but is not initialized in standby mode. 8.4.3 irl interrupts 267 deleted irl interrupts are included with noise canceller function and detected when the sampled levels of each peripheral module clock keep same value for 2 cycles. this prevents sampling error level in irl pin changing. in standby mode, noise canceller is handled by the rtc clock because the perip heral module clocks are halted. therefore, when rtc is not used, recovering to standby by irl interrupts cannot be executed in standby mode. rev. 3.00 jan. 18, 2008 page 1402 of 1458 rej09b0033-0300 item page revision (see manual for details) 8.4.4 pint interrupts 268 added while an rtc clock is supplied, recovery from a standby state on a pint inte rrupt is possible if the interrupt level is higher than that set in the i3 to i0 bits of the sr register. ammended interrupt source interru pt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority usb h usbhi h'a60 * 3 0 to 15 (0) iprj (11 to 8) ? dma c (2) dei4 h'b80 * 3 0 to 15 (0) iprf (11 to 8) high dei5 h'ba0 * 3 low tmu tmu_suni h'6c0 0 to 15 (0) iprd (11 to 8) ? 8.4.6 interrupt exception handling and priority table 8.3 interrupt exception handling sources and priority (irq mode) 270 ? ? ? ? ? ? rev. 3.00 jan. 18, 2008 page 1403 of 1458 rej09b0033-0300 item page revision (see manual for details) changed interrupt source interrupt code interrupt priority (initial value) ipr (bit numbers) priority within ipr setting unit default priority nmi h-udi irl irl3 to rl0 =b'0000 h'200 * 3 15 ? ? irl3 to irl0 =b'0001 h'220 * 3 14 ? ? irl3 to irl0 =b'0010 h'240 * 3 13 ? ? irl3 to irl0 =b'0011 h'260 * 3 12 ? ? irl3 to i rl0 =b'0100 h'280 * 3 11 ? ? irl3 to irl0 =b'0101 h'2a0 * 3 10 ? ? irl3 to irl0 =b'0110 h'2c0 * 3 9 ? ? irl3 to irl0 =b'0111 h'2e0 * 3 8 ? ? irl3 to irl0 =b'1000 h'300 * 3 7 ? ? irl3 to irl0 =b'1001 h'320 * 3 6 ? ? irl3 to irl0 =b'1010 h'340 * 3 5 ? ? irl3 to irl0 =b'1011 h'360 * 3 4 ? ? irl3 to irl0 =b'1100 h'380 * 3 3 ? ? irl3 to irl0 =b'1101 h'3a0 * 3 2 ? ? irl3 to irl0 =b'1110 h'3c0 * 3 1 ? ? tmu tmu_suni h'6c0 0 to 15 (0) iprd (11 to 8) ? table 8.4 interrupt exception handling sources and priority (irl mode) 272 ? ? ? ? ? ? rev. 3.00 jan. 18, 2008 page 1404 of 1458 rej09b0033-0300 item page revision (see manual for details) amended name i/o function rd/ wr o read/write signal connects to we pins when sdram or byte-selection sram is connected. rd o read strobe (read data output enable signal) a strobe signal to indicate the memory read cycle when the pcmcia is used. wait i external wait input (sampled at the falling edge of ckio) refout o bus mastership request signal for refreshing section 9 bus state controller (bsc) 9.2 input/output pins table 9.1 pin configuration 283, 284 9.3.2 shadow area 285 changed the bsc decodes a28 to a25 of the physical address and generates chip select signals that correspond to areas 0, 2 to 4, 5a, 5b, 6a, and 6b. amended bit bit name initial value r/w description 31 to 16 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 9.4.1 common control register (cmncr) 291 rev. 3.00 jan. 18, 2008 page 1405 of 1458 rej09b0033-0300 item page revision (see manual for details) changed bit bit name description 30 29 28 iww2 iww1 iww0 idle cycles between write-read cycles and write-write cycles ? 000: no idle cycle ? 9.4.2 csn space bus control register (csnbcr) 294 added bit r/w description 10 9 8 7 r/w r/w r/w r/w ? specify the number of wait cycles that are necessary for read or write access. ? 9.4.3 csn space wait control register (csnwcr) (1) normal space, byte-selection sram ? cs0wcr, cs6bwcr ? cs2wcr, cs3wcr ? cs4wcr ? cs5awcr ? cs5bwcr ? cs6awcr added bit bit name description ? cs4wcr ? cs5awcr ? cs5bwcr 18 17 16 r/w r/w r/w ? specify the number of cycles that are necessary for write access. 000: the same cycles as wr3 to wr0 setting (read or write access wait) rev. 3.00 jan. 18, 2008 page 1406 of 1458 rej09b0033-0300 item page revision (see manual for details) amended bit bit name r/w description 12 ? r reserved this bit is always read as 0. the write value should always be 0. 11 rfsh r/w refresh control specifies whether or not the refresh operation of the sdram is performed. 0: no refresh 1: refresh 9.4.4 sdram control register (sdcr) 326 9.5.5 sdram interface (10) low-frequency mode deleted 9.5.7 byte-selection sram interface figure 9.34 wait timing for byte- selection sram (bas = 1) (software wait only) 390 changed t2 ckio a25 to a0 tf th t1 tw figure 9.36 example of connection with 16-bit data-width byte-selection sram 391 changed 64kx16bit sram a15 a0 cs oe we i/o15 i/o0 ub lb 9.5.8 pcmcia interface (1) basic timing for memory card interface 395 changed if all 32 mbytes of the memory space are used as an ic memory card interface, the reg signal that switches between the common memory and attribute memory can be generated by an i/o port. rev. 3.00 jan. 18, 2008 page 1407 of 1458 rej09b0033-0300 item page revision (s ee manual for details) changed channel name pin name i/o 0 dma transfer request dreq0 input dma transfer request reception dack0 output dma transfer end tend0 output 1 dma transfer request dreq1 input dma transfer request reception dack1 output dma transfer end tend1 output section 10 direct memory access controller (dmac) 10.2 input/output pins table 10.1 pin configuration 409 section 10 direct memory access controller (dmac) 10.4.2 dma transfer requests (3) 428 added ?.transfer request signals comprise the transmit data empty transfer request and receive data full transfer request from the adc set by chcr0 to chcr5 and the scif0, scif1, mmc, usbf, sim, siof0, siof1, and sdhi set by dmars0/1/2,?. these conditions also apply to the siof1, mmc, usbf, sim, siof0, siof1, and sdhi?.. table 10.18 example of bsc ordinary memory access (no wait, idle cycle 1, longword access to 16-bit device) 447 amended ckio csn wen wait rd address data t1 t2 taw t1 t2 note: the dack is asserted for the last transfer unit of the dma transfer. when the transfer unit is divided into several bus cycles and the csn is negated between bus cycles, the dack is also divided. dackn (active-low) 10.5 usage notes 10.5.2 notes on the cases when dack is divided 448 section 10.5.2 added rev. 3.00 jan. 18, 2008 page 1408 of 1458 rej09b0033-0300 item page revision (see manual for details) section 11 clock pulse generator (cpg) 11.1 features 453 deleted ? clocks for specific modules generated: in addition to i , p , and b , two other clocks, usbh/usbf clock (u ), can be generate d for specific modules. u is a clock input from an external pin. table 11.1 pin configuration 457 amended note: to prevent device malf unction, the value of the mode control pin is sampled only upon a power- on reset. 11.3 clock operating modes 458 changed mode 0: ?? the frequency of ckio ranges from 24.00 to 66.67 mhz, because the input clock frequency ranges from 24.00 to 66.67 mhz. section 11 clock pulse generator (cpg) 11.4.1 frequency control register (frqcr) 461 changed ?frqcr is initialized by a power-on reset, but not initialized by a power-on reset at the wdt overflow. frqcr retains its value in a manual reset and in standby mode. deleted bit bit name description 15 pll2en pll2 enable pll2en specifies whether make the pll circuit 2 on in clock operating mode 7. when the pll circuit 2 is necessary to output the usbh/usbf clock, pll2en makes the circuit on. the pll circuit 2 is on in non-clock operating mode 7 regardless of the pll2en setting. 0: pll circuit 2 is off 1: pll circuit 2 is on 461 rev. 3.00 jan. 18, 2008 page 1409 of 1458 rej09b0033-0300 item page revision (see manual for details) changed bit bit name description 7 6 5 usscs2 usscs1 usscs0 source clock select these bits select the source clock. 000: clock stopped 001: setting prohibited 010: setting prohibited 011: initial value (to run the usbh/usb, however, change the setting to "110: extal_usb" or "111: usb crystal resonator".) 100: setting prohibited 101: setting prohibited 110: extal_usb 111: usb crystal resonator 11.4.2 usbh/usbf clock control register (uclkcr) 464 11.6 usage notes 466 notes 4 and 5 added. changed mode transition conditions canceling procedure software standby mode execute sleep instruction with stby bit in stbcr set to 1 ? interrupt (nmi, irq (edge detection), rtc, tmu, pint ? reset section 13 power-down modes 13.1 features table 13.1 states of power-down modes 478 changed pin name abbreviation i/o status 1 output status1 output status 0 output status0 chip active ca input 13.2 input/output pins table 13.2 pin configuration 479 rev. 3.00 jan. 18, 2008 page 1410 of 1458 rej09b0033-0300 item page revision (see manual for details) amended and notes added bit bit name description 7 ? reserved this bit is always read as 0. the write value should always be 0. 6 mstp56 module stop bit 56 when the mstp56 bit is set to 1, the supply of the clock to the sdhi is halted. 0: clock supply to sdhi halted 1: sdhi operates note: on the models not having the sdhi, this bit is reserved and is always read as 0. the write value should always be 0. 2 mstp52 module stop bit 52 when the mstp52 bit is set to 1, the supply of the clock to the ssl is halted. 0: ssl operates 1: clock supply to ssl halted note: on the models not having the ssl, this bit is reserved. the write value should always be 1. 13.3.5 standby control register 5 (stbcr5) 486 13.5 software standby mode 13.5.2 canceling software standby mode 489, 490 changed software standby mode is canceled by interrupts (nmi, irq (edge detection), rtc, tmu, and pint) or a reset. (1) canceling with interrupt the on-chip wdt can be used for hot starts. when the chip detects an nmi, irq (edge detection) * 1 , rtc * 1 , tmu * 1 , or pint * 1 interrupt,? notes: 1. only when the rtc is used, software standby mode can be canceled by irq (edge detection), rtc, tmu, or pint interrupt. rev. 3.00 jan. 18, 2008 page 1411 of 1458 rej09b0033-0300 item page revision (see manual for details) 13.8 hardware standby mode 13.8.1 transition to hardware standby mode 496 deleted after entering software standby mode by the sleep instruction, this lsi enters hardware standby mode by driving the ca pin low. section 13 power-down modes figure 13.12 timing when power of pins other than vcc_rtc and vccq_rtc is off 498 amended ca status power supply other than vcc_rtc and vccq_rtc resetp rtc protection normal * 3 standby* 2 undefined reset * 1 normal * 3 specification: checking the standby state of the status pin 0 to 10 bcyc * 4 0 to 30 bcyc notes: * 1 reset: hh (status1 = high, status0 = high) * 2 standby: lh (status1 = low, status0 = high) * 3 normal operation: ll (status1 = low, status0 = low) * 4 bcyc: bus clock cycle changed channel name pin name i/o 0 tpu compare match output 0 tpu_to0 output 1 tpu compare match output 1 tpu_to1 output 2 tpu compare match output 2a tpu_to2 output tpu clock input 2a tpu_ti2a input tpu clock input 2b tpu_ti2b input 3 tpu compare match output 3a tpu_to3 output tpu clock input 3a tpu_ti3a input tpu clock input 3b tpu_ti3b input section 15 16-bit timer pulse unit (tpu) 15.2 input/output pins table 15.2 tpu pin configurations 514 section 15 16-bit timer pulse unit (tpu) 15.4.4 pwm modes 536 amended conditions of duty 0% and 100% are shown below. ? duty 0%: the set value of the duty register (tgra) is tgrb + 1 for the period register(tgrb). ? duty 100%: the set value of the duty register (tgra) is 0. rev. 3.00 jan. 18, 2008 page 1412 of 1458 rej09b0033-0300 item page revision (see manual for details) changed channel pin name abbreviation 0 scif0_sck sck scif0_rxd rxd scif0_txd txd scif0_cts cts * 2 scif0_rts rts * 2 section 18 serial communication interface with fifo (scif) table 18.1 pin configuration 588 18.5 interrupt sources and dmac 635 changed ? set the interrupt enable bits (tie, rie) that correspond to the interrupt sources used for activation of the dmac. clear the other interrupt enable bits (tsie, erie, brie, and drie) to 0. changed name pin name abbreviation irda receive data irrx irrx irda transmit data irtx irtx section 19 infrared data association module (irda) 19.2 input/output pins table 19.1 pin configuration 640 section 19.3 infrared data association module (irda) 19.3.1 irda mode register (scimr) 641 added note: recommended value of irda changed name pin name abbreviation iic clock iic_scl scl iic data i/o iic_sda sda section 20 i 2 c bus interface (iic) 20.2 input/output pins table 20.1 i 2 c bus interface pins 648 rev. 3.00 jan. 18, 2008 page 1413 of 1458 rej09b0033-0300 item page revision (see manual for details) changed bit bit name description 3 stop stop condition detection flag [setting conditions] ? in master mode: when a stop condition is detected after frame transfer is completed ? in slave mode: when a stop condition is detected after the address set in sar matches the salve address that comes as the first byte after the detection of a start condition [clearing condition] ? when 0 is written in stop after reading stop = 1 20.3.5 i 2 c bus status register (icsr) 656 20.7 usage notes 677 changed the falling edge of the ninth clock is recognized by checking the sclo bit in the i 2 c bus control register 2 (iccr2). section 21 serial i/o with fifo (siof) 679 deleted this lsi includes a clo ck-synchronized serial i/o module with fifo (siof) that comprises two channels. the siof can perform serial communication with a serial peripheral interface bus (spi). 21.1 features 679 spi mode deleted. 21.2 input/output pins table 21.1 pin configuration 681 all descriptions related to spi mode deleted. 21.3 register descriptions 682 spi c ontrol register (spicr) deleted. rev. 3.00 jan. 18, 2008 page 1414 of 1458 rej09b0033-0300 item page revision (see manual for details) changed bit bit name description 15 14 13 tfwm2 tfwm1 tfwm0 ? ? a transfer request to the transmit fifo is issued by the tdreq bit in sistr. ? the transmit fifo is always used as 16 stages of the fifo regardless of these bit settings. 7 6 5 rfwm2 rfwm1 rfwm0 ? ? a transfer request to the receive fifo is issued by the rdreq bit in sistr. ? the receive fifo is always used as 16 stages of the fifo regardless of these bit settings. 21.3.9 fifo control register (sifctr) 701, 702 21.4.7 transmit and receive procedures (1) transmission in master mode 721 figure 21.9 replaced. clear the txe bit in sictr to 0 end set to dis 8 set the fse bit in sictr to 0 set the mssel bit in siscr to 1 set brdv=111 and bprs=00000 in siscr start the setting fse=0, txe=0 and other bit. add pulse (0 1 0) to the txrst in siscr reset the master clock source and baud rate in siscr synchronize this lsi internal frame with fse=0 if restarting transmit later. execute internal initialization of the bit rate generator if restarting transmit later. 'no' requires further setting if transmission is not restarted (no). when returning to the same transmit mode from here, go back to no.4, fse setting, on this flowchart. go to "start" on each flowchart. 9 10 11 12 no ye s change other transmit mode? note: * when interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the txe bit should be set to 1. rev. 3.00 jan. 18, 2008 page 1415 of 1458 rej09b0033-0300 item page revision (see manual for details) (2) reception in master mode 722 figure 21.10 replaced. clear the rxe bit in sictr to 0 set to disa 8 9 10 11 12 end set the fse bit in sictr to 0 set the mssel bit in siscr to 1 set brdv=111 and bprs=00000 in siscr start the setting fse=0, txe=0 and other bit. add pulse (0 1 0) to the rxrst in siscr reset the master clock source and baud rate in siscr synchronize this lsi internal frame with fse=0 if restarting recept later. execute internal initialization of the bit rate generator if restarting recept later. 'no' requires further setting if transmission is not restarted (no). when returning to the same recept mode from here, go back to no.4, fse setting, on this flowchart. go to "start" on each flowchart. no ye s change other transmit mode? table 21.11 transmit and receive reset 725 added note 1 to 4 notes: refer to the following procedure to operate the transmit reset/receive reset. 1. set the master clock source in peripheral clock. (write 1 (master clock = pf (peripheral clock)) to mssel bit in the siscr register). 2. set prescaler count value of the baud rate generator by1/1. (write "00000" (division ratio= 1/1) to the brps bits 4 to 0 in siscr register). 3. set division ratio in borate generator's output level by 1/1. (write "111" (division ratio=1/1) to the brdv bits 2 to 0 in siscr register). 4. reset transmit/receive op eration. (write "1", to reset, to txrst or rxrst bit in the sictr register). 21.4 operation 21.4.10 spi mode deleted 21.5 usage notes 734 added rev. 3.00 jan. 18, 2008 page 1416 of 1458 rej09b0033-0300 item page revision (see manual for details) changed name pin name i/o usb1 power enable/pull-up control pin usb1_pwr_en/ usbf_uplup output usb2 power enable pin usb2_pwr_en output usb1 overcurrent /monitor pin usb1_ovr_current / usbf_vbus input usb2 overcurrent pin usb2_ovr_current input section 23 usb pin multiplex controller 23.2 input/output pins table 23.3 pin configuration (power control signal) 757 23.4 examples of external circuit 23.4.1 example of the connection between usb function controller and transceiver 759 changed the usbf_vbus pin is multiplexed with the usb1_ovr_current pin, and writing 1 to bit 0 (usb_sel) of utrctl selects the usbf_vbus pin functions. 23.5 usage notes 23.5.3 handling of usb power supply deleted section 24 usb host controller (usbh) 24.1 features 765 added ? support 127 endpoints control in maximum ? possible to use only the sdram area of area 3 as transmit data and discriptor. rev. 3.00 jan. 18, 2008 page 1417 of 1458 rej09b0033-0300 item page revision (see manual for details) amended pin name pin name i/o function usb1 power enable/pull-up control pin usb1_pwr_en output usb port 1 power enable control usb2 power enable pin usb2_pwr_en output usb port 2 power enable control usb1 overcurrent/m onitor pin usb1_ovr_current / usbf_vbus input usb port 1 over- current detect/ usb cable connection monitor pin usb2 overcurrent pin usb2_ovr_current input usb port 2 over- current detect usb external clock extal_usb input connect a crystal resonator for usb. alternatively, an external clock (48 mhz) may be input for usb. usb crystal xtal_usb output connect a crystal resonator for usb. 24.2 input/output pins table 24.1 pin configuration 766 24.7 usage notes 801 note 1 changed as below, and note 2 added. 1. when using the usb host controller, the bus clock (b ) must be set to 32 mhz or higher. the peripheral clock (p ) must also be set to a higher frequency than 13 mhz. 2. usage notes on resume operation 801 section name changed rev. 3.00 jan. 18, 2008 page 1418 of 1458 rej09b0033-0300 item page revision (see manual for details) section 25 usb function controller (usbf) 25.1 features 803 deleted ? supports self - powered mode changed name pin name i/o function usb1 overcurrent/m onitor pin usb1_ovr_current / usbf_vbus input usb port 1 over- current detection/ usb cable connection monitor pin usb external clock extal_usb input connect a crystal resonator for usb. alternatively, an external clock (48 mhz) may be input for usb. usb crystal xtal_usb output connect a crystal resonator for usb. usb1 power enable/pull-up control pin usb1_pwr_en/us bf_uplup output usb port 1 power enable control/ pull-up control output pin 2p pin usb2_p i/o d + 2m pin usb2_m i/o d ? section 25 usb function controller (usbf) 25.2 input/output pins table 25.1 pin configuration and functions 805 25.3 register description 25.3.1 interrupt flag register 0 (ifr0) 25.3.2 interrupt flag register 1 (ifr1) 25.3.3 interrupt flag register 2 (ifr2) 25.3.4 interrupt flag register 3 (ifr3) 25.3.5 interrupt flag register 4 (ifr4) 808, 810, 811, 813, 815 amended shown below is the revised explanation in section 25.3.1. the same change has been made to sections 25.3.2 to 25.3.5 when each flag is set to 1 and the interrupt is enabled in the corresponding bit of ier0, an interrupt request is generated from the int pin as specified by the corresponding bit in isr0. rev. 3.00 jan. 18, 2008 page 1419 of 1458 rej09b0033-0300 item page revision (see manual for details) 25.3.6 interrupt select register 0 (isr0) 25.3.7 interrupt select register 1 (isr1) 25.3.8 interrupt select register 2 (isr2) 25.3.9 interrupt select register 3 (isr3) 25.3.10 interrupt select register 4 (isr4) 816, 817, 818 amended shown below is the revised explanation in section 25.3.6 (above the table). the same change has been made to sections 25.3.7 to 25.3.10 (only the register names differ: isr0 isr1 to isr4 and interrupt flag register 0 interrupt flag register 1 to 4). isr0 selects the interrupt r equests to the intc to be indicated in interrupt flag register 0. when a bit in isr0 is cleared to 0, the corresponding interrupt is requested as a usbfi0 interrupt. when a bit is set to 1, the corresponding interrupt is requested as a usbfi1 interrupt. with the initial value, each of the interrupt source flags in the interrupt flag register 0 is selected as a usbfi0 interrupt. 25.3.11 interrupt enable register 0 (ier0) 25.3.12 interrupt enable register 1 (ier1) 25.3.13 interrupt enable register 2 (ier2) 25.3.14 interrupt enable register 3 (ier3) 25.3.15 interrupt enable register 4 (ier4) 818, 819, 820, changed shown below is the revised explanation in section 25.3.11. the same change has been made to sections 25.3.12 to 25.3.15 (only t he register name differs: interrupt select register 0 interrupt select register 1 to 4). when an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, the interrupt request set in the interrupt select register 0 is issued. 25.3.31 dma transfer setting register (dma) 826 corrected the usb1_pwr_en pin level can be controlled by the bit 2. changed bit bit name initial value r/w description 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 25.3.36 control register 0 (ctlr0) 830 rev. 3.00 jan. 18, 2008 page 1420 of 1458 rej09b0033-0300 item page revision (see manual for details) 25.5 ep4 isochronous-out transfer figure 25.14 ep4 isochronous- out transfer operation (sof is normal) figure 25.15 ep4 isochronous- out transfer operation (sof is broken) 849, 890 all ?intn? in the figures ch anged to ?interrupt request?. 25.6 ep5 isochronous-in transfer figure 25.16 ep5 isochronous-in transfer operation (sof is normal) figure 25.17 ep5 isochronous-in transfer operation (sof in broken) 852, 853 all ?intn? in the figures ch anged to ?interrupt request?. 25.9 usage notes 25.9.7 note on clock frequency 861 section 25.9.7 added. section 26 lcd controller 863 representat ions of the bus clock and peripheral clock are changed from bck and pck to b and p , respectively. 26.1 features 863 corrected ? supports the selection of data formats (the endian setting for bytes, packed pixel method) by register settings. 26.3 register description 26.3.1 lcdc input clock register (ldickr) 867 added this lcdc can select the bus clock (b ), the peripheral clock (p ), or the external clock (lcd_clk) as its operation clock source. 26.3.10 lcdc horizontal character number register (ldhcnr) 880 deleted notes: 1. the values set in hdcn and htcn must satisfy the relationship of htcn hdcn. also, the total number of characters of htcn must be an even number. (the set value will be an odd number, as it is one less than the actual number.) rev. 3.00 jan. 18, 2008 page 1421 of 1458 rej09b0033-0300 item page revision (see manual for details) table 26.3 limits on the resolution of ro tated displays, burst length, and connected memory (32-bit sdram) 901 changed note: set the data of the number of line specified as burst length that can be stored in address of sdram same as that of row. 26.5 clock and lcd data signal examples figure 26.21 clock and lcd data signal example (tft color 12-bit data bus module) deleted. section 27 a/d converter 27.1 features 929 amended ? high-speed conversion ? minimum conversion time: 15 s per channel (p = 33 mhz operation) changed pin name abbreviation i/o function analog power supply pin avcc input analog power supply and reference voltage for a/d conversion analog ground pin avss input analog ground adc analog input pin 0 an0 input analog inputs adc analog input pin 1 an1 input adc analog input pin 2 an2 input adc analog input pin 3 an3 input adc external trigger pin adtrg input external trigger input for starting a/d conversion 27.2 input pins table 27.1 pin configuration 931 27.3 register description 27.3.1 a/d data registers a to d (addra to addrd) 932 added each addr is initialized to h'0000 by a reset and the module standby function and in standby mode. 27.3.2 a/d control/status registers (adcsr) 933 added adcsr is initialized to h'0000 by a reset and the module standby function and in standby mode. rev. 3.00 jan. 18, 2008 page 1422 of 1458 rej09b0033-0300 item page revision (see manual for details) 27.4 operation 27.4.1 single mode 936 steps 1 and 9 added; step 8 partially deleted. 1. start the clock supply to the adc module (clear the mstp33 bit in stbcr3 to 0) to run the adc module. ? 8. execution of the a/d in terrupt handling routine ends. then, when the adst bit is set to 1, a/d conversion starts and steps 2 to 7 are executed. 9. stop the clock supply to the adc module (set the mstp33 bit in stbcr3 to 1) to place the adc in the module standby state. 27.4.2 multi mode 938 steps 1 and 7 added (same as steps 1 and 9 above). 27.4.3 scan mode 940 steps 1 and 8 added (same as steps 1 and 9 above); step 7 partially deleted and changed. ? 7. steps 3 to 5 are repeat ed as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again fro m the first channel (an0). ? table 27.3 a/d conversion time (single mode) 943 added note: values in the table ar e numbers of states (tcyc) for p . 27.7 usage notes 27.7.1 notes on a/d conversion 27.7.2 notes on a/d conversion- end interrupt and dma transfer 946 to 948 added rev. 3.00 jan. 18, 2008 page 1423 of 1458 rej09b0033-0300 item page revision (s ee manual for details) 27.7.5 setting analog input voltage 949 deleted operating the chip in exce ss of the following voltage range may result in damage to chip reliability. ? analog input voltage range: during a/d conversion, the voltages (vann) input to the analog input pins ann should be in the range av ss vann av cc (n = 0 to 3). ? the relationship between av cc , av ss and v cc q , v ss q should satisfy v cc q - 0.3 v av cc v cc q + 0.3 v and av ss = v ss q . even when the a/d converter is not used, make sure that av cc is connected to vccq and av ss is connected to vssq . section 28 d/a converter (dac) 28.5 usage note 28.5.1 handling of the analog power supply pins deleted section 29 pc card controller (pcc) 29.1.1 pcmcia support (1) continuous 32-mbyte area mode 959 changed ?.when an address of 32 mbytes or less is accessed, set 0 in popa25. this bit does not affect access to attribute memory space or i/o memory space. (2) continuous 16-mbyte area mode 961 changed and deleted ?.in the common memory space, set the pc card address in bit 2 (p0pa25) and bit 1 (p0pa24) of the general control register to access each address space of 16 mbytes unit. by this operation, values are output to a25 and a24 pins, enabling an address space of more than 16 mbytes specified by p0pa24 to be accessed (initial value: 0 for p0pa25) . rev. 3.00 jan. 18, 2008 page 1424 of 1458 rej09b0033-0300 item page revision (s ee manual for details) changed pin name abbreviation i/o pcc wait request pcc_wait input pcc 16-bit input/output pcc_iois16 input pcc ready pcc_rdy input pcc battery detection 1 pcc_bvd1 input pcc battery detection 2 pcc_bvd2 input pcc card detection 1 pcc_cd1 input pcc card detection 2 pcc_cd2 input pcc voltage detection 1 pcc_vs1 input pcc voltage detection 2 pcc_vs2 input pcc space indication pcc_reg output pcc buffer control pcc_drv output pcc reset pcc_reset output 29.2 input/output pins table 29.2 pcc pin configuration 962 29.3 register description 963 pin description changed [before change] [after change] ? pcc_rdy ( ireq ) rdy/ bsy ? pcc_iois16 (wp) wp ? pcc_vs2 vs2 ? pcc_vs1 vs1 ? pcc_cd2 cd2 ? pcc_cd1 cd1 rev. 3.00 jan. 18, 2008 page 1425 of 1458 rej09b0033-0300 item page revision (s ee manual for details) amended bit bit name description 7 p0rdy/ ireq pcc0 ready the value on the rdy/ bsy pin of the pc card connected to area 6 is re ad when the ic memory card interface is connected. the value of ireq pin of the pc card connected to area 6 is read when the i/o card interface is connected. this bit cannot be written to. 0: indicates that the value of rdy/ bsy is 0 when the pc card connected to area 6 is an ic memory card interface type. the value of rdy/ bsy is 0 when the pc card connected to area 6 is the i/o card interface type. 1: indicates that the value of pcc_rdy ( ireq ) is 1 when the pc card connected to area 6 is the ic memory card interface type. the value of pcc_rdy ( ireq ) is 1 when the pc card connected to area 6 is the i/o card interface type. 6 p0mwp pcc0 write protect the value of wp of the pc card connected to area 6 is read when the ic me mory card interface is connected. 0 is re ad when the i/o card interface is connected. this bit cannot be written to. 0: indicates that the value of wp is 0 when the pc card connected to area 6 uses the ic memory card interface type. the value of bit 6 is always 0 when the pc card connected to area 6 is the i/o card interface type. 1: indicates that the value of wp is 1 when the pc card connected to area 6 is the ic memory card interface type. 29.3.1 area 6 interface status register (pcc0isr) 964 changed bit bit name description 1 p0bvd 2/ p0spk r 0 p0bvd 1/ p0sts chg pcc0 battery voltage detect 2 and 1 the values of bvd1 and bvd2 pin of the pc card connected to area 6 are read when the ic memory card interface is connected. the values of stschg and spkr pin of the pc card connected to area 6 are read when the i/o card interface is connected. these bits cannot be written to. (1) and (2) added 29.3.1 area 6 interface status register (pcc0isr) 965 rev. 3.00 jan. 18, 2008 page 1426 of 1458 rej09b0033-0300 item page revision (see manual for details) 29.5 usage notes (2) pin function control and card type switching 985 changed ?.also, the card status change register (pcc0cscr) must be cleared after the setting has been made. however, this restriction does not apply to the card detection pins ( cd1 and cd2 ). changed name abbreviation i/o sim data sim_d * i/o sim clock sim_clk output sim reset sim_rst output section 30 sim card module (sim) 30.2 input/output pins table 30.1 pin configuration 989 1033 changed rsptyr specifies command format in conjunction with cmdtyr. bits rty2 to rty0 are used to specify the number of response bytes, and bits rty5 and rty4 are used to make additional settings. 1033 bit 6 changed to a reserved bit. 31.3.3 response type register (rsptyr) 1033 note: checking of crc by rty4 and rty6 is not checking the command response crc error bit but checking the command response crc. this checking is not performed for the crc of the r2 command response in mmc mode. rev. 3.00 jan. 18, 2008 page 1427 of 1458 rej09b0033-0300 item page revision (see manual for details) * deleted and note changed. rsptyr cmd index 6 5 4 2 to 0 cmd2 * 101 cmd3 * 100 cmd4 000 cmd7 1 * 100 cmd9 * 101 cmd10 * 101 table 31.2 correspondence between commands and settings of cmdtyr and rsptyr 1034, 1035 notes: ? * of rty4 and rty6 : set 1 after checking crc in command response. ? deleted ? this setting is ignored by the stream transfer command in mmc mode stream. before executing a command with data read in the multiblock transfer, 16 or more bytes should be set. bit bit name description 3 2 1 0 c3 c2 c1 c0 transfer data block size before executing a command with data transfer, 4 or more bytes should be set before. note that the c3 to c0 bits should be set to 0000 when forcible erase is performed by the cmd42 command. 0000: 1 byte ?. 31.3.4 transfer byte number count register (tbcr) 1036 rev. 3.00 jan. 18, 2008 page 1428 of 1458 rej09b0033-0300 item page revision (see manual for details) changed bit bit name initial value r/w 7 to 5 ? all 0 ? 4 to 0 rsprd all 0 r/w 31.3.7 response registers 0 to 16 and d (rspr0 to rspr16 and rsprd) 1040 amended bit bit name description 2 crceri crc error flag [setting condition] when a crc error for command response or receive data, and crc status error for transmission data response are detected while crcerie = 1. for any non-r2 command response, crc is checked when the rty4 in rsptyr is set for enabling. for the r2 command response, crc is not checked; therefore, this flag is not set. [clearing condition] write 0 after reading crceri = 1. note: when the crc error occurs, halt the command sequence by setting the cmdoff bit to 1. 31.3.14 interrupt status registers 0 and 1 (intstr0 and intstr1) 1051 31.3.15 transfer clock control register (clkon) 1053 changed the 33-mhz peripheral clock is needed, and bits csel3 to csel0 should be set to 0001 for a 16.5- mbps transfer clock of the mmcif. changed bit bit name description 7 clkon clock on 0: stops the transfer clock output from the clk/sclk pin. 1: outputs the transfer clock from the clk/sclk pin. 1053 rev. 3.00 jan. 18, 2008 page 1429 of 1458 rej09b0033-0300 item page revision (see manual for details) 31.3.19 dma control register (dmacr) 1055 restrictions added set this register before executing a multiblock transfer command (cmd18 or cmd25). auto mode cannot be used for open-ended multiblock transfer. 1059 deleted ?in this case, the transfer clock of clkon should be divided by 100 and the transfer clock frequency should be set sufficiently slow. 31.4 operation 31.4.1 operations in mmc mode (1) operation of broadcast commands corrected and deleted the individual mmc compares its cid and data on the mmc_cmd, and if different, aborts cid output. a single mmc in which the cid can be entirely output enters the acknowledge state. when the r2 response is necessary, ctocr should be set to h'01. (4) operation of commands without data transfer 1062 corrected for a command that is related to time-consuming processing such as flash memory write/erase, the mmc indicates the data busy state via the mmc_dat. ? ? whether the data busy state is entered or not is determined by the dtbusy bit in cstr. ? figure 31.5 example of command sequence for commands without data transfer (with data busy state) 1064 changed (busy) (req) command sequence execution period data busy period (dtbusy_tu) (dtbusy) rev. 3.00 jan. 18, 2008 page 1430 of 1458 rej09b0033-0300 item page revision (see manual for details) (4) operation of commands without data transfer figure 31.6 operational flowchart for commands without data transfer 1065 changed write 1 to cmdstrt write 1 to cmdoff crceri interrupt generated? * r1b response? dbsyi interrupt generated? dtbusy detected? ye s ye s ye s ye s ye s ye s no no no no no no crpi interrupt generated? command sequence end cteri interrupt generated? note * : for the r2 command response, no crc check is performed by hardware. therefore, perform crc checking by software to see if there is an error. 1066 changed ? the end of the command se quence is detected by polling the busy flag in cstr or by the data transfer end flag (dti) or the multiblock transfer (pre-defined) end flag (bti). (5) commands with read data 1067 added note: in multiblock transfer, if you terminate the command sequence (by writing 1 in the cmdoff bit) before the command response reception is completed (crpi = 1), the command response cannot be received correctly. to receive a command response, continue the command sequence (by setting the rd_conti bit to 1) until the reception of the command response is completed. rev. 3.00 jan. 18, 2008 page 1431 of 1458 rej09b0033-0300 item page revision (see manual for details) figure 31.11 operational flowchart for commands with read data (single block transfer) 1071 changed command sequence end read response register read data from fifo fifo clear write 1 to cmdoff write 1 to rd_conti read data from fifo write 1 to cmdoff ye s no ye s no ye s no ye s ye s no no ye s no ye s no cap len - cap n(ffi) is response status normal? is dteri interrupt generated? is crceri interrupt generated? is dteri interrupt generated? is dti interrupt generated? is ffi interrupt generated? * block length (byte) len: cap: n(ffi): fifo size (byte) the number of feis from the start of read sequence note: * figure 31.12 operational flowchart for commands with read data (open-ended multiblock transfer) (2) 1073 changed no ye s cap len (1 + n(dti)) - cap n(ffi) * (6) commands with write data figure 31.15 example of command sequence for commands with write data (block size fifo size) 1078 changed (cwre) (busy) (dtbusy_tu) (dtbusy) (req) single block write command execution sequence (fifo_empty) figure 31.19 operational flowchart for commands with write data (single block transfer) 1082 changed execute cmd24 (cmdr to cmdstrt) read response register is crpi interrupt generated? is cteri interrupt generated? ye s ye s ye s ye s no no no is response status normal? does cmd16 end successfully? is crceri interrupt generated? ye s no rev. 3.00 jan. 18, 2008 page 1432 of 1458 rej09b0033-0300 item page revision (see manual for details) figure 31.21 operational flowchart for commands with write data (pre-defined multiblock transfer) (1) 1085 corrected ye s no is crceri interrupt generated? figure 31.21 operational flowchart for commands with write data (pre-defined multiblock transfer) (2) 1086 corrected (arrow deleted) is drpi interrupt generated? is dtbusy detected? tbncr = n(drpi)? is bti interrupt generated? ye s ye s ye s ye s no no no no notes: 1. write data of block length when block length fifo size, data of fifo size when block length > fifo size. 31.5 operations using dmac figure 31.25 operational flowchart for read sequence (pre-defined multiblock transfer) (1) 1093 corrected set the number of transfer blocks to tbncr figure 31.27 operational flowchart for pre-defined multiblock read transfer in auto mode (1) 1096 corrected write the number of transfer blocks to tbncr 31.5.2 operation of write sequence figure 31.29 operational flowchart for write sequence (open-ended multiblock transfer) (2) 1102 changed write 1 to cmdoff set dmacr to h'00 write 1 to cmdoff fifo clear write 1 to cmdoff no ye s is next block written? command sequence end execute cmd12 execute cmd12 rev. 3.00 jan. 18, 2008 page 1433 of 1458 rej09b0033-0300 item page revision (see manual for details) figure 31.30 operational flowchart for write sequence (pre-defined multiblock transfer) (2) 1104 changed write 1 to cmdoff set dmacr to h'00 write 1 to cmdoff fifo clear write 1 to cmdoff ye s no is bti interrupt generated? command sequence end execute cmd12 figure 31.31 operational flowchart for write sequence (stream write transfer) 1105 changed write 1 to daten set dmacr (mmcif) ye s no is frdyi interrupt generated or does dma transfer end? 31.5.2 operation of write sequence figure 31.32 operational flowchart for pre-defied multiblock write transfer in auto mode (1) 1106 changed set dmac read response register is cteri interrupt generated? ye s ye s ye s no no is crceri interrupt generated? ye s no no is response status normal? ye s does cmd23 end successfully? [1] [2] set dmacr (mmcif) execute cmd25 (cmdr to cmdstrt) is crpi interrupt generated? figure 31.32 operational flowchart for pre-defied multiblock write transfer in auto mode (2) 1107 changed write 1 to cmdoff set dmacr to h'00 write 1 to cmdoff fifo clear write 1 to cmdoff command sequence end execute cmd12 rev. 3.00 jan. 18, 2008 page 1434 of 1458 rej09b0033-0300 item page revision (see manual for details) section 34 pin function controller (pfc) 1141 added note: the signals related to the sdhi can be selected only on the models that include them. added and changed port port function (related module) other function (related module) e pte6 input (port) afe_rxin input (afeif)/iic_scl input/output (iic) pte5 input (port) afe_rdet input (afeif)/iic_sda input/output (iic) f ptf0 input (port) adtrg input (adc) t ptt4 input/output (port) scif0_cts input (scif)/tpu_to1 output (tpu) ptt3 input/output (port) scif0_rts output (scif)/tpu_to0 output (tpu) ptt2 input/output (port) scif0_txd output (scif)/irtx output (irda) ptt1 input/output (port) scif0_rxd input (scif)/irrx input(irda) ptt0 input/output (port) scif0_sck input/output (scif) u ptu4 input/output (port) siof1_sync input/output (siof)/sd_dat2 input/output (sdhi) ptu3 input/output (port) siof1_mclk input (siof)/sd_dat1 input/output (sdhi)/ tpu_ti3b input (tpu) ptu2 input/output (port) mmc_dat input/output (mmc)/ siof1_txd output (siof)/sd_dat0 input/output (sdhi)/ tpu_ti3a input (tpu) ptu1 input/output (port) mmc_cmd input/output (mmc)/ siof1_rxd input (siof)/sd_cmd input/output (sdhi)/ tpu_ti2b input (tpu) ptu0 input/output (port) mmc_clk output (mmc)/ siof1_sck input/output (siof)/sd_clk output (sdhi)/ tpu_ti2a input (tpu) table 34.1 multiplexed pins 1142, 1144, 1145 rev. 3.00 jan. 18, 2008 page 1435 of 1458 rej09b0033-0300 item page revision (see manual for details) added and changed port port function (related module) other function (related module) v ptv4 input/output (port) mmc_vddon output (mmc)/ scif1_cts input (scif)/ lcd_vepwc output (lcdc)/tpu_to3 output (tpu) ptv2 input/output (port) sim_d input/output (sim)/scif1_txd output (scif)/sd_cd input (sdhi) ptv1 input/output (port) sim_rst output (sim)/scif1_rxd input (scif)/ sd_wp input (sdhi) ptv0 input/output (port) sim_clk output (sim)/scif1_sck input/output (scif)/sd_dat3 in put/output (sdhi) table 34.1 multiplexed pins 1145 changed bit bit name description 1 0 pf0md1 pf0md0 pf0 mode 00: other functions (see table 34.1.) 01: reserved 10: port input (pull-up mos: on) 11: port input (pull-up mos: off) 34.1.6 port f control register (pfcr) 1155 rev. 3.00 jan. 18, 2008 page 1436 of 1458 rej09b0033-0300 item page revision (see manual for details) deleted and amended bit bit name description 15 14 pselc15 pselc14 mmc_clk/siof1_sck/sd_clk/tpu_t i2a select as ptu0 other functions 00: select siof1_sck 01: select tpu_ti2a 10: select mmc_clk 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_clk when pselb0 = 1 13 12 pselc13 pselc12 mmc_cmd/siof1_rxd/sd_cmd/tpu_ ti2b select as ptu1 other functions 00: select siof1_rxd 01: select tpu_ti2b 10: select mmc_cmd 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_cmd when pselb0 = 1 11 10 pselc11 pselc10 sim_rst/scif1_rxd/sd_wp select as ptv1 other functions 00: select scif1_rxd 01: reserved 10: select sim_rst 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_wp when pselb0 = 1 34.1.21 pin select register c (pselc) 1174, 1175 9 8 pselc9 pselc8 sim_d/scif1_txd/sd_cd select as ptv2 other functions 00: select scif1_txd 01: reserved 10: select sim_d 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_cd when pselb0 = 1 rev. 3.00 jan. 18, 2008 page 1437 of 1458 rej09b0033-0300 item page revision (s ee manual for details) amended bit bit name description 14 13 pseld14 pseld13 mmc_dat/siof1_txd/sd_dat0/tpu_ ti3a select as ptu2 other functions 00: select siof1_txd 01: select tpu_ti3a 10: select mmc_dat 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_dat0 when pselb0 = 1 10 9 pseld10 pseld9 siof1_mclk/sd_dat1/tpu_ti3b select as ptu3 other functions 00: select siof1_mclk 01: select tpu_ti3b 10: reserved 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_dat1 when pselb0 = 1 6 5 pseld6 pseld5 siof1_sync/sd_dat2 select as ptu4 other functions 00: select siof1_sync 01: reserved 10: reserved 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_dat2 when pselb0 = 1 34.1.22 pin select register d (pseld) 1176, 1177 2 1 pseld2 pseld1 sim_clk/scif1_sck/sd_dat3 select as ptv0 other functions 00: select scif1_sck 01: reserved 10: select sim_clk 11: select according to pselb0 setting reserved when pselb0 = 0 select sd_dat3 when pselb0 = 1 rev. 3.00 jan. 18, 2008 page 1438 of 1458 rej09b0033-0300 item page revision (see manual for details) section 35 i/o ports 35.5 port e figure 35.5 port e 1187 changed port e pte6 (input)/afe_rxin (input)/iic_scl (input/output) pte5 (input)/ afe_rdet (input)/iic_sda (input/output) pte4 (input/output) / ldc_m_disp (output) pte3 (input/output) / ldc_cl1 (output) pte2 (input/output) / ldc_cl2 (output) pte1 (input/output) / ldc_don (output) pte0 (input/output) / ldc_flm (output) 1188 added and changed separate tables have been provided for conditions n = 0 to 4 and n = 5 and 6. deleted pecr state penmd1 penmd0 pin state read write 0 0 other function pedr value value is written to pedr, but does not affect pin state. 1 reserved ? ? 1 0 input (pull - up mos on) pin state value is writte n to pedr, but does not affect pin state. 1 input (pull- up mos off) pin state value is written to pedr, but does not affect pin state. 35.5.2 port e data register (pedr) table 35.5 port e data register (pedr) read/write operations 1189 note: n= 5 or 6 35.6 port f figure 35.6 port f 1190 changed port f ptf6 (input) / da1 (output) ptf5 (input) / da0 (output) ptf4 (input) / an3 (input) ptf3 (input) / an2 (input) ptf2 (input) / an1 (input) ptf1 (input) / an0 (input) ptf0 (input)/ adtrg (input) 35.6.2 port f data register (pfdr) 1191 deleted pfdr is a register that stores data for pins ptf6 to ptf0. bits pf6dt to pf0dt correspond to pins ptf6 to ptf0. when the function is general input port, if the port is read, the corresponding pin level is read. ? rev. 3.00 jan. 18, 2008 page 1439 of 1458 rej09b0033-0300 item page revision (see manual for details) changed pfcr state pfnmd1 pfnmd0 pin state read write 0 1 reserved ? ? table 35.6 port f data register (pfdr) read/write operations 1191 35.16 port t figure 35.16 port t 1211 changed port t ptt4 (input/output) / scif0_cts (input) / tputo1 (output) ptt3 (input/output) / scif0_rts (output) / tputo0 (output) ptt2 (input/output) / scif0_txd (output) / irtx (output) ptt1 (input/output) / scif0_rxd (input) / irrx (input) ptt0 (input/output) / scif0_sck (input/output) section 36 user debugging interface (h-udi) 36.3 register descriptions 1220 added id register (sdid) shift register 36.3.3 shift register 1221 added shift register is a 32-bit register. the upper 16-bits are set in sdir at update-ir. if shifted in, the shift-in valu e is shift out after the value of the 32-bit shift register is shifted out. 36.3.4 boundary scan register (sdbsr) 1221 changed sdbsr is a 434-bit shift register, located on the pad, for controlling the ? rev. 3.00 jan. 18, 2008 page 1440 of 1458 rej09b0033-0300 item page revision (s ee manual for details) changed bit pin name i/o 395 rd/ wr out 389 we1 / dqmlu / we out 354 rd/ wr control 348 we1 / dqmlu / we control 194 scif0_rxd/irrx/ptt1 in 193 scif0_txd/irtx/ptt2 in 155 scif0_rxd/irrx/ptt1 out 154 scif0_txd/irtx/ptt2 out 117 scif0_rxd/irrx/ptt1 control 116 scif0_txd/irtx/ptt2 control table 36.3 pins and boundary scan register bits 1222, 1225, 1226, 1227 deleted and changed` bit bit name description 31 to 0 did31 to did0 device id31 to id0 device id register that is stipulated by jtag. h'002f200f (initial value) for this sh7720 group. h'002f2447 (initial value) for this SH7721 group. upper four bits may be changed by the chip version. sdidh corresponds to bits 31 to 16. sdidl corresponds to bits 15 to 0. 36.3.5 id register (sdid) 1230 rev. 3.00 jan. 18, 2008 page 1441 of 1458 rej09b0033-0300 item page revision (s ee manual for details) amended and the following registers deleted: spi control register_0 (spicr_0) spi control register_1 (spicr_1) register name abbreviati on number of bits address module acces s size interrupt request register 9 irr9 8 h'a408 0028 8 interrupt request register 10 irr10 8 h'a408 002a 8 interrupt request register 0 irr0 8 h'a414 0004 8 sdram mode register sdmr3 ? h'a4fd5x xx 16 port a data register padr 8 h'a405 0140 i/o port 8 section 37 list of registers 37.1 register addresses 1238, 1240, 1253 port b data register pbdr 8 h'a405 0142 8 rev. 3.00 jan. 18, 2008 page 1442 of 1458 rej09b0033-0300 item page revision (see manual for details) amended and spicr_0 and spicr_1 deleted. register abbreviation bit 31/23/ 15/7 bit 30/22/ 14/6 bit 29/21/ 13/5 bit 28/20/ 12/4 bit 27/19/ 11/3 bit 26/18/ 10/2 bit 25/17/ 9/1 bit 24/16/ 8/0 module iprg scif0 scif1 intc ? ? ? ? ? ? ? ? iprh pinta pintb irr9 pccir usbhir ? cmir ? usbfi1 r usbfi0 r ? irr0 ? tmu_ sunir irq5r irq4r irq3r irq2r irq1r irq0r irr1 ? ? ? ? dei3r dei2r dei1r dei0r irr2 ? ? ? sslir ? ? ? lcdcir iprd ? ? tmu (tmu_sun1) cmncr ? bsd ? map block dprty 1 dprty 0 dmaiw 2 sdcr ? ? deep ? rfsh rmode pdown bactv bsc cvr cnfv1 cnfv0 intv1 intv0 ? altv2 altv1 altv0 usbf ctlr0 ? ? ? rwups rsme ? asce ? tsrh ? ? ? ? ? d10 d9 d8 cmdtyr ? ty6 ty5 ty4 ty3 ty2 ty1 ty0 mmc rsptyr ? ? rty5 rty4 rty3 rty2 rty1 rty0 rspr16 rspr 167 rspr 166 rspr 165 rspr 164 rspr 163 rspr 162 rspr 161 rspr 160 mmc rsprd ? ? ? rsprd 4 rsprd 3 rsprd 2 rsprd 1 rsprd 0 pacr pa7md 1 pa7md 0 pa6md 1 pa6md 0 pa5md 1 pa5md 0 pa4md 1 pa4md 0 pfc pecr ? ? pe6md 1 ? pe5md 1 ? pe4md 1 pe4md 0 pe3md 1 pe3md 0 pe2md 1 pe2md 0 pe1md 1 pe1md 0 pe0md 1 pe0md 0 pselb pselb 15 pselb 14 pselb 13 pselb 12 pselb 11 pselb 10 pselb9 pselb8 ? ? ? ? ? ? ? pselb0 padr pa7dt pa6dt pa5dt pa4dt pa3dt pa2dt pa1dt pa0dt i/o port 37.2 register bits 1256 to 1288 pjdr ? pj6dt pj5dt pj4dt pj3dt pj2dt pj1dt pj0dt rev. 3.00 jan. 18, 2008 page 1443 of 1458 rej09b0033-0300 item page revision (see manual for details) amended, and spicr_0 and spicr_1 deleted. register abbreviation power-on reset * 1 manual reset * 1 software standby module standby sleep module irr9 initialized initialized retained ? retained intc irr10 initialized initialized retained ? retained irr0 initialized initialized retained ? retained uclkcr initialized retained retained ? retained cpg mclkcr initialized retained retained ? retained frqcr initialized * 6 retained retained ? retained wtcnt initialized * 6 retained retained ? retained wdt wtcsr initialized * 6 retained retained ? retained scimr initialized initialized retained retained retained irda(sci f0) addra initialized initialized initialized initialized retained adc addrb initialized initialized initialized initialized retained addrc initialized initialized initialized initialized retained addrd initialized initialized initialized initialized retained adcsr initialized initialized initialized initialized retained dadr0 initialized initialized retained retained retained dac padr initialized retained retained ? retained i/o port 37.3 register states in each operating mode 1289 to 1304 notes: ???.. 5. changes according to the status of the pc card. 6. not initialized by a power-on reset due to the wdt. changed item sym bol min. typ. max. unit test conditions analog (a/d, d/a) power supply voltage av cc 3.0 3.3 3.6 v when not in use, connect to v cc q. analog usb power supply voltage av cc _ usb 3.0 3.3 3.6 v when not in use, connect to v cc q. i cc ? 230 300 ma v cc = 1.5v i = 133 mhz current consumpt ion norm al opera tion i cc q ? 60 80 ma v cc q, v cc q1 = 3.3 v b = 66 mhz section 38 electrical characteristics 38.3 dc characteristics table 38.4 dc characteristics (1) [common] 1309, 1310 rev. 3.00 jan. 18, 2008 page 1444 of 1458 rej09b0033-0300 item page revision (s ee manual for details) table title amended added and deleted item symb ol min. typ. max. unit test conditions ptf5 to ptf6 v ih 2.2 ? av cc + 0.3 v an0/ p tf1 to an3/ p tf4 2.0 ? av cc + 0.3 v input high voltage other input pins 2.2 ? v cc q + 0.3 v ptf5 to ptf6 v il ? 0.3 ? av cc 0.2 v an0/ p tf1 to an3/ p tf4 ? 0.3 ? av cc 0.2 v table 38.4 dc characteristics (2- a) [except usb transceiver, i 2 c, adc, and dac analog related pins] 1311 input low voltage other input pins ? 0.3 ? v cc q 0.2 v table 38.4 dc characteristics (2- c) [usb transceiver related pins] 1313 notes: 2. av cc _usb should satisfy the condition v cc q av cc _usb and be supplied between av cc _usb and av ss _usb. changed item symbol min. unit resetp pulse width t respw 20 * 3 tcyc* 2 * 4 resetm pulse width t respw 20 * 3 tcyc* 2 * 4 38.4.2 control signal timing table 38.8 control signal timing 1319 38.4.3 ac bus timing table 38.9 bus timing 1322 changed conditions: clock mode 0, v cc q = 2.7 to 3.6 v, ? rev. 3.00 jan. 18, 2008 page 1445 of 1458 rej09b0033-0300 item page revision (s ee manual for details) figures 38.14 to 38.19 1326 to 1331 the description of "asynchronous" deleted from the figure title 38.4.6 sdram timing 1349 to 1352 figures 38.37 to 38.40 in rev 2.00 removed figure 38.39 pcmcia memory card interface bus timing 1351 changed rd/ wr rd t rwd1 t rwd1 t rsd t rdh1 t rsd figure 38.40 pcmcia memory card interface bus timing (ted[3:0] = b'0010, teh[3:0] = b'0001, software wait 1, hardware wait 1) 1352 changed rd/ wr rd d15 to d0 t rwd1 t rwd1 t rsd t rds1 t rdh1 read t rsd 38.4.8 peripheral module signal timing table 38.10 peripheral module signal timing 1355 changed conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = ?20 to 75c 38.4.9 16-bit timer pulse unit (tpu) table 38.11 16-bit timer pulse unit 1356 changed conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = -20 to 75c note: * peripheral clock (p ) cycle. 38.4.10 rtc signal timing table 38.12 rtc signal timing 1357 changed conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = -20 to 75c rev. 3.00 jan. 18, 2008 page 1446 of 1458 rej09b0033-0300 item page revision (s ee manual for details) changed and deleted conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = -20 to 75c module item symb ol min . scif rts delay time t rtsd ? cts setup time (clock time) t ctss 100 cts hold time (clock time) t ctsh 100 38.4.11 scif module signal timing table 38.13 scif module signal timing 1358 figure 38.51 scif input/output timing in synchronous mode 1359 figure title amended 38.4.13 siof module signal timing table 38.15 siof module signal timing 1362 changed conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = -20 to 75c 38.4.14 afeif module signal timing table 38.16 afeif module signal timing 1365 changed conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = -20 to 75c note: t pcyc is a cycle time (ns) of a peripheral clock (p ). changed and deleted item symbol min. max. unit figure extal_usb clock frequency (48 mhz) t freq 47.9 48.1 mhz 38.60 clock rise time t r48 ? 6 ns clock fall time t f48 ? 6 ns duty (t high /t low ) t duty 90 110 % 38.4.15 usb module signal timing table 38.17 usb module clock timing 1366 rev. 3.00 jan. 18, 2008 page 1447 of 1458 rej09b0033-0300 item page revision (s ee manual for details) 38.4.16 lcdc module signal timing table 38.20 lcdc module signal timing 1368 conditions added conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = -20 to 75c changed conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = -20 to 75c item symbol min. max. sim_clk clock cycle t smcyc 2 x tpcyc 16 x tpcyc 38.4.17 sim module signal timing table 38.21 sim module signal timing 1369 38.4.18 mmcif module signal timing table 38.22 mmcif module signal timing 1370 changed conditions: v cc q = 2.7 to 3.6 v, v cc q1 = 2.7 to 3.6 v or 1.65 to 1.95 v, v cc = 1.4 to 1.6 v, av cc = 3.0 to 3.6 v, ta = -20 to 75c 38.4.19 h-udi related pin timing table 38.23 h-udi related pin timing 1372 conditions: vccq = vccq_rtc = 2.7 to 3.6 v, vccq1 = 2.7 to 3.6 v or 1.65 to 1.95 v, vcc = vcc_pll1 = vcc _pll2 = vcc_rtc = 1.4 to 1.6 v, avcc = avcc_usb = 3.0 to 3.6 v, ta = -20 to 75c table 38.24 and 38.25 1374 condition changed [before change] avcc = 3.3 0.3v [after change] avcc = 3.0 to 3.6 v 38.7 ac characteristic test conditions 1375 changed ? input pulse level: vccq to vssq, vccq1 to vssq1 rev. 3.00 jan. 18, 2008 page 1448 of 1458 rej09b0033-0300 item page revision (see manual for details) changed category plbg 0256ga-a plbg 0256ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins a17 a16 an0/ptf1 z z/i z/z z/z i/i i/i pull-up b13 e16 usb2_pwr_en /pth1 z o/p o/k z/z o/p o/io pull-up b16 a17 usb2_m z * 2 l z z i io pull-down b17 a18 usb1_p z * 1 z * 1 z z i io open b18 a21 usb1_m z * 1 z * 1 z z i io open c14 e17 adtrg /ptf0 v i/p z/k z/z i/p i/i open c16 d16 usb2_p z * 2 l z z i io pull-down c19 b20 usb1_ovr_current /usbf_vbus i i/i i/i i/i i/i i/i pull-down d17 a19 usb1d_dmns / pint11/ afe_rlycnt /pcc_bvd2/ ptg3 z i/i/o/i/p i/i/o/z/p z/z/z/z/z i/i/o/i/p i/i/o/i/io pull-up h18 h17 sim_rst/scif1_ rxd/ sd_wp/ptv1 z o/z/i/p z/z/z/k z/z/z/z o/i/i/p o/i/i/io pull-up k17 l20 scif0_txd/irtx/p tt2 v z/z/p z/z/k z/z/z o/o/p o/o/io open l17 l21 scif0_rxd/irrx/ ptt1 v z/z/p z/z/k z/z/z i/i/p i/i/io open l18 m20 irq3/ irl3 /ptp3 v i/i/p i/i/k z/z/z i/i/p i/i/io open n18 p20 audata2/ptj3 x o/p o/k z/z o/p o/io open n19 n18 audata1/ptj2 x o/p o/k z/z o/p o/io open n20 r17 audata3/ptj4 x o/p o/k z/z o/p o/io open p4 r5 vss ? ? ? ? ? ? p17 p21 vcc ? ? ? ? ? ? p18 r20 audata0/ptj1 x o/p o/k z/z o/p o/io open p19 p18 audck/ptj6 v o/p o/k z/z o/p o/io open p20 t17 vssq ? ? ? ? ? ? r1 p4 vccq1 ? ? ? ? ? ? r2 t2 a11 o o oz z z o open r3 r2 a13 o o oz z z o open appendix a. pin states table a.1 pin states 1377 to 1384 r4 r1 a15 o o oz z z o open rev. 3.00 jan. 18, 2008 page 1449 of 1458 rej09b0033-0300 item page revision (see manual for details) changed category plbg 0256ga-a plbg 0256ka-a pin name power- on reset manual reset software standby hardware standby bus release i/o handling of unused pins r17 t20 audsync /ptj0 x o/p o/k z/z o/p o/io open r18 r21 asemd0 i i i i i i pull-up r19 r18 trst /ptl7 i i/p z/k z/z i/p i/io pull-down r20 u17 vccq ? ? ? ? ? ? t1 t5 a16 o o oz z z o open t2 v1 a6 o o oz z z o open t3 v2 a5 o o oz z z o open t4 t1 a12 o o oz z z o open t17 u20 tms/ptl6 i i/p z/k z/z i/p i/io pull-up t18 t18 tck/ptl3 i i/p z/k z/z i/p i/io pull-up t19 u21 pcc_reset /pint7/ptk3 v o/i/p o/i//p z/z/z o/i//p o/i/io open t20 v18 asebrkak /ptj5 v o/p o/k z/z o/p o/io open u1 r4 vssq1 ? ? ? ? ? ? u2 t4 a9 o o oz z z o open u3 w1 a4 o o oz z z o open u4 aa3 a10 o o oz z z o open u5 y5 d11 z z z z z io pull-up u6 y6 d8 z z z z z io pull-up u19 v21 pcc_rdy/pint6/ ptk2 v i/i/p z/i/p z/z/z i/i/p i/i/io open v15 y19 dreq0 /pint0 /ptm6 v i/i/p z/i/p z/z/z i/i/p i/i/io open v19 aa21 pcc_vs2 /pint5/ ptk1 v i/i/p z/i/p z/z/z i/i/p i/i/io open w2 aa2 a2 o o oz z z o open w3 aa1 a1 o o oz z z o open appendix a. pin states table a.1 pin states 1384 to 1387 w19 y21 pcc_vs1 /pint4/ ptk0 v i/i/p z/i/p z/z/z i/i/p i/i/io open rev. 3.00 jan. 18, 2008 page 1450 of 1458 rej09b0033-0300 item page revision (see manual for details) table a.1 pin states 1388 t able notes changed and added. notes: * 1 the conditions for setting usb1_p and usb1_m to z (open) are as follows: ? * 2 after negation of resetp, usb2_p and usb2_m go low after tens of extal_usb clock cycles have been input. table a.1 pin states 1389 t able legends deleted and added. b: input buffer on, output buffer on x: undefined b. product lineup 1390, 1391 table of product lineup replaced rev. 3.00 jan. 18, 2008 page 1451 of 1458 rej09b0033-0300 index numerics 16-bit timer pulse unit (tpu)................. 511 16-bit/32-bit di splacement....................... 55 a a/d converter ......................................... 929 absolute addresses ................................... 55 acknowledge .......................................... 661 address array.......................................... 198 address space identifier (asid)............. 173 address transition ................................... 172 address-array read.................................. 209 address-array write (associative ope ration) ............................ 210 address-array write (non-associative operation)..................... 209 afe interface.......................................... 750 analog front end interface (afeif) ....... 735 area division........................................... 285 asynchronous mode ............................... 613 auto-reload count operation ................... 506 auto-request mode ................................ 426 b baud rate generator................................. 709 big endian......................................... 52, 331 bit synchronous circuit ........................... 676 boundary sc an ...................................... 1234 buffer operation...................................... 534 burst mode.............................................. 440 bus state controller (bsc) ...................... 279 c cache ...................................................... 197 clock synchronous mode ........................ 607 compare match timer (cmt) ................. 547 control registers........................................ 42 control transfer ....................................... 839 cpu........................................................... 37 cycle-steal mode..................................... 439 d d/a converter (dac) ............................. 953 daa interface......................................... 752 data array................................................ 198 data-array read........................................ 210 data-array write ...................................... 211 delayed branching .................................... 54 direct memory access controller (dmac).................................................. 407 double data transfer instructions (movx.w, movy.w) .......................... 101 dsp operating unit.................................... 81 dsp operation instructions...................... 118 dsp registers..................................... 88, 113 dual address mode.................................. 435 e exception handling ................................. 217 exception hand ling state ........................... 37 extension of status register (sr)............... 85 external request mode............................. 426 f fixed mode ............................................. 431 free-running operation............................ 555 rev. 3.00 jan. 18, 2008 page 1452 of 1458 rej09b0033-0300 g general registers ....................................... 42 global base register (gbr) ...................... 50 h h-udi interrupt .................................... 1233 h-udi reset .......................................... 1233 i i/o ports................................................ 1179 i 2 c bus format......................................... 660 i 2 c bus interface (iic) ............................ 645 infrared data association module (irda) 639 instruction length...................................... 54 intermittent mode ................................... 439 interrupt controller (intc)..................... 243 irq interrupts......................................... 266 j jtag .................................................... 1217 l lcd controller (lcdc) ......................... 863 lcd module power-supply states .......... 914 lcdc module signal timing................. 1368 literal co nstant ......................................... 55 little endian...................................... 53, 331 load/store architecture ............................. 54 logical address space ............................. 168 low-power consum ption state.................. 37 lru ........................................................ 199 m manual reset ................................... 227, 479 memory management unit (mmu)......... 165 mmc mode........................................... 1058 mmu ...................................................... 165 modem control........................................ 623 module standby function ........................ 491 modulo addressing.................................. 108 modulo register (mod)............................ 86 multi mode.............................................. 938 multimediacard interface (mmcif) ..... 1027 multiple virtual memory mode ............... 173 multiply and accumulate registers (mach/macl) ....................................... 46 n nmi interrupt.......................................... 266 noise canceller....................................... 670 notes on display-off mode (lcdc stopped)...................................... 915 o on-chip peripheral module request mode ........................................... 428 one-shot operation.................................. 554 p p0, p3, and u0 areas ............................... 168 p0/u0 area ................................................ 39 p1 area .............................................. 39, 168 p2 area .............................................. 39, 169 p3 area ...................................................... 39 p4 area .............................................. 40, 169 pc card controller (pcc) ........................ 957 phase counting mode .............................. 539 physical address space ............................ 172 power-down modes................................. 477 power-on reset ................................ 227, 479 power-supply control sequences............. 910 rev. 3.00 jan. 18, 2008 page 1453 of 1458 rej09b0033-0300 prefetch hit.............................................. 207 prefetch miss........................................... 207 procedure register (pr)............................. 46 processing modes ..................................... 38 program counter ....................................... 42 pwm modes ........................................... 536 r read hit................................................... 207 read miss................................................ 207 realtime cloc k (rtc)............................. 559 registers acdr ....................746, 1246, 1275, 1297 actr ....................737, 1246, 1275, 1296 adcsr..................933, 1250, 1282, 1300 addr....................932, 1250, 1282, 1300 asdr ....................746, 1246, 1276, 1297 astr.....................740, 1246, 1275, 1296 bamra ..............1114, 12 52, 1286, 1302 bamrb........................ 1117, 1252, 1302 bara ..................1113, 1252 , 1285, 1302 barb ..................1116, 1252 , 1285, 1302 basra................1125, 12 52, 1286, 1302 basrb ................1126, 12 52, 1286, 1302 bbra ..................1114, 1252 , 1286, 1302 bbrb ..................1119, 1252 , 1285, 1302 bdmrb...............1118, 12 52, 1285, 1302 bdrb ..................1117, 1252 , 1285, 1302 betr...................1124, 1252, 1285, 1302 brcr ..................1120, 1252 , 1285, 1302 brdr ..................1125, 1252, 1286, 1302 brsr...................1124, 1252, 1285, 1302 ccr1 .....................200 , 1238, 1 255, 1289 ccr2 .....................201 , 1238, 1 255, 1289 ccr3 .....................204 , 1238, 1 255, 1289 chcr ....................413, 1240, 1262, 1291 clkon ...............1053, 1251, 1283, 1301 cmcnt .................553, 1243, 1269, 1293 cmcor.................553, 1243, 1269, 1293 cmcsr................. 551, 1243, 1269, 1293 cmdr................. 1037, 1250, 1283, 1300 cmdstrt.......... 1040, 12 50, 1283, 1301 cmdtyr ........... 1031, 1251, 1284, 1301 cmncr ................ 291, 1239, 1257, 1290 cmstr................. 550, 1243, 1269, 1293 csnbcr................ 294, 1239, 1258, 1290 csnwcr .............. 299, 1239, 1259, 1290 cstr .................. 1045, 1251, 1283, 1301 ctlr0 .................. 830, 1248, 1280, 1298 ctlr1 .................. 831, 1248, 1280, 1299 ctocr ............... 1043, 1251, 1283, 1301 cvr ...................... 828, 1248, 1280, 1298 dacr ................... 955, 1250, 1282, 1300 dadr ................... 954, 1250, 1282, 1300 dar...................... 412, 1240, 1261, 1290 dasts.................. 825, 1248, 1280, 1298 dma ..................... 826, 1248, 1280, 1298 dmacr.............. 1055, 1252, 1284, 1302 dmaor................ 418, 1240, 1264, 1291 dmars ................ 420, 1241, 1264, 1291 dmatcr ............. 412, 1240, 1261, 1291 dpnq.................... 745, 1246, 1275, 1296 dr....................... 1054, 1252, 1284, 1302 dtoutr ............ 1044, 1252, 1284, 1302 epdr0i ................. 821, 1247, 1279, 1298 epdr0o ................ 821, 1247, 1279, 1298 epdr0s................. 821, 1247, 1279, 1298 epdr1 .................. 822, 1247, 1279, 1298 epdr2 .................. 822, 1247, 1279, 1298 epdr3 .................. 822, 1248, 1279, 1298 epdr4 .................. 823, 1248, 1279, 1298 epdr5 .................. 823, 1248, 1279, 1298 epir...................... 831, 1248, 1280, 1299 epstl0................. 827, 1248, 1280, 1298 epstl1................. 828, 1248, 1280, 1298 epsz0o ................. 823, 1248, 1280, 1298 epsz1 ................... 824, 1248, 1280, 1298 epsz4 ................... 824, 1248, 1280, 1298 expevt ............... 219, 1238, 1256, 1289 rev. 3.00 jan. 18, 2008 page 1454 of 1458 rej09b0033-0300 fclr0 ...................825, 1248, 1280, 1298 fclr1 ...................826, 1248, 1280, 1298 fifoclr.............1055, 12 52, 1284, 1302 frqcr..................461, 1241, 1265, 1291 gbr...................................................... 50 iccr1....................649, 1245, 1272, 1295 iccr2....................650, 1245, 1272, 1295 icdrr...................658, 1245, 1273, 1295 icdrs ................................................ 658 icdrt ...................658, 1245, 1273, 1295 icier.....................653, 1245, 1272, 1295 icmr.....................651, 1245, 1272, 1295 icr0 ......................249, 1239, 1257, 1290 icr1 ......................250, 1239, 1257, 1289 icsr ......................655, 1245, 1272, 1295 ier0.......................818, 1247, 1279, 1298 ifr0.......................808, 1247, 1279, 1297 intcr ................1047, 1251, 1252, 1283, .......................................1284, 1301, 1302 intevt.................219, 1238, 1256, 1289 intevt2...............220, 1238, 1256, 1289 intstr ..............1049, 1251, 1252, 1283, .......................................1284, 1301, 1302 ipr.........................247, 1239, 1257, 1290 irr0 ......................252, 1238, 1257, 1289 isr0.......................816, 1247, 1279, 1298 ldaclnr ............885, 1249, 1281, 1299 ldcntr ...............892, 1249, 1282, 1299 lddfr..................871, 1249, 1281, 1299 ldhcnr...............880, 1249, 1281, 1299 ldhsynr ............881, 1249, 1281, 1299 ldickr ................867, 1248, 1280, 1299 ldintr ................886, 1249, 1281, 1299 ldlaor...............877, 1249, 1281, 1299 ldlirnr..............896, 1249, 1282, 1300 ldmtr .................868, 1248, 1280, 1299 ldpalcr.............878, 1249, 1281, 1299 ldpmmr..............889, 1249, 1282, 1299 ldpr.....................879, 1248, 1280, 1299 ldpspr ................891, 1249, 1282, 1299 ldsarl............... 876, 1249, 1281, 1299 ldsaru .............. 875, 1249, 1281, 1299 ldsmr................. 873, 1249, 1281, 1299 lduintlnr........ 895, 1249, 1282, 1300 lduintr............. 893, 1249, 1282, 1299 ldvdlnr ........... 882, 1249, 1281, 1299 ldvsynr ........... 884, 1249, 1281, 1299 ldvtlnr............ 883, 1249, 1281, 1299 mach .................................................. 46 macl................................................... 46 mmucr ............... 175, 1238, 1255, 1289 moder.............. 1031, 1251, 1284, 1301 opcr.................. 1041, 1251, 1283, 1301 padr.................. 1180, 1253, 1287, 1303 pbdr.................. 1182, 1253, 1287, 1303 pcc0cscier....... 972, 1250, 1282, 1300 pcc0cscr........... 969, 1250, 1282, 1300 pcc0gcr............. 966, 1250, 1282, 1300 pcc0isr............... 963, 1250, 1282, 1300 pcdr.................. 1184, 1253, 1287, 1303 pddr.................. 1186, 1253, 1288, 1303 pedr .................. 1188, 1253, 1288, 1303 pfdr .................. 1191, 1253, 1288, 1303 pgdr.................. 1194, 1253, 1288, 1303 phdr.................. 1196, 1253, 1288, 1303 pinter ................ 264, 1239, 1257, 1290 pjdr ................... 1198, 1253, 1288, 1303 pkdr.................. 1200, 1253, 1288, 1303 pldr .................. 1202, 1253, 1288, 1303 pmdr ................. 1204, 1253, 1288, 1303 ppdr .................. 1206, 1253, 1288, 1303 pr ......................................................... 46 prdr.................. 1208, 1253, 1288, 1303 psdr .................. 1210, 1253, 1288, 1303 psela ................ 1171, 1253, 1287, 1303 pselb ................ 1173, 1253, 1287, 1303 pselc ................ 1174, 1253, 1287, 1303 pseld ................ 1176, 1253, 1287, 1303 ptdr .................. 1212, 1253, 1288, 1303 pteh .................... 174, 1238, 1255, 1289 rev. 3.00 jan. 18, 2008 page 1455 of 1458 rej09b0033-0300 ptel......................175, 1238, 1255, 1289 pudr ..................1214, 1253, 1288, 1304 pvdr ..................1216, 1253, 1288, 1304 r64cnt ................563, 1243, 1270, 1294 rcnt ....................746, 1246, 1275, 1297 rcr1 .....................575 , 1244, 1 271, 1294 rcr2 .....................577 , 1244, 1 271, 1294 rcr3 .....................579 , 1244, 1 271, 1294 rdayar ..............573, 1244, 1271, 1294 rdaycnt............568, 124 4, 1271, 1294 rdfp .....................747, 1246, 1276, 1297 rhrar .................571, 1244, 1271, 1294 rhrcnt ...............566, 1243, 1271, 1294 rminar ...............570, 1244, 1271, 1294 rmincnt.............565, 124 3, 1270, 1294 rmonar..............574, 1244, 1271, 1294 rmoncnt ...........569, 1244, 1271, 1294 rsecar................570, 1244, 1271, 1294 rseccnt .............564, 124 3, 1270, 1294 rspr ...................1038, 1251, 1284, 1301 rsptyr ..............1033, 1251, 1284, 1301 rtcnt ..................329, 1240, 1261, 1290 rtcor..................330, 1240, 1261, 1290 rtcsr ..................328, 1240, 1261, 1290 rwkar ................572, 1244, 1271, 1294 rwkcnt..............567, 1244, 1271, 1294 ryrar .................574, 1244, 1271, 1294 ryrcnt ...............569, 1244, 1271, 1294 sar ........................411, 657, 1240, 1245, ...................1261, 1273, 129 0, 1291, 1295 scbrr .................607, 1244, 1271 , 1272, ................................................ 1294, 1295 scbrr (sim)........991, 125 0, 1283, 1300 scfcr...................609, 1244, 1272, 1295 scfdr ..................612, 1244, 1272, 1295 scfer...................599, 1244, 1271, 1295 scfrdr................590, 1244, 1272, 1295 scftdr ................590, 1244, 1272, 1295 scgrd................1004, 1250, 1283, 1300 scimr...................640, 1245, 1272, 1295 scrdr ............... 1001, 12 50, 1283, 1300 scrsr ................................................ 590 scrsr (sim) ................................... 1001 scsc2r .............. 1003, 1250, 1283, 1300 scscmr ............ 1002, 12 50, 1283, 1300 scscr ................. 595, 1244, 1271, 1272, ................................................ 1294, 1295 scscr (sim) ....... 992, 1250, 1283, 1300 scsmpl ............. 1005, 1250, 1283, 1300 scsmr ................ 591, 1244, 1271, 1272, ................................................ 1294, 1295 scsmr (sim) ...... 990, 1250, 1283, 1300 scssr .................. 600, 1244, 1272, 1295 scssr (sim)........ 995, 1250, 1283, 1300 sctdr (sim)....... 994, 1250, 1283, 1300 sctdsr ............... 613, 1244, 1271, 1295 sctsr ................................................ 590 sctsr (sim)...................................... 994 scwait ............. 1004, 1250, 1283, 1300 sdbpr.............................................. 1220 sdbsr.............................................. 1221 sdcr .................... 325, 1239, 1261, 1290 sdid ................... 1230, 1254, 1288, 1304 sdir ................... 1220, 1254, 1288, 1304 sicdar................ 707, 1245, 1273, 1296 sictr ................... 686, 1245, 1273, 1296 sifctr................. 701, 1245, 1273, 1296 siier .................... 699, 1245, 1273, 1296 simdr.................. 683, 1245, 1273, 1295 sircr................... 692, 1245, 1274, 1296 sirdar................ 706, 1245, 1273, 1295 sirdr................... 690, 1245, 1273, 1296 siscr ................... 703, 1245, 1273, 1295 sistr.................... 693, 1245, 1273, 1296 sitcr ................... 691, 1245, 1274, 1296 sitdar ................ 704, 1245, 1273, 1295 sitdr................... 689, 1245, 1273, 1296 spc ....................................................... 50 sr ......................................................... 48 ssr ....................................................... 50 rev. 3.00 jan. 18, 2008 page 1456 of 1458 rej09b0033-0300 stbcr ..................480, 1241, 1265, 1292 stbcr2 ................481, 1241, 1265, 1292 stbcr3 ................483, 1241, 1265, 1292 stbcr4 ................484, 1241, 1265, 1292 stbcr5 ................486, 1241, 1265, 1292 tbcr...................1036, 1251, 1283, 1301 tbncr................1037, 1251, 1284, 1301 tcnt...........504, 1241, 1265, 1266, 1292 tcor ....................504, 1241, 1265, 1292 tcr .....503, 516, 1241, 1265, 1266, 1292 tdfp .....................747, 1246, 1276, 1297 tea .......................220, 1238, 1256, 1289 tgr .......................526, 1242, 1266, 1292 tier ......................523, 1241, 1266, 1292 tior......................521, 1241, 1266, 1292 tmdr ...................520, 1241, 1266, 1292 tra .......................218, 1238, 1256, 1289 trg .......................824, 1248, 1280, 1298 tsr........................524, 1241, 1266, 1292 tstr ...502, 527, 1241, 1265, 1266, 1292 ttb .......................175, 1238, 1255, 1289 uclkcr...............464, 1241, 1265, 1291 usbhbced..........781, 1247, 1277, 1297 usbhbhed..........780, 1247, 1277, 1297 usbhc..................768, 1246, 1276, 1297 usbhcced..........780, 1247, 1277, 1297 usbhched..........780, 1246, 1277, 1297 usbhcs................771, 1246, 1276, 1297 usbhdhed .........781, 1247, 1277, 1297 usbhfi.................781, 1247, 1278, 1297 usbhfn ...............784, 1247, 1278, 1297 usbhfr................783, 1247, 1278, 1297 usbhhcca .........779, 1246, 1277, 1297 usbhid ................777, 1246, 1276, 1297 usbhie.................776, 1246, 1276, 1297 usbhis.................774, 1246, 1276, 1297 usbhlst .............786, 1247, 1278, 1297 usbhpced ..........779, 1246, 1277, 1297 usbhps ................785, 1247, 1278, 1297 usbhr..................768, 1246, 1276, 1297 usbhrda ........... 787, 1247, 1278, 1297 usbhrdb ........... 789, 1247, 1278, 1297 usbhrps............. 792, 1247, 1279, 1297 usbhrs............... 790, 1247, 1278, 1297 utrctl............... 758, 1246, 1276, 1297 vbr ...................................................... 50 vdcnt............................................. 1054 wtcnt ................ 471, 1241, 1265, 1291 wtcsr................. 471, 1241, 1265, 1291 repeat end regi ster (re)........................... 86 repeat start register (rs) .......................... 86 reset state ................................................. 37 round-robin mode .................................. 431 rtc crystal oscillator circuit .................. 584 s save program counter (spc) .................... 50 save status regi ster (ssr)......................... 50 scan mode............................................... 940 serial communication interface with fifo (scif).................................... 585 serial i/o with fifo (siof)................... 679 setting the display resolution.................. 910 signal-source impedance........................ 948 sim card module (sim).......................... 987 single address mode ............................... 437 single data transfer instructions.............. 102 single mode ............................................ 936 single virtual me mory mode................... 173 slave address .......................................... 661 sleep mode.............................................. 488 smart card interface .............................. 1007 software standby mode........................... 489 stall operations ....................................... 856 start cond ition......................................... 661 status register (sr) ................................... 48 stop cond ition ......................................... 661 synonym pr oblem................................... 186 system control instructions..................... 103 rev. 3.00 jan. 18, 2008 page 1457 of 1458 rej09b0033-0300 system registers........................................ 42 t t bit .......................................................... 55 tap controller ...................................... 1231 timer unit (tmu)................................... 499 transfer rate............................................ 659 u usb function controller (usbf) ............ 803 usb host controller (usbh) .................. 765 usb pin multiplex controller.................. 755 user break controller (ubc) ................ 1111 user debugging inte rface (h-udi)...... 1217 uxy area.................................................. 171 v vector base register (vbr)....................... 50 w watchdog timer (wdt) .......................... 469 write hit .................................................. 207 write miss ............................................... 208 x x/y memory ........................................... 213 rev. 3.00 jan. 18, 2008 page 1458 of 1458 rej09b0033-0300 renesas 32-bit risc microcomputer hardware manual sh7720 group, SH7721 group publication date: rev.1.00, jun. 28, 2007 rev.3.00, jan. 18, 2008 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2008. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7858/7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2377-3473 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 3518-3399 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, m alaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.2 sh7720 group, SH7721 group hardware manual |
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